CN109582986A - A kind of method of network on three-dimensional chip test port selection optimization under power consumption limit - Google Patents
A kind of method of network on three-dimensional chip test port selection optimization under power consumption limit Download PDFInfo
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- CN109582986A CN109582986A CN201710902018.4A CN201710902018A CN109582986A CN 109582986 A CN109582986 A CN 109582986A CN 201710902018 A CN201710902018 A CN 201710902018A CN 109582986 A CN109582986 A CN 109582986A
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Abstract
A kind of method of network on three-dimensional chip test port selection optimization under power consumption limit, computer communication technology is transplanted in IC design by network-on-chip, it architecturally efficiently solves the problems, such as multi-core communication, and there is good spatial spread and parallel communications ability.The method that the present invention proposes test port selection optimization under a kind of power consumption limit, so as to shorten the testing time.Test port logarithm is determined with system power dissipation, Internet resources are occupied at least with kernel test and the testing time is most short for target, to be tested core selection port position.Using cloud evolution algorithm to different port position grouping optimizing, the optimal test port combination of adaptive value is rapidly converged to, completes Study on Test Method, it improves testing efficiencies, shorten the testing time, reduce test cost.
Description
Technical field
The present invention relates to the ports of network-on-chip design more particularly to network-on-chip to select optimization design.
Background technique
With increasing for electronics applications type, whether high-performance computing sector or equipment of the core network, base station with
And all to the performance of processor, more stringent requirements are proposed for individual mobile communication terminal.It was promoted in the past by improving chip dominant frequency
The method of processor performance has faced physics bottleneck, and multi-core technology gradually becomes the inexorable trend of high performance chips development.Cause
This provides efficient interconnection communication system for numerous processor cores of extensive system on chip and becomes more and more important.Network-on-chip
Computer communication technology is transplanted in IC design by (Network-on-Chip, NoC), is architecturally effectively solved
Multi-core communication of having determined problem, and there is good spatial spread and parallel communications ability.With the rapid development of NoC technology,
The integrated nucleus number of on piece is continuously increased, the NoC (2D-NoC) of conventional two-dimensional framework can not fundamentally avoid global wires it is too long,
The problems such as wiring delay, power dissipation overhead.Then NoC (the three dimensional network-on- of three-dimension-framework is proposed
Chip, 3D-NoC) solve these relevant issues.2D-NoC is packaged into a three-dimensional structure by 3D-NoC, and layer can be adopted with interlayer
With through silicon via (through silicon vias, TSV) technology in histogram to interconnection, TSV is the realization for constructing 3D-NoC structure
Provide effective approach.In addition, line between layers is wanted compared with the line inside layer by way of three-dimensional interconnection
Much shorter, therefore faster clock rate can be reached, network throughput is improved, delay is reduced.
Since the structure process of 3D-NoC is more complicated, test becomes urgent problem to be solved.NoC kernel test can lead to
Concurrent testing is crossed to reduce the testing time.But parallel port is excessive, and it is excessive to will lead to testing power consumption, when being more than system nominal power
When, the breaking-up of unrepairable can be brought.Parallel port is very few or the selection of test port position is unreasonable, and the testing time can mistake
It is long, cause test resource to waste.So test, which must cooperate with, considers test port logarithm and port position.
The selection of NoC kernel test port position is np hard problem, and traditional calculation method is difficult to traverse optimizing.Using cloud into
Changing algorithm has good randomness and steady tendency, is capable of degree and the search range of self adaptive control hereditary variation, from
And rapidly converge to optimal solution.The present invention proposes that a kind of test method, this method are evolved based on the cloud of high-precision optimizing and calculated as a result,
Method is completed the selection to 3D-NoC test port and is optimized, reduce the testing time in the case where meeting multiple constraint conditions.
Summary of the invention
The purpose of the present invention is occupy Internet resources and most short testing time with least kernel test to realize three-dimensional plate
The selection of upper network test port optimizes.
The technical solution adopted by the present invention to solve the technical problems is:
Under a kind of power consumption limit cloud of the method based on high-precision optimizing of network on three-dimensional chip test port selection optimization into
Change algorithm, test meets multiple constraint conditions, completes 3D- based on NoC is reused as Test access mechanism and XYZ routing mode
NoC test port placement optimization, obtains the optimal testing time.
The cloud evolution algorithm cloud models theory is combined with natural evolution strategy, is utilized cloud model C (Ex, En, He)
Evolutionary process is described.Wherein Ex is known as it is expected, represents elite seed individual；En is known as evolution entropy, represents the general of transmutation of species
The range of range, En more Big mutation rate is also bigger, otherwise smaller；He is known as super entropy of evolving, and indicates the stability in evolutionary process, He
Bigger stability is smaller, otherwise bigger.By adjust En, He value can well the degree of self adaptive control hereditary variation and
Search range.
The constraint condition are as follows: 1) each tested core need to only be tested once, and test midway cannot stop；2) it is testing
Core occupy Internet resources until test just discharge, before not discharging, other test cores must not occupy；3) in same test
Different test cores on period, it is necessary to avoid test resource conflict, have resource contention that must stop, being waited；4) same
In one testing time section, the total power consumption of all test cores must satisfy system power dissipation limitation；5) in same testing time section, together
The total power consumption of one layer of test core must satisfy this layer of power consumption limit.
The test Test access mechanism is adopted based on the test dispatching scheme test resource distribution of kernel priority to be measured
With non-preemptive allocation strategy, in order to reduce hardware spending additional in test process, test reuses 3D-NoC and visits as test
Ask mechanism, i.e. routing node, routing channel and the TSV Internet resources of recycling 3D-NoC complete test.
The XYZ routing mode be data packet from source node into destination node transmission process, data packet successively to X,
Y, Z-direction is transmitted.
The beneficial effects of the present invention are:
Network on three-dimensional chip test port selection optimization method improves testing efficiency under a kind of power consumption limit, shortens survey
The time is tried, test cost is reduced
Detailed description of the invention
Fig. 1 shows be based on cloud evolution algorithm test port select flow chart
Specific embodiment
One, the test port I/O logarithm: port logarithm n is determinedioDetermine that formula isWherein: PmaxTable
Show system maximum power dissipation；PtotalIndicate test total power consumption；nioIt indicates to allow full test port logarithm under system power dissipation limitation；
N indicates the total input of NoC, output port quantity.
Two, determine test core test I/O port position: use XYZ routing algorithm, routing node with three-dimensional coordinate (x, y,
Z) it indicates, coordinate (xc,yc,zc)、(xi,yi,zi), (xo, yo, zo) respectively indicates core to be measured, test port outputs and inputs position
It sets, is learnt according to routed path: the routing channel number that path is passed through: kchannel=| xc-xi|+|xo-xc|+|yc-yi|+|yo-yc
|；Through silicon via number: k is passed through in pathTSV=| zc-zi|+|zo-zc|；The routing node number that path is passed through: krouter=kchannel+1+
kTSV+1.Wherein: kchannel(i)、krouter(i)、kTSV(i) routing channel number, routing node that core i test is passed through are respectively represented
Several and through silicon via number.In every group of port position combination, each there is always so that test is occupied the least survey of Internet resources for tested core
Try port position.
Three, calculate testing power consumption: test process, which must accurately calculate testing power consumption, ensures that test meets power consumption limit.Power consumption
Model isPpass(i)=kchannel(i)×Pchannel+krouter(i)×Prouter
+kTSV(i)×PTSV.Wherein, P (i), Pcore(i)、Ppass(i) test total power consumption, testing power consumption, the test biography of core i are respectively indicated
Defeated power consumption, Prouter、PchannelRespectively indicate transmission power consumption of the test data on routing node, the transmission power consumption on channel.
Four, the limitation of system layer power consumption: layer power consumption limit requires the testing power consumption summation of the resource kernel of same layer to be less than
Every layer of rated disspation:Wherein: P [c] [i] indicates the testing power consumption of c layers of test core i, PlIt (c) is c
Layer rated disspation, b indicate the sum of c layers of core.
Five, the testing time is calculated: to shorten the 3D-NoC resource kernel testing time as target, to the test port of 3D-NoC
Selection optimization is carried out, so value of the testing time as test Estimate equation.Under the conditions of meeting power consumption limit, the testing time is got over
Short, testing scheme is better.Test data Network Transmission Delays in NoC are generally expressed in clock cycles；In NoC network transmission
Process, the testing time of core are longer than test data transmission time very much；The total testing time of core includes test data transmission time
And the testing time of core；In the test process of core, remaining data packet is passed to network in succession, so when test data is transmitted
Between mainly first data packet be input to tested core and the last one data packet is output to the biography of output port from tested core
The defeated time；The delay between data packet is not considered during the test.
Six, cloud computing algorithm: evolution algorithm cloud models theory is combined with natural evolution strategy, using cloud model C (Ex,
En, He) description evolutionary process.Wherein Ex is known as it is expected, represents elite seed individual；En is known as evolution entropy, represents transmutation of species
Probable ranges, the range of En more Big mutation rate is also bigger, otherwise smaller；He is known as super entropy of evolving, and indicates steady in evolutionary process
Qualitative, He is bigger, and stability is smaller, otherwise bigger.Value by adjusting En, He being capable of self adaptive control hereditary variation well
Degree and search range.The present invention uses One-Dimensional Normal cloud model, realizes that steps are as follows:
Input: parameter Ex, En, He, w of one-dimensional cloud model
Output: { (x1, m1) ..., (xw, mw)}
For i=0 to w
{ En'=RANDN (En, He)
xi=RANDN (Ex, En')
Drop (xi, ui) }
Cloud evolution algorithm is applied to the port 3D-NoC and optimizes the expression and control that must solve annual reporting law to optimization process.This
Text selects optimization to complete code Design mainly in combination with port, on the basis of cloud model qualitative evolution strategy, in order to preferably real
The optimizing of existing algorithm, the natural evolutions strategy such as introduced cross, selfing.Define first: population is random generation h kind test port group
The collection of conjunction is combined into population, and h indicates the scale of population；Individual: one of test port composite set port combination is known as
Individual, multiple individual composition populations；Chromosome: chromosome indicates a pair of specific test port, and a plurality of chromosome constitutes one
Individual；Gene: an input or output port, gene in a pair of specific test port of gene representation are the minimums evolved
Unit, two genes form item chromosome；Adaptive value: system completes the time of test needs as calculation under port combination
The adaptive value of method, adaptive value is smaller, and testing scheme is better.By the quality of adaptive value judgement individual, the evolution side of population is guided
To.
Six, the coding of cloud evolution algorithm: algorithm first has to solve encoded question, needs difference for different optimization problems
Encoding scheme, algorithm uses integer coding to node and port.For example, (1,2,3,4,5,6,7,8) is indicated by eight genes
The individual of composition is input port in odd number gene position, is output port in even number gene position, encodes in adjacent odd even gene position
It is a pair of of port.In evolutionary process, the water dust that cloud model generates is by round after decimal point.
Seven, filial generation generates: it is one-dimensional just to choose more new gene (a port is chosen in a port combination) conduct from individual
The desired value Ex of state cloud generator, entropy En value H/a1, super entropy He value H/a2, H is weight (test port Serial Number Range, a1、
a2It indicates control coefrficient, sets value a herein1≤H/2、a2≤H/2.The base that the gene that cloud generator generates is rounded and does not update
Because forming new individual.Selection adaptive value replaces seed better than seed-bearing individual in generating new offspring individual, as
Contemporary seed achievees the purpose that elite retains.
Eight, the Yun Jinhua adjustable strategies strategy can be realized by adjusting En, He.By tuning up control coefrficient a1、a2
(a1=2, a2=3) range searched for is reduced to turn En, He down, achievees the purpose that local refinement；When mostly generation is more preferably a without finding
When body, by turning control coefrficient a down1、a2(a1=1.1, a2=1.5) searching for new range tuning up En, He realizes that part is asked
Become.
Nine, make a variation adjustable strategies: when not obtaining by several generations, adaptive value is more preferably individual, and algorithm may fall into part
It is optimal, it needs to jump out part by mutation operation at this time.Cross and variation is implemented to group by natural evolution strategy and realizes mutation
Operation；The random chance p for generating 0~1 executes multiple spot selfing operation as 0≤p≤0.15；It is executed when 0.15 < p≤0.9 more
Dot blot operation, executes mutation operation as 0.9 < p≤1.Different Individual is selected from population using roulette mode, it is different
Multiple spot crossover operation is realized in chromosome exchange between individual；Different genes position, which swaps, in same individual realizes multiple spot selfing behaviour
Make.
Claims (5)
1. the method for network on three-dimensional chip test port selection optimization is evolved based on the cloud of high-precision optimizing under a kind of power consumption limit
Algorithm, test meet multiple constraint conditions, complete 3D-NoC based on NoC is reused as Test access mechanism and XYZ routing mode
Test port placement optimization obtains the optimal testing time.
2. the method for network on three-dimensional chip test port selection optimization under a kind of power consumption limit according to claim 1,
Cloud evolution algorithm cloud models theory is combined with natural evolution strategy, is evolved using cloud model C (Ex, En, He) description
Journey, wherein Ex is known as it is expected, represents elite seed individual;En is known as evolution entropy, represents the probable ranges of transmutation of species, and En is got over
The range of Big mutation rate is also bigger, otherwise smaller;He is known as super entropy of evolving, and indicates the stability in evolutionary process, and He is bigger steady
Qualitative smaller, otherwise bigger, the value by adjusting En, He being capable of the degree of self adaptive control hereditary variation and search model well
It encloses.
3. the method for network on three-dimensional chip test port selection optimization under a kind of power consumption limit according to claim 1,
Constraint condition are as follows: 1) each tested core need to only be tested once, and test midway cannot stop;2) what the core tested occupied
Internet resources are just discharged until testing, and before not discharging, other test cores must not be occupied;3) in same testing time section
Different test cores, it is necessary to avoid test resource conflict, have resource contention that must stop, being waited;4) in same test
In period, the total power consumption of all test cores must satisfy system power dissipation limitation;5) same in same testing time section
The total power consumption of layer test core must satisfy this layer of power consumption limit.
4. the method for network on three-dimensional chip test port selection optimization under a kind of power consumption limit according to claim 1,
Test access mechanism uses non-preemptive allocation strategy based on the test dispatching scheme test resource distribution of kernel priority to be measured,
In order to reduce hardware spending additional in test process, test reuses 3D-NoC as Test access mechanism, i.e. recycling 3D-
Routing node, routing channel and the TSV Internet resources of NoC complete test.
5. the method for network on three-dimensional chip test port selection optimization under a kind of power consumption limit according to claim 1,
XYZ routing mode be data packet from source node into destination node transmission process, data packet successively to X, Y, Z-direction transmit.
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| CN111314167A (en) * | 2020-01-15 | 2020-06-19 | 桂林电子科技大学 | Test planning system and method based on hypercube topological structure in network on chip |
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| CN111314167A (en) * | 2020-01-15 | 2020-06-19 | 桂林电子科技大学 | Test planning system and method based on hypercube topological structure in network on chip |
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