CN109543309B - Interference checking method based on layout key signals - Google Patents
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- CN109543309B CN109543309B CN201811410376.4A CN201811410376A CN109543309B CN 109543309 B CN109543309 B CN 109543309B CN 201811410376 A CN201811410376 A CN 201811410376A CN 109543309 B CN109543309 B CN 109543309B
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Abstract
The invention provides an interference checking method based on layout key signals. The interference elimination method is based on an RULE script of DRC verification language for automatically checking layout signal protection, can obtain a checking result of signal protection by executing DRC design RULE checking, and can quickly locate a place with signal interference in a layout. The whole interference signal checking process is performed by an automatic script, so that the operation is convenient, fast and efficient, the result is visual, the time and the energy required by manual checking are greatly saved, the method can be quickly applied to the interference signal checking of different process layouts by simply modifying a predefined form, and the universality is high.
Description
Technical Field
The invention relates to the field of automatic design of integrated circuit layouts, in particular to an interference checking method based on layout key signals.
Background
The design of integrated circuit layout is a key link for connecting circuit design and process manufacturing. Although the chip completes all simulation work in the circuit design stage and ensures that the functions and the performances of the circuit are within an acceptable range under a severe environment, the produced chip has a series of problems after long-time waiting, so that the functional deviation of the chip occurs, and the performance of the chip cannot achieve the expected effect. Most of these reasons are caused by signal interference. Signal interference not only causes deviations in chip function and performance, but also causes difficulties in chip debugging, resistance to chip testing, and the like. Although the preset signal interference point is found in the subsequent testing process, the verification and confirmation need to be carried out by using experimental methods such as FIB and the like, and then the production is carried out again, so that not only is the research and development cost of the chip increased, but also the time for the chip to enter the market is prolonged, and the chip possibly loses the good opportunity of the market.
In order to ensure the reliability of the chip operation, after the basic physical verification and the functional verification are completed on the layout, the sensitive signals, the high-resistance signals, the small signals and the high-frequency signals in the layout need to be protected and checked to prevent the occurrence of signal interference, thereby improving the reliability of the circuit performance. The common signal interference checking method includes three methods, one is to enlarge the distance between the signals in the same layer, the other is to add shielding wires in the same physical layer between the signals in the same layer, and the other is to adopt different metal layers to route the signals in the adjacent layers. The conventional interference checking method aiming at the signal interference problem comprises the following steps:
1) The method comprises the steps of obtaining a key signal table of a circuit to be processed, and searching each key signal in the key signal table on a circuit schematic diagram in a targeted mode, so that a module to be processed where the key signal is located is determined, and the complexity of a searching process is increased.
2) In a layout interface, searching a key signal line in the module to be processed, checking the specific trend of the key signal line, and then determining whether the key signal line and other signal lines on the same layer are parallel. If the parallel same-layer signal line and the key signal line belong to the same signal, or the parallel same-layer signal is a shielding signal line, the condition of signal interference does not exist; if the parallel signal lines in the same layer and the key signal do not belong to the same signal class, there is a danger of signal interference, and the distance that should be kept between the signal lines needs to be set by calculation to prevent signal interference. Because in the same layout, the same signal line is built up by different metal layers, which means that the number and the total number of types of the signal lines in the same layer parallel to the signal line are large, the checking mode is complex and tedious, and the phenomenon of checking omission is generated.
Therefore, the traditional interference checking method aiming at the signal interference problem has the defects of complex and tedious flow and unreliable result, which seriously influences the chip delivery time.
Disclosure of Invention
In order to make the troubleshooting of the signal line with the interference in the layout simpler, more comprehensive and more accurate, the invention provides the following technical scheme:
an interference checking method based on layout key signals comprises the following steps: predefining key signal lines, shielding signal lines, safety spacing values causing interference of the key signal lines and corresponding process-related metal level information in a layout circuit structure; capturing metal level connection information of the shielding signal line and metal level connection information of the key signal line, and merging and storing the metal level connection information of the same level of the same type of signal line; according to the merged and stored metal level connection information of the same level of the same type of signal lines and the metal level connection information of the shielding signal lines, outputting a report result that the distance between the preset signal line and the key signal line does not accord with the safe distance value as a checking result; the preset signal line and the key signal line are signal lines of the same-layer metal layer of non-similar signals and non-shielding signals, and the signal lines of the non-shielding signals are signal lines except the shielding signal line; the safety distance value is a distance value at which signal interference between the preset signal line and the key signal line is attenuated to an engineering negligible degree.
Further, before the capturing the metal level connection information of the shielding signal line and the metal level connection information of the key signal line, the method further includes: classifying the signal lines of the layout to be checked, wherein the classification conditions comprise signal types, signal characteristics and metal layers to which the signal lines belong; the signal lines are divided into the same-class signal lines and the non-same-class signal lines according to signal types, the shielded signal lines and the non-shielded signal lines according to signal characteristics, and the signal lines of the metal layers on the same layer and the signal lines of the metal layers on the non-same layer are divided according to the metal layers to which the signal lines belong.
Further, the scripts of the foregoing step methods all use DRC verification language, and output the troubleshooting results of the key signal by performing DRC checks.
Compared with the prior art, the interference troubleshooting method based on the layout key signals can rapidly classify all metal layer signal lines on the integrated circuit layout to be debugged according to the specified classification rule, can rapidly position the position with signal interference by utilizing automatic script troubleshooting and comprehensively replacing manual troubleshooting, and has the advantages of accurate and reliable troubleshooting result, simple, rapid and visual operation.
In addition, the method can be quickly applied to the layouts of different IC processes for signal protection and troubleshooting only by modifying the relevant physical layer definition and the relevant signal definition of the IC processes in the classification rule, and the technical scheme has strong universality.
Drawings
Fig. 1 is a flowchart of an interference elimination method based on layout key signals according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a metal connection region in a layout to be detected before the interference elimination method is executed according to the embodiment of the present invention;
fig. 3 is a schematic diagram of a metal connection line region after the interference elimination method is executed in a layout to be detected according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention.
The invention provides an interference elimination method based on layout key signals, which is controlled and executed by a design rule script based on a DRC verification language, wherein a check result of signal protection can be obtained by executing DRC design rule check, and a place with signal interference in a layout can be quickly positioned, so that the operation is convenient, quick and efficient, the result is intuitive, the time and the energy required by manual elimination are greatly saved, the interference elimination method can be quickly applied to the elimination of interference signals of different process layouts by simply modifying a predefined form, and the universality is strong. The specific implementation of the interference checking method can refer to the flowchart 1.
The predefined information is as follows: the key signal line is used for defining the signal type of the key signal line according to a specified circuit key signal table; meanwhile, shielding the signal line in advance; predefining a safe spacing value causing the critical signal line interference; and predefining process-related metal level information.
Information capturing: and capturing metal level connection information of the shielding signal line, capturing metal level connection information of the key signal line, and merging and storing the metal layer information of the same level of the same type of signal. Meanwhile, the metal level connection information of the non-shielding signal line can be obtained. It should be noted that, in the layout design, the similar signals of the key signal line do not interfere with the key signal line, so that the metal layer information of the same level of the similar signals is merged and stored. In addition, the signal lines of the metal layers at different levels do not generate interference problems.
Before the information is captured, the signal lines need to be classified, wherein the classification process of the classification condition specifically includes: dividing the signals into homogeneous signals and non-homogeneous signals according to the types of the signals; dividing the signal into a shielded signal line and a non-shielded signal line according to signal characteristics; and the metal layer to which the signal line belongs is divided into the signal line of the metal layer on the same layer and the signal line of the metal layer on the different layer. It should be noted that the above-mentioned process describes a process of individually classifying according to each classification condition, and when the classification condition is a check, for example, there are two or more classification conditions, there is no specific precedence order between the two or more classification conditions.
And (3) outputting violation information: according to the merged and stored information of the same-layer metal layers of the same-type signal lines and the metal layer connection information of the shielding signal lines, a result report that the distance between the preset signal line and the key signal line does not accord with the safe distance value is output as a checking result, namely the result report is output as the violation information of DRC (design rule base), namely the distance value of one boundary of the key signal line and the boundary of the preset signal line with the nearest distance between the key signal line and the boundary does not meet the safe distance value, and the key signal is indicated to have the risk of being interfered. The preset signal line and the key signal line are signal traces of non-shielding signals of the same metal layer, and the signal traces of the non-shielding signals are signal traces except the shielding signal line.
The scripts of the foregoing methods all use DRC verification language, implement the checking process of the key signals by performing DRC checks, and then, according to the DRC check results, move the signal traces of the same-layer metal layers where interference occurs so that the distances between them are adjusted to the safe distance values when necessary and feasible. Wherein the safe distance value is: and if the key signal wire is arranged in the adjacent routing area of the metal layer on the same layer, the signal interference between the key signal wire and the signal routing of the metal layer on the same layer of the non-shielding signal belonging to the non-homogeneous signal is attenuated to a distance value which can be ignored in engineering.
Generally speaking, executing the DRC design rule check and adjusting the layout according to the DRC check result is a process that needs to be repeatedly executed, and the structural features of the layout are continuously adjusted by obtaining the result obtained by repeatedly executing the DRC check until the preset signal line check is completed and there is no signal line interfering with the key signal.
As an embodiment of the present invention, fig. 2 is a metal connection line region of a layout to be detected before executing the interference elimination method, where: reference numeral 101 in fig. 2 and 3 denotes the key signal line, which is formed by a first predetermined metal layer; reference numeral 103 and reference numeral 101 in fig. 2 and fig. 3 belong to the non-homogeneous signal line, and reference numeral 103 is the non-shielding signal line, and is formed by a second preset metal layer; reference numeral 102 in fig. 2 and 3 represents the non-shielded signal line, and reference numeral 102 and reference numeral 101 belong to the non-homogeneous signal line, and are formed by the first predetermined metal layer.
In this embodiment, the signal line 101 and the signal line 102 belong to signal traces of metal layers on the same layer, that is, the first predetermined metal layer and the third predetermined metal layer belong to metal layers on the same layer, and a distance between the signal line 101 and the signal line 102 in fig. 2 is smaller than the safety distance value, so that there is a danger of signal interference between the signal line 101 and the signal line 102. In this embodiment, the safe pitch value may be set to be greater than or equal to three times of the signal trace line width of the metal layer on the same layer. Meanwhile, the signal lines 101 and 103 belong to signal traces of different metal layers on different layers, so that there is no danger of signal interference between the signal lines 101 and 103. By using the interference checking method, the position where the signal interference exists on the layout can be quickly located, as shown in fig. 3, a thick line box 104 between the metal layer boundary of the signal line 101 and the metal layer boundary of the signal line 102 is highlighted, so as to prompt a layout designer that the width of the thick line box 104 does not meet the safety distance value, which indicates that a factor causing the signal interference of the key signal line 101 exists in the region of the thick line box 104, that is, the signal line 102 interferes with the signal line 101 (the key signal line). Then, according to the violation information obtained by DRC check, under the necessary condition that the violation information conforms to the design rule, the signal lines 102 of the same metal layer interfering with the signal lines 101 are moved so that the distance between the signal lines meets the safety distance value, that is, the signal routing line width of the same metal layer is greater than three times, and meets the safety distance value, so as to ensure that the critical signals are not affected by signal interference in the working process of the chip.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (3)
1. An interference checking method based on layout key signals is characterized by comprising the following steps:
predefining key signal lines, shielding signal lines, safe interval values causing the interference of the key signal lines and metal level information related to corresponding processes in a layout circuit structure;
capturing metal level connection information of the shielding signal line and metal level connection information of the key signal line, and merging and storing the metal level connection information of the same level of the same type of signal line;
according to the merged and stored metal level connection information of the same level of the same type of signal lines and the metal level connection information of the shielding signal lines, outputting a report result as a troubleshooting result, wherein the report result indicates that the distance between a preset signal line and the key signal line does not accord with the safe distance value;
the preset signal line and the key signal line are signal lines of the same-layer metal layer of non-similar signals and non-shielding signals, and the signal lines of the non-shielding signals are signal lines except the shielding signal line; the safety distance value is a distance value at which signal interference between the preset signal line and the key signal line is attenuated to an engineering negligible degree.
2. The interference elimination method according to claim 1, further comprising, before the capturing the metal-level connection information of the shielding signal line and the metal-level connection information of the key signal line: classifying the signal lines of the layout to be checked, wherein the classification conditions comprise signal types, signal characteristics and metal layers to which the signal lines belong; the signal lines are divided into the same-class signal lines and the non-same-class signal lines according to signal types, the signal lines are divided into the shielding signal lines and the non-shielding signal lines according to signal characteristics, and the signal lines of the metal layers on the same layer and the signal lines of the metal layers on the non-same layer are divided according to the metal layers to which the signal lines belong.
3. The interference elimination method according to any one of claims 1 to 2, wherein the scripts of the foregoing step methods are all the DRC verification language, and the elimination process of the key signals is realized by executing DRC check.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2001088956A2 (en) * | 2000-05-15 | 2001-11-22 | Atheros Communications, Inc. | Rf integrated circuit layout |
| CN101782931A (en) * | 2009-01-20 | 2010-07-21 | 英业达股份有限公司 | Processing method and system of constraint areas of circuit board wiring |
| CN102855337A (en) * | 2011-06-27 | 2013-01-02 | 鸿富锦精密工业（深圳）有限公司 | Automated wiring inspection system and automated wiring inspection method |
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| US7739624B2 (en) * | 2002-07-29 | 2010-06-15 | Synopsys, Inc. | Methods and apparatuses to generate a shielding mesh for integrated circuit devices |
| US7943436B2 (en) * | 2002-07-29 | 2011-05-17 | Synopsys, Inc. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001088956A2 (en) * | 2000-05-15 | 2001-11-22 | Atheros Communications, Inc. | Rf integrated circuit layout |
| CN101782931A (en) * | 2009-01-20 | 2010-07-21 | 英业达股份有限公司 | Processing method and system of constraint areas of circuit board wiring |
| CN102855337A (en) * | 2011-06-27 | 2013-01-02 | 鸿富锦精密工业（深圳）有限公司 | Automated wiring inspection system and automated wiring inspection method |
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