CN109491659A

CN109491659A - Instruct conversion method and device

Info

Publication number: CN109491659A
Application number: CN201710813786.2A
Authority: CN
Inventors: 张利霞; 余银
Original assignee: Loongson Technology Corp Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2017-09-11
Filing date: 2017-09-11
Publication date: 2019-03-19
Anticipated expiration: 2037-09-11
Also published as: CN109491659B

Abstract

The embodiment of the invention provides a kind of instruction conversion methods, comprising: obtains the arithmetic instruction of underlying virtual machine LLVM compiler intermediate code；Determine the operand and operation code of the arithmetic instruction of the LLVM compiler intermediate code；Determine the system digit of target platform；In the instruction set of the target platform, object run code corresponding with the arithmetic instruction operation code of the LLVM compiler intermediate code and the system digit is determined；Using the operand and object run code, the arithmetic instruction of target platform is generated.In embodiments of the present invention, LLVM compiler can generate the matched arithmetic instruction of system digit with goal systems according to the system digit of target platform when the arithmetic instruction of intermediate code to be converted to the arithmetic instruction of target platform.

Description

Instruct conversion method and device

Technical field

The present invention relates to field of computer technology, more particularly to a kind of instruction conversion method and a kind of instruction converting means It sets.

Background technique

LLVM (Low Level Virtual Machine, underlying virtual machine) compiler is that one kind can be by high-level language Code is converted to the compiler of target platform code.Higher-level language code is converted to the centre of LLVM by LLVM compiler first Then intermediate command is converted to target platform code again by sound instruction IR.

The intermediate language instructions IR of LLVM compiler, needs to be converted to by SelectionDAG Node Selector and has The instruction of SelectionDAG node.ISD order space includes one and records all SelectionDAG node types and value class The enumerated list of type, SelectionDAG node therein include: the more instruction of precision addition and subtraction ADDC, SUBC, ADDE, SUBE.

It only realizes in the prior art and more precision addition and subtractions is instructed into ADDC, SUBC, ADDE, SUBE, be converted to 32 The conversion operation of 64 MIPS platforms is not implemented in the conversion operation of instruction on MIPS platform.

Summary of the invention

In view of the above problems, it proposes the embodiment of the present invention and overcomes the above problem or at least partly in order to provide one kind A kind of instruction conversion method to solve the above problems and a kind of corresponding instruction conversion equipment.

To solve the above-mentioned problems, the embodiment of the invention discloses a kind of instruction conversion methods, comprising:

Obtain the arithmetic instruction of underlying virtual machine LLVM compiler intermediate code；

Determine the operand and operation code of the arithmetic instruction of the LLVM compiler intermediate code；

Determine the system digit of target platform；

In the instruction set of the target platform, the determining arithmetic instruction operation code with the LLVM compiler intermediate code And the corresponding object run code of the system digit；

Using the operand and object run code, the arithmetic instruction of target platform is generated.

Preferably, the target platform is MIPS platform, and the arithmetic instruction includes: ADDC addition instruction and SUBC subtraction Instruction；The operation code of the ADDC addition instruction is ADDC operation code；The operation code of the SUBC subtraction instruction is SUBC operation Code；

The target instruction target word in the target platform is concentrated, the determining finger that counts with the LLVM compiler intermediate code The step of operation code of order corresponding object run code includes:

If the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and ADDC addition instruction Operand do not include immediate, it is determined that add operation code DADDu corresponding with the ADDC operation code；

If the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and SUBC subtraction instruction Operand do not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBC operation code；

If the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and ADDC addition instruction Operand include immediate, it is determined that add operation code DADDiu corresponding with the ADDC operation code；

If the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and SUBC subtraction instruction Operand include immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBC operation code.

Preferably, the operand of the ADDC addition instruction and the SUBC subtraction instruction includes: first operand and Two operands；Described to use the operand and object run code, the step of generating the arithmetic instruction of target platform, includes:

Using the first operand, the second operand and the add operation code DADDu, ADDC addition is generated Instruction is in the corresponding addition instruction of 64 target platforms；Or,

Using the first operand, the second operand and the subtraction operation code DSUBu, SUBC subtraction is generated Instruction is in the corresponding subtraction instruction of 64 target platforms；Or,

Using the first operand, the second operand and the add operation code DADDiu, generates ADDC and add Method is instructed in the corresponding addition instruction of 64 target platforms；Or,

Using the first operand, the second operand and the subtraction operation code DSUBiu, generates SUBC and subtract Method is instructed in the corresponding subtraction instruction of 64 target platforms.

Preferably, the target platform is MIPS platform, and the arithmetic instruction includes: ADDE addition instruction and SUBE subtraction Instruction；The operation code of the ADDE addition instruction is ADDE operation code；The operation code of the SUBE subtraction instruction is SUBE operation Code；

It is described in the instruction set of the target platform, the determining arithmetic instruction with the LLVM compiler intermediate code is grasped The step of making code and the system digit corresponding object run code include:

If the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and ADDE addition instruction Operand do not include immediate, it is determined that add operation code DADDu corresponding with the ADDE operation code；

If the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and SUBE subtraction instruction Operand do not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBE operation code；

If the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and ADDE addition instruction Operand include immediate, it is determined that add operation code DADDiu corresponding with the ADDE operation code；

If the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and SUBE subtraction instruction Operand include immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBE operation code.

Preferably, the operand of the ADDE addition instruction and the SUBE subtraction instruction includes: first operand, second Operand, input carry value；

Described to use the operand and object run code, the step of generating the arithmetic instruction of target platform, includes:

Using the first operand, second operand and the add operation code DADDu, generates DADDu addition and refer to It enables；Or,

Using the first operand, second operand and the subtraction operation code DSUBu, generates DSUBu subtraction and refer to It enables；Or,

Using the first operand, second operand and the add operation code DADDiu, DADDiu addition is generated Instruction；Or,

Using the first operand, second operand and the subtraction operation code DSUBiu, DSUBiu subtraction is generated Instruction；

Using the input carry value, first operand and the second operand, generates the calculating of output carry value and refer to It enables；

In conjunction with the DADDu addition instruction and the output carry value computations, as ADDE addition instruction at 64 The corresponding addition instruction of target platform；Or,

In conjunction with the DSUBu subtraction instruction and the output carry value computations, as SUBE subtraction instruction at 64 The corresponding subtraction instruction of target platform；Or,

In conjunction with the DADDiu addition instruction and the output carry value computations, as ADDE addition instruction at 64 The corresponding addition instruction of target platform；Or,

In conjunction with the DSUBiu subtraction instruction and the output carry value computations, as SUBE subtraction instruction at 64 The corresponding subtraction instruction of target platform.

Preferably, described using the input carry value, first operand and the second operand, generation export into The step of place value computations includes:

For the DADDu addition instruction, the first output carry value computations are generated；The first output carry value meter Calculate instruction for executes use the DADDu addition instruction operation result, respectively with the first operand and described second Operand is compared, and determines addition carry value；The input carry value is added with the addition carry value, obtain exporting into The operation of place value；

For the DSUBu subtraction instruction, the second output carry value computations are generated；The second output carry value meter Instruction is calculated for executing the first operand and the second operand, determines that subtraction borrows value；By it is described input into Place value subtracts the subtraction and borrows value, obtains the operation of output carry value；

For DADDiu addition instruction, third output carry value computations are generated；The third output carry value calculates Instruction is grasped with the first operand and described second respectively for executing the operation result using the DADDiu addition instruction It counts and is compared, determine addition carry value；The input carry value is added with the addition carry value, obtains output carry The operation of value；

For DSUBiu subtraction instruction, the 4th output carry value computations are generated；The 4th output carry value calculates Instruction determines that subtraction borrows value for executing the first operand and the second operand；By the input carry Value subtracts the subtraction and borrows value, obtains the operation of output carry value.

Preferably, described using the input carry value, first operand and the second operand, generation export into The step of place value computations further include:

Generate specific output carry value computations；If the specific output carry value computations add for executing ADDE The second operand of method instruction or SUBE subtraction instruction is 0, then using input carry value as the operation of output carry value.

The embodiment of the invention also discloses a kind of instruction conversion equipments, comprising:

Arithmetic instruction obtains module, for obtaining the arithmetic instruction of LLVM compiler intermediate code；

Operating parameter determining module, for determining operand and the behaviour of the arithmetic instruction of the LLVM compiler intermediate code Make code；

System digit determining module, for determining the system digit of target platform；

Object run code determining module, for determining and the LLVM compiler in the instruction set of the target platform The arithmetic instruction operation code of intermediate code and the corresponding object run code of the system digit；

Arithmetic instruction generation module generates counting for target platform for using the operand and object run code Instruction.

The object run code determining module includes:

First operation code determines submodule, if being ADDC addition instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of ADDC addition instruction does not include immediate, it is determined that corresponding with the ADDC operation code to add Method operation code DADDu；

Second operation code determines submodule, if being SUBC subtraction instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of SUBC subtraction instruction does not include immediate, it is determined that corresponding with the SUBC operation code to subtract Method operation code DSUBu；

Third operation code determines submodule, if being ADDC addition instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of ADDC addition instruction includes immediate, it is determined that addition corresponding with the ADDC operation code Operation code DADDiu；

4th operation code determines submodule, if being SUBC subtraction instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of SUBC subtraction instruction includes immediate, it is determined that subtraction corresponding with the SUBC operation code Operation code DSUBiu.

Preferably, the operand of the ADDC addition instruction and the SUBC subtraction instruction includes: first operand and Two operands；The arithmetic instruction generation module includes:

First arithmetic instruction generates submodule, for using the first operand, the second operand and described Add operation code DADDu generates ADDC addition instruction in the corresponding addition instruction of 64 target platforms；Or,

Second arithmetic instruction generates submodule, for using the first operand, the second operand and described Subtraction operation code DSUBu generates SUBC subtraction instruction in the corresponding subtraction instruction of 64 target platforms；Or,

Third arithmetic instruction generates submodule, for using the first operand, the second operand and described Add operation code DADDiu generates ADDC addition instruction in the corresponding addition instruction of 64 target platforms；Or,

4th arithmetic instruction generates submodule, for using the first operand, the second operand and described Subtraction operation code DSUBiu generates SUBC subtraction instruction in the corresponding subtraction instruction of 64 target platforms.

The object run code determination includes:

5th operation code determines submodule, if being ADDE addition instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of ADDE addition instruction does not include immediate, it is determined that corresponding with the ADDE operation code to add Method operation code DADDu；

6th operation code determines submodule, if being SUBE subtraction instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of SUBE subtraction instruction does not include immediate, it is determined that corresponding with the SUBE operation code to subtract Method operation code DSUBu；

7th operation code determines submodule, if being ADDE addition instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of ADDE addition instruction includes immediate, it is determined that addition corresponding with the ADDE operation code Operation code DADDiu；

8th operation code determines submodule, if being SUBE subtraction instruction, the system of target platform for the arithmetic instruction Digit is 64, and the operand of SUBE subtraction instruction includes immediate, it is determined that subtraction corresponding with the SUBE operation code Operation code DSUBiu.

The arithmetic instruction generation module includes:

5th arithmetic instruction generates submodule, for using the first operand, second operand and the addition Operation code DADDu generates DADDu addition instruction；Or,

6th arithmetic instruction generates submodule, for using the first operand, second operand and the subtraction Operation code DSUBu generates DSUBu subtraction instruction；Or,

7th arithmetic instruction generates submodule, for using the first operand, second operand and the addition Operation code DADDiu generates DADDiu addition instruction；Or,

8th arithmetic instruction generates submodule, for using the first operand, second operand and the subtraction Operation code DSUBiu generates DSUBiu subtraction instruction；

Output carry value computations generate submodule, for using the input carry value, first operand and institute Second operand is stated, output carry value computations are generated；

9th arithmetic instruction generates submodule, for calculating in conjunction with the DADDu addition instruction and the output carry value Instruction, as ADDE addition instruction in the corresponding addition instruction of 64 target platforms；Or,

Tenth arithmetic instruction generates submodule, for calculating in conjunction with the DSUBu subtraction instruction and the output carry value Instruction, as SUBE subtraction instruction in the corresponding subtraction instruction of 64 target platforms；Or,

11st arithmetic instruction generates submodule, based in conjunction with the DADDiu addition instruction and the output carry value Instruction is calculated, as ADDE addition instruction in the corresponding addition instruction of 64 target platforms；Or,

12nd arithmetic instruction generates submodule, based in conjunction with the DSUBiu subtraction instruction and the output carry value Instruction is calculated, as SUBE subtraction instruction in the corresponding subtraction instruction of 64 target platforms.

Preferably, the output carry value computations generation submodule includes:

First output carry value computing unit, for generating the first output carry value meter for the DADDu addition instruction Calculate instruction；The first output carry value computations are used to execute the operation result using the DADDu addition instruction, respectively It is compared with the first operand and the second operand, determines addition carry value；By the input carry value and institute The addition of addition carry value is stated, the operation of output carry value is obtained；

Second output carry value computing unit, for generating the second output carry value meter for the DSUBu subtraction instruction Calculate instruction；The second output carry value computations are used to execute the first operand and the second operand, Determine that subtraction borrows value；The input carry value is subtracted into the subtraction and borrows value, obtains the operation of output carry value；

Third output carry value computing unit, for generating third output carry value and calculating for DADDiu addition instruction Instruction；The third output carry value computations are used to execute the operation result using the DADDiu addition instruction, respectively It is compared with the first operand and the second operand, determines addition carry value；By the input carry value and institute The addition of addition carry value is stated, the operation of output carry value is obtained；

4th output carry value computing unit, for generating the 4th output carry value and calculating for DSUBiu subtraction instruction Instruction；The 4th output carry value computations are for executing the first operand and the second operand, really Determine subtraction and borrows value；The input carry value is subtracted into the subtraction and borrows value, obtains the operation of output carry value.

Preferably, the output carry value computations generate submodule further include:

Specific output carry value computing unit, for generating specific output carry value computations；The specific output into If it is 0 that place value computations, which are used to execute ADDE addition instruction or the second operand of SUBE subtraction instruction, by input carry It is worth the operation as output carry value.

The embodiment of the invention also discloses a kind of electronic equipment, including memory, processor and storage are on a memory simultaneously The computer program that can be run on a processor, which is characterized in that the processor performs the steps of when executing described program

Obtain the arithmetic instruction of LLVM compiler intermediate code；

Determine the system digit of target platform；

The embodiment of the invention also discloses a kind of computer readable storage mediums, are stored thereon with computer program, special The step of sign is, the above method is realized when which is executed by processor.

The embodiment of the present invention includes following advantages:

In embodiments of the present invention, the arithmetic instruction of intermediate code is being converted to counting for target platform by LLVM compiler When instruction, the matched arithmetic instruction of system digit with goal systems can be generated according to the system digit of target platform.

In the embodiment of the present invention, LLVM compiler is in the finger that counts that the arithmetic instruction of intermediate code is converted to MIPS platform When enabling, for 32 MIPS platforms, LLVM compiler can be by the arithmetic instruction (ADDC/SUBC/ADDE/ of intermediate code SUBE instruction) switch to arithmetic instruction on 32 MIPS platforms.For 64 MIPS platforms, LLVM compiler can will be intermediate The arithmetic instruction (ADDC/SUBC/ADDE/SUBE instruction) of code switchs to the arithmetic instruction on 64 MIPS platforms.

Detailed description of the invention

Fig. 1 is a kind of step flow chart of instruction conversion method embodiment 1 of the invention；

Fig. 2 is a kind of step flow chart of instruction conversion method embodiment 2 of the invention；

Fig. 3 is a kind of step flow chart of instruction conversion method embodiment 3 of the invention；

Fig. 4 is a kind of structural block diagram of instruction conversion equipment embodiment of the invention.

Specific embodiment

In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real Applying mode, the present invention is described in further detail.

Referring to Fig.1, a kind of step flow chart of instruction conversion method embodiment 1 of the invention is shown, specifically can wrap Include following steps:

Step 101, the arithmetic instruction of LLVM compiler intermediate code is obtained；

During the instruction of high-level language is converted to the instruction of target platform by LLVM compiler, LLVM compiler is first The instruction of high-level language is first converted into intermediate language instructions IR, intermediate language instructions IR is then converted into band The instruction of SelectionDAG node.

In embodiments of the present invention, the arithmetic instruction of intermediate code is exactly the arithmetic instruction with SelectionDAG node. The SelectionDAG node of arithmetic instruction may include: more precision addition node ADDC and ADDE, more precision subtraction nodes SUBC and SUBE.

ADDC/SUBC is the carry setting node of more precision additions and subtraction, and ADDC/SUBC node has the two of same type A operand, and two are generated as a result, first is normally added deduct as a result, second is carry flag result.

ADDE/SUBE is the carry application node of more precision additions and subtraction, and there are three operand, the first two to be for the node Two number of left and right normally to add deduct, third operand are the inputs of carry flag, which generates two as a result, first Be normally add deduct as a result, second be carry flag output.A carry flag is all read and write to these nodes to permit Perhaps the adduction of arbitrarily large number is subtracted and is cascaded by they.

Step 102, the operand and operation code of the arithmetic instruction of the LLVM compiler intermediate code are determined；

Arithmetic instruction with SelectionDAG node includes operand and operation code, and wherein operation code is exactly SelectionDAG node.

Operand is equivalent to the input of instruction, and operation code then describes the processing mode to input.

Step 103, the system digit of target platform is determined；

In embodiments of the present invention, target platform may include MIPS platform.The system digit of MIPS platform may include 32 and 62.

Specifically, can be come by ABI (Application Binary Interface, application binaries interface) Judge the system digit of MIPS platform.

It is to be distinguished by the way that ABI is o32 or n64 on mips platform, system digit is 32 or 64.

Step 104, in the instruction set of the target platform, the determining finger that counts with the LLVM compiler intermediate code Enable operation code and the corresponding object run code of the system digit；

It is exactly by the essence that the instruction of intermediate code is converted to target platform instruction, using in the instruction set of target platform Operation code generates the instruction with the same function that counts with intermediate code.

Object run code can be it is preset, may be implemented intermediate code algorithm instruction function operation code.

For the target platform of not homologous ray digit, the operation code for realizing the function of the algorithm instruction of intermediate code can To be different.Therefore, it is necessary to the selected matched operation codes of system digit with target platform.

Step 105, using the operand and object run code, the arithmetic instruction of target platform is generated.

It is raw using the object run code in the operand of the arithmetic instruction of intermediate code and the instruction set of target platform At the instruction of target platform.

For example, using the object run in the operand of the arithmetic instruction of intermediate code and the instruction set of MIPS platform Code generates the instruction of MIPS platform.

Referring to Fig. 2, a kind of step flow chart of instruction conversion method embodiment 2 of the invention is shown, the target is flat Platform be MIPS (Microprocessor without interlocked piped stages, no inner interlocked pipelining-stage it is micro- Processor) platform, the method can specifically include following steps:

Step 201, the arithmetic instruction of LLVM compiler intermediate code is obtained；The arithmetic instruction of the intermediate code includes: ADDC addition instruction and SUBC subtraction instruction；

Step 202, the operand and operation code of the arithmetic instruction of the LLVM compiler intermediate code are determined；

In inventive embodiments, the operation code of the ADDC addition instruction is ADDC operation code；The SUBC subtraction instruction Operation code be SUBC operation code；

Step 203, the system digit of the MIPS platform is determined；

MIPS platform may include 32 systems and 64 systems.

Step 204, in the instruction set of the MIPS platform, the determining finger that counts with the LLVM compiler intermediate code Enable operation code and the corresponding object run code of the system digit；

In embodiments of the present invention, the step 204 may include following sub-step:

Sub-step S11, if the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and The operand of ADDC addition instruction does not include immediate, it is determined that add operation code DADDu corresponding with the ADDC operation code；

Sub-step S12, if the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and The operand of SUBC subtraction instruction does not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBC operation code；

Sub-step S13, if the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and The operand of ADDC addition instruction includes immediate, it is determined that add operation code DADDiu corresponding with the ADDC operation code；

Sub-step S14, if the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and The operand of SUBC subtraction instruction includes immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBC operation code；

Sub-step S15, if the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 32, and The operand of ADDC addition instruction does not include immediate, it is determined that add operation code ADDu corresponding with the ADDC operation code；

Sub-step S16, if the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 32, and The operand of SUBC subtraction instruction does not include immediate, it is determined that subtraction operation code SUBu corresponding with the SUBC operation code；

Sub-step S17, if the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 32, and The operand of ADDC addition instruction includes immediate, it is determined that add operation code ADDiu corresponding with the ADDC operation code；

Sub-step S18, if the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 32, and The operand of SUBC subtraction instruction includes immediate, it is determined that subtraction operation code SUBiu corresponding with the SUBC operation code.

Step 205, using the operand and object run code, the arithmetic instruction of the MIPS platform is generated.

In embodiments of the present invention, the operand of the ADDC addition instruction and the SUBC subtraction instruction includes: first Operand and second operand；

First operand is specially left operand LHS (Left-Hand Side), and second operand is specially right operand RHS(right-Hand Side)。

The step 205 may include following sub-step:

Sub-step S21 is raw using the first operand, the second operand and the add operation code DADDu At ADDC addition instruction in the corresponding addition instruction of 64 target platforms；Or,

If the system digit of MIPS platform is 64, and the operand of ADDC addition instruction does not include immediate, then uses It is corresponding in 64 MIPS platforms to generate ADDC addition instruction by first operand, second operand and add operation code DADDu Addition instruction.

Sub-step S22 is raw using the first operand, the second operand and the subtraction operation code DSUBu At SUBC subtraction instruction in the corresponding subtraction instruction of 64 target platforms；Or,

If the system digit of MIPS platform is 64, and the operand of SUBC subtraction instruction does not include immediate, then uses It is corresponding in 64 MIPS platforms to generate SUBC subtraction instruction by first operand, second operand and subtraction operation code DSUBu Subtraction instruction.

Sub-step S23, using the first operand, the second operand and the add operation code DADDiu, ADDC addition instruction is generated in the corresponding addition instruction of 64 target platforms；Or,

If the system digit of MIPS platform is 64, and the operand of ADDC addition instruction includes immediate, then using the It is corresponding in 64 MIPS platforms to generate ADDC addition instruction by one operand, second operand and add operation code DADDiu Addition instruction.

Sub-step S24, using the first operand, the second operand and the subtraction operation code DSUBiu, SUBC subtraction instruction is generated in the corresponding subtraction instruction of 64 target platforms；Or,

If the system digit of MIPS platform is 64, and the operand of SUBC subtraction instruction includes immediate, then using the It is corresponding in 64 MIPS platforms to generate SUBC subtraction instruction by one operand, second operand and subtraction operation code DSUBiu Subtraction instruction.

Sub-step S25 is raw using the first operand, the second operand and the add operation code ADDu At ADDC addition instruction in the corresponding addition instruction of 32 target platforms；Or,

If the system digit of MIPS platform is 32, and the operand of ADDC addition instruction does not include immediate, then uses It is corresponding in 32 MIPS platforms to generate ADDC addition instruction by first operand, second operand and add operation code ADDu Addition instruction.

Sub-step S26 is raw using the first operand, the second operand and the subtraction operation code SUBu At SUBC subtraction instruction in the corresponding subtraction instruction of 32 target platforms；Or,

If the system digit of MIPS platform is 32, and the operand of SUBC subtraction instruction does not include immediate, then uses It is corresponding in 32 MIPS platforms to generate SUBC subtraction instruction by first operand, second operand and subtraction operation code SUBu Subtraction instruction.

Sub-step S27 is raw using the first operand, the second operand and the add operation code ADDiu At ADDC addition instruction in the corresponding addition instruction of 32 target platforms；Or,

If the system digit of MIPS platform is 32, and the operand of ADDC addition instruction includes immediate, then using the One operand, second operand and add operation code ADDiu, generate ADDC addition instruction 32 MIPS platforms it is corresponding plus Method instruction.

Sub-step S28 is raw using the first operand, the second operand and the subtraction operation code SUBiu At SUBC subtraction instruction in the corresponding subtraction instruction of 32 target platforms.

If the system digit of MIPS platform is 32, and the operand of SUBC subtraction instruction includes immediate, then using the One operand, second operand and subtraction operation code SUBiu generate SUBC subtraction instruction and subtract 32 MIPS platforms are corresponding Method instruction.

In the embodiment of the present invention, LLVM compiler is in the finger that counts that the arithmetic instruction of intermediate code is converted to MIPS platform When enabling, for 32 MIPS platforms, LLVM compiler can switch to the arithmetic instruction (ADDC/SUBC instruction) of intermediate code Arithmetic instruction on 32 MIPS platforms.For 64 MIPS platforms, LLVM compiler can be by the finger that counts of intermediate code (ADDC/SUBC instruction) is enabled to switch to the arithmetic instruction on 64 MIPS platforms.

In order to make those skilled in the art can better understand that the embodiment of the present invention, real to the present invention below by example Example is applied to be illustrated:

As follows is the DSUBu subtraction instruction that SUBC instruction is converted to 64 MIPS platforms in the embodiment of the present invention Code:

Wherein, GPR64 indicates that operand type is 64, and $ LHS indicates that left operand, $ RHS indicate right operand.

SUBC instruction includes: operation code SUBC, 64 left operand LHS and 64 right operand RHS.

DSUBu subtraction instruction includes: operation code DSUBu, 64 left operand LHS and 64 right operand RHS.

DSUBu addition instruction generation as follows for ADDC instruction to be converted to 64 MIPS platforms in the embodiment of the present invention Code:

Wherein, ADDC instruction includes: operation code ADDC, 64 left operand LHS and 64 right operand RHS.

DADDu instruction includes: operation code ADDDu, 64 left operand LHS and 64 right operand RHS.

DADDiu addition instruction as follows for ADDC instruction to be converted to 64 MIPS platforms in the embodiment of the present invention Code:

Wherein, $ imm indicates immediate.

ADDC instruction includes: operation code ADDC, 64 left operand LHS and 64 immediate imm.

DADDiu instruction includes: operation code DADDiu, 64 left operand LHS and 64 immediate imm.

Referring to Fig. 3, a kind of step flow chart of instruction conversion method embodiment 3 of the invention is shown, the target is flat Platform be MIPS (Microprocessor without interlocked piped stages, no inner interlocked pipelining-stage it is micro- Processor) platform, the method can specifically include following steps:

Step 301, the arithmetic instruction of LLVM compiler intermediate code is obtained；The arithmetic instruction of the intermediate code includes: ADDE addition instruction and SUBE subtraction instruction；

Step 302, the operand and operation code of the arithmetic instruction of the LLVM compiler intermediate code are determined；

In embodiments of the present invention, the operation code of the ADDE addition instruction is ADDE operation code；The SUBE subtraction refers to The operation code of order is SUBE operation code；

Step 303, the system digit of MIPS platform is determined；

MIPS platform may include 32 systems and 64 systems.

Step 304, in the instruction set of the MIPS, the determining arithmetic instruction with the LLVM compiler intermediate code is grasped Make code and the corresponding object run code of the system digit；

In embodiments of the present invention, the step 304 may include following sub-step:

Sub-step S31, if the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and The operand of ADDE addition instruction does not include immediate, it is determined that add operation code DADDu corresponding with the ADDE operation code；

Sub-step S32, if the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and The operand of SUBE subtraction instruction does not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBE operation code；

Sub-step S33, if the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and The operand of ADDE addition instruction includes immediate, it is determined that add operation code DADDiu corresponding with the ADDE operation code；

Sub-step S34, if the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and The operand of SUBE subtraction instruction includes immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBE operation code；

Sub-step S35, if the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 32, and The operand of ADDE addition instruction does not include immediate, it is determined that add operation code ADDu corresponding with the ADDE operation code；

Sub-step S36, if the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 32, and The operand of SUBE subtraction instruction does not include immediate, it is determined that subtraction operation code SUBu corresponding with the SUBE operation code；

Sub-step S37, if the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 32, and The operand of ADDE addition instruction includes immediate, it is determined that add operation code ADDiu corresponding with the ADDE operation code；

Sub-step S38, if the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 32, and The operand of SUBE subtraction instruction includes immediate, it is determined that subtraction operation code SUBiu corresponding with the SUBE operation code.

Step 305, using the operand and object run code, the arithmetic instruction of the MIPS is generated.

In embodiments of the present invention, the operand of the ADDE addition instruction and the SUBE subtraction instruction includes: first Operand, second operand, input carry value；

First operand is specially left operand LHS (Left-Hand Side), and second operand is specially right operand RHS (right-Hand Side), input carry value are the values of input carry mark Carry.

In embodiments of the present invention, the step 305 may include following sub-step:

Sub-step S41 is generated using the first operand, second operand and the add operation code DADDu DADDu addition instruction；Or,

If the system digit of MIPS platform is 64, and the operand of ADDE addition instruction does not include immediate, then uses First operand, second operand and add operation code DADDu generate DADDu addition instruction；

Sub-step S42 is generated using the first operand, second operand and the subtraction operation code DSUBu DSUBu subtraction instruction；

If the system digit of MIPS platform is 64, and the operand of SUBE subtraction instruction does not include immediate, then uses First operand, second operand and subtraction operation code DSUBu generate DSUBu subtraction instruction；

Sub-step S43 is generated using the first operand, second operand and the add operation code DADDiu DADDiu addition instruction；

If the system digit of MIPS platform is 64, and the operand of ADDE addition instruction includes immediate, then using the One operand, second operand and add operation code DADDiu generate DADDiu addition instruction.

Sub-step S44 is generated using the first operand, second operand and the subtraction operation code DSUBiu DSUBiu subtraction instruction；

If the system digit of MIPS platform is 64, and the operand of SUBE subtraction instruction includes immediate, then using the One operand, second operand and subtraction operation code DSUBiu generate DSUBiu subtraction instruction.

Sub-step S45 is generated using the first operand, second operand and the add operation code ADDu ADDu addition instruction；

If the system digit of MIPS platform is 32, and the operand of ADDE addition instruction does not include immediate, then uses First operand, second operand and add operation code ADDu generate ADDu addition instruction.

Sub-step S46 is generated using the first operand, second operand and the subtraction operation code SUBu SUBu subtraction instruction；

If the system digit of MIPS platform is 32, and the operand of SUBE subtraction instruction does not include immediate, then uses First operand, second operand and subtraction operation code SUBu generate SUBu subtraction instruction.

Sub-step S47 is generated using the first operand, second operand and the add operation code ADDiu ADDiu addition instruction；

If the system digit of MIPS platform is 32, and the operand of ADDE addition instruction includes immediate, then using the One operand, second operand and add operation code ADDiu generate ADDiu addition instruction.

Sub-step S48 is generated using the first operand, second operand and the subtraction operation code SUBiu SUBiu subtraction instruction；

If the system digit of MIPS platform is 32, and the operand of SUBE subtraction instruction includes immediate, then using the One operand, second operand and subtraction operation code SUBiu generate SUBiu subtraction instruction.

Sub-step S49, using the input carry value, first operand and the second operand, generation export into Place value computations；

In embodiments of the present invention, the sub-step S49 may include following sub-step:

Sub-step S491 generates the first output carry value computations for the DADDu addition instruction；Described first Output carry value computations are used to execute the operation result using the DADDu addition instruction, operate respectively with described first The several and second operand is compared, and determines addition carry value；By the input carry value and the addition carry value phase Add, obtains the operation of output carry value；

In inventive embodiments, the calculation of the output carry value of different instruction is different.

For executing the instruction of add operation, output carry value is equal to input carry value, in addition the carry of add operation Value.

For executing the instruction of subtraction operation, output carry value is equal to input carry value, subtracts borrowing for subtraction Value.

Specifically, can determine addition carry value using compare instruction SLTu.SLTu instruction is meant, if condition is full Foot just sets 1, otherwise sets 0.

The operation result of DADDu addition instruction is the additive value of first operand and second operand.SLTu instruction passes through The operation result and any one of first operand or second operand for comparing DADDu addition instruction, if DADDu addition instruction Operation result be less than any one in first operand or second operand, then carry 1, is otherwise 0.Judge and is less than When any one addend, carry 1, otherwise not-carry.

Sub-step S492 generates the second output carry value computations for the DSUBu subtraction instruction；Described second Output carry value computations determine that subtraction borrows value for executing the first operand and the second operand； The input carry value is subtracted into the subtraction and borrows value, obtains the operation of output carry value；

For DSUBu subtraction instruction, SLTu instructs the value for comparing first operand and second operand, borrows if being less than 1, otherwise borrow 0.First operand is equivalent to minuend, and second operand is equivalent to subtrahend, that is, judges that minuend is less than subtrahend When, 1 is borrowed, otherwise borrows 0.

Sub-step S493 generates third output carry value computations for DADDiu addition instruction；The third output Carry value computations be used for executes use the DADDiu addition instruction operation result, respectively with the first operand and The second operand is compared, and determines addition carry value；The input carry value is added with the addition carry value, is obtained To the operation of output carry value；

The operation result of DADDiu addition instruction is the additive value of first operand and second operand.SLTu instruction is compared The operation result of DADDiu addition instruction and any one of first operand or second operand, if DADDiu addition instruction Operation result is less than any one in first operand or second operand, then carry 1, is otherwise 0.Judge and be less than to appoint Anticipate an addend when, carry 1, otherwise not-carry.

Sub-step S494 generates the 4th output carry value computations for DSUBiu subtraction instruction；4th output Carry value computations determine that subtraction borrows value for executing the first operand and the second operand；By institute It states input carry value and subtracts the subtraction and borrow value, obtain the operation of output carry value.

For DSUBiu subtraction instruction, SLTu instructs the value for comparing first operand and second operand, borrows if being less than Position 1, otherwise borrows 0.First operand is equivalent to minuend, and second operand is equivalent to subtrahend, that is, judges that minuend is less than and subtract When number, 1 is borrowed, otherwise borrows 0.

Sub-step S495 generates the 5th output carry value computations for ADDu addition instruction；Described 5th export into Place value computations are used to execute the operation result of the use ADDu addition instruction, respectively with the first operand and described Second operand is compared, and determines addition carry value；The input carry value is added with the addition carry value, is obtained defeated The operation of carry value out；

The operation result of ADDu addition instruction is the additive value of first operand and second operand.SLTu instruction is compared The operation result of ADDu addition instruction and any one of first operand or second operand, if the operation of ADDu addition instruction As a result less than any one in first operand or second operand, then carry 1, is otherwise 0.Judge and is less than any one When a addend, carry 1, otherwise not-carry.

Sub-step S496 generates the 6th output carry value computations for SUBu subtraction instruction；Described 6th export into Place value computations determine that subtraction borrows value for executing the first operand and the second operand；It will be described Input carry value subtracts the subtraction and borrows value, obtains the operation of output carry value；

For SUBu subtraction instruction, SLTu instructs the value for comparing first operand and second operand, borrows if being less than 1, otherwise borrow 0.First operand is equivalent to minuend, and second operand is equivalent to subtrahend, that is, judges that minuend is less than subtrahend When, 1 is borrowed, otherwise borrows 0.

Sub-step S497 generates the 7th output carry value computations for ADDiu addition instruction；7th output Carry value computations be used for executes use the ADDiu addition instruction operation result, respectively with the first operand and The second operand is compared, and determines addition carry value；The input carry value is added with the addition carry value, is obtained To the operation of output carry value；

The operation result of ADDiu addition instruction is the additive value of first operand and second operand.SLTu instruction is compared The operation result of ADDiu addition instruction and any one of first operand or second operand, if the fortune of ADDiu addition instruction Result is calculated less than any one in first operand or second operand, then carry 1, is otherwise 0.Judge and is less than any When one addend, carry 1, otherwise not-carry.

Sub-step S498 generates the 8th output carry value computations for SUBiu subtraction instruction；8th output Carry value computations determine that subtraction borrows value for executing the first operand and the second operand；By institute It states input carry value and subtracts the subtraction and borrow value, obtain the operation of output carry value；

For SUBiu subtraction instruction, SLTu instructs the value for comparing first operand and second operand, borrows if being less than 1, otherwise borrow 0.First operand is equivalent to minuend, and second operand is equivalent to subtrahend, that is, judges that minuend is less than subtrahend When, 1 is borrowed, otherwise borrows 0.

Sub-step S499 generates specific output carry value computations；The specific output carry value computations are used for If the second operand for executing ADDE addition instruction or SUBE subtraction instruction is 0, using input carry value as output carry value Operation.

If the second operand of ADDE addition instruction or SUBE subtraction instruction be 0, using input carry value as export into Place value.

Sub-step S50, in conjunction with the DADDu addition instruction and the output carry value computations, as ADDE addition Instruction is in the corresponding addition instruction of 64 target platforms；Or,

Sub-step S51, in conjunction with the DSUBu subtraction instruction and the output carry value computations, as SUBE subtraction Instruction is in the corresponding subtraction instruction of 64 target platforms；Or,

Sub-step S52, in conjunction with the DADDiu addition instruction and the output carry value computations, as ADDE addition Instruction is in the corresponding addition instruction of 64 target platforms；Or,

Sub-step S53, in conjunction with the DSUBiu subtraction instruction and the output carry value computations, as SUBE subtraction Instruction is in the corresponding subtraction instruction of 64 target platforms；Or,

Sub-step S54 refers in conjunction with the ADDu addition instruction and the output carry value computations as ADDE addition It enables in the corresponding addition instruction of 32 target platforms；Or,

Sub-step S55 refers in conjunction with the SUBu subtraction instruction and the output carry value computations as SUBE subtraction It enables in the corresponding subtraction instruction of 32 target platforms；Or,

Sub-step S56, in conjunction with the ADDiu addition instruction and the output carry value computations, as ADDE addition Instruction is in the corresponding addition instruction of 32 target platforms；Or,

Sub-step S57, in conjunction with the SUBiu subtraction instruction and the output carry value computations, as SUBE subtraction Instruction is in the corresponding subtraction instruction of 32 target platforms.

In the embodiment of the present invention, LLVM compiler is in the finger that counts that the arithmetic instruction of intermediate code is converted to MIPS platform When enabling, for 32 MIPS platforms, LLVM compiler can switch to the arithmetic instruction (ADDE/SUBE instruction) of intermediate code Arithmetic instruction on 32 MIPS platforms.For 64 MIPS platforms, LLVM compiler can be by the finger that counts of intermediate code (ADDE/SUBE instruction) is enabled to switch to the arithmetic instruction on 64 MIPS platforms.

In embodiments of the present invention, ADDC addition instruction only includes two operands, exports left operand LHS and right operation The additive value of number RHS.ADDE addition instruction includes three operands, exports being added for left operand LHS and right operand RHS Value and output carry value；Output carry value is equal to input carry value being added plus left operand LHS and right operand RHS Carry value.

Therefore, ADDE addition instruction switchs to the corresponding instruction of MIPS platform, switchs to the corresponding of MIPS platform with ADDC instruction Instruction is compared, and merely adds one for indicating the SLTu compare instruction of carry value.

For example, ADDC addition instruction to be converted to the instruction of 64 MIPS are as follows: DADDu addition instruction；

It include: DADD addition instruction by the instruction that ADDE addition instruction is converted to 64 MIPS, and for indicating carry The SLTu compare instruction of value.

It is as follows, it show the addition instruction that ADDE instruction is converted to 32 or 64 MIPS platforms in the embodiment of the present invention Code.

It should be noted that for simple description, therefore, it is stated as a series of action groups for embodiment of the method It closes, but those skilled in the art should understand that, embodiment of that present invention are not limited by the describe sequence of actions, because according to According to the embodiment of the present invention, some steps may be performed in other sequences or simultaneously.Secondly, those skilled in the art also should Know, the embodiments described in the specification are all preferred embodiments, and the related movement not necessarily present invention is implemented Necessary to example.

Referring to Fig. 4, show a kind of structural block diagram of instruction conversion equipment embodiment of the invention, can specifically include as Lower module:

Arithmetic instruction obtains module 401, for obtaining the arithmetic instruction of LLVM compiler intermediate code；

Operating parameter determining module 402, the operand of the arithmetic instruction for determining the LLVM compiler intermediate code And operation code；

System digit determining module 403, for determining the system digit of target platform；

Object run code determining module 404, in the instruction set of the target platform, the determining and LLVM to be compiled The arithmetic instruction operation code of device intermediate code and the corresponding object run code of the system digit；

Arithmetic instruction generation module 405 generates the calculation of target platform for using the operand and object run code Number instruction.

In a kind of example in embodiments of the present invention, the target platform is MIPS platform, and the arithmetic instruction includes: ADDC addition instruction and SUBC subtraction instruction；The operation code of the ADDC addition instruction is ADDC operation code；The SUBC subtraction The operation code of instruction is SUBC operation code；

The object run code determining module 404 may include:

In embodiments of the present invention, the operand of the ADDC addition instruction and the SUBC subtraction instruction includes: first Operand and second operand；The arithmetic instruction generation module 405 may include:

In another example in embodiments of the present invention, the target platform is MIPS platform, the arithmetic instruction packet It includes: ADDE addition instruction and SUBE subtraction instruction；The operation code of the ADDE addition instruction is ADDE operation code；The SUBE subtracts The operation code of method instruction is SUBE operation code；

The object run code determines that 404 may include:

The arithmetic instruction generation module 405 may include:

In embodiments of the present invention, the output carry value computations generation submodule may include:

In embodiments of the present invention, the output carry value computations, which generate submodule, to include:

For device embodiment, since it is basically similar to the method embodiment, related so being described relatively simple Place illustrates referring to the part of embodiment of the method.

Obtain the arithmetic instruction of LLVM compiler intermediate code；

Determine the system digit of target platform；

Preferably, it can also be performed the steps of when the processor executes described program

The embodiment of the invention also discloses a kind of computer readable storage mediums, are stored thereon with computer program, the journey The method of the embodiment of the present invention is realized when sequence is executed by processor.

All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.

It should be understood by those skilled in the art that, the embodiment of the embodiment of the present invention can provide as method, apparatus or calculate Machine program product.Therefore, the embodiment of the present invention can be used complete hardware embodiment, complete software embodiment or combine software and The form of the embodiment of hardware aspect.Moreover, the embodiment of the present invention can be used one or more wherein include computer can With in the computer-usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) of program code The form of the computer program product of implementation.

The embodiment of the present invention be referring to according to the method for the embodiment of the present invention, terminal device (system) and computer program The flowchart and/or the block diagram of product describes.It should be understood that flowchart and/or the block diagram can be realized by computer program instructions In each flow and/or block and flowchart and/or the block diagram in process and/or box combination.It can provide these Computer program instructions are set to general purpose computer, special purpose computer, Embedded Processor or other programmable data processing terminals Standby processor is to generate a machine, so that being held by the processor of computer or other programmable data processing terminal devices Capable instruction generates for realizing in one or more flows of the flowchart and/or one or more blocks of the block diagram The device of specified function.

These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing terminal devices In computer-readable memory operate in a specific manner, so that instruction stored in the computer readable memory generates packet The manufacture of command device is included, which realizes in one side of one or more flows of the flowchart and/or block diagram The function of being specified in frame or multiple boxes.

These computer program instructions can also be loaded into computer or other programmable data processing terminal devices, so that Series of operation steps are executed on computer or other programmable terminal equipments to generate computer implemented processing, thus The instruction executed on computer or other programmable terminal equipments is provided for realizing in one or more flows of the flowchart And/or in one or more blocks of the block diagram specify function the step of.

Although the preferred embodiment of the embodiment of the present invention has been described, once a person skilled in the art knows bases This creative concept, then additional changes and modifications can be made to these embodiments.So the following claims are intended to be interpreted as Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.

Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements not only wrap Those elements are included, but also including other elements that are not explicitly listed, or further includes for this process, method, article Or the element that terminal device is intrinsic.In the absence of more restrictions, being wanted by what sentence "including a ..." limited Element, it is not excluded that there is also other identical elements in process, method, article or the terminal device for including the element.

Above to a kind of instruction conversion method provided by the present invention and a kind of instruction conversion equipment, detailed Jie has been carried out It continues, used herein a specific example illustrates the principle and implementation of the invention, and the explanation of above embodiments is only It is to be used to help understand method and its core concept of the invention；At the same time, for those skilled in the art, according to this hair Bright thought, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not manage Solution is limitation of the present invention.

Claims

1. a kind of instruction conversion method characterized by comprising

Determine the system digit of target platform；

In the instruction set of the target platform, determining arithmetic instruction operation code with the LLVM compiler intermediate code and The corresponding object run code of the system digit；

2. the method according to claim 1, wherein the target platform is MIPS platform, the arithmetic instruction It include: ADDC addition instruction and SUBC subtraction instruction；The operation code of the ADDC addition instruction is ADDC operation code；The SUBC The operation code of subtraction instruction is SUBC operation code；

The target instruction target word in the target platform is concentrated, determining and the LLVM compiler intermediate code arithmetic instruction The step of operation code corresponding object run code includes:

If the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and the behaviour of ADDC addition instruction It counts and does not include immediate, it is determined that add operation code DADDu corresponding with the ADDC operation code；

If the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and the behaviour of SUBC subtraction instruction It counts and does not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBC operation code；

If the arithmetic instruction is ADDC addition instruction, the system digit of target platform is 64, and the behaviour of ADDC addition instruction It counts comprising immediate, it is determined that add operation code DADDiu corresponding with the ADDC operation code；

If the arithmetic instruction is SUBC subtraction instruction, the system digit of target platform is 64, and the behaviour of SUBC subtraction instruction It counts comprising immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBC operation code.

3. according to the method described in claim 2, it is characterized in that, the ADDC addition instruction and the SUBC subtraction instruction Operand includes: first operand and second operand；It is described to use the operand and object run code, it is flat to generate target The step of arithmetic instruction of platform includes:

Using the first operand, the second operand and the add operation code DADDu, ADDC addition instruction is generated In the corresponding addition instruction of 64 target platforms；Or,

Using the first operand, the second operand and the subtraction operation code DSUBu, SUBC subtraction instruction is generated In the corresponding subtraction instruction of 64 target platforms；Or,

Using the first operand, the second operand and the add operation code DADDiu, generates ADDC addition and refer to It enables in the corresponding addition instruction of 64 target platforms；Or,

Using the first operand, the second operand and the subtraction operation code DSUBiu, generates SUBC subtraction and refer to It enables in the corresponding subtraction instruction of 64 target platforms.

4. the method according to claim 1, wherein the target platform is MIPS platform, the arithmetic instruction It include: ADDE addition instruction and SUBE subtraction instruction；The operation code of the ADDE addition instruction is ADDE operation code；The SUBE The operation code of subtraction instruction is SUBE operation code；

It is described in the instruction set of the target platform, the determining arithmetic instruction operation code with the LLVM compiler intermediate code And the step of system digit corresponding object run code, includes:

If the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and the behaviour of ADDE addition instruction It counts and does not include immediate, it is determined that add operation code DADDu corresponding with the ADDE operation code；

If the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and the behaviour of SUBE subtraction instruction It counts and does not include immediate, it is determined that subtraction operation code DSUBu corresponding with the SUBE operation code；

If the arithmetic instruction is ADDE addition instruction, the system digit of target platform is 64, and the behaviour of ADDE addition instruction It counts comprising immediate, it is determined that add operation code DADDiu corresponding with the ADDE operation code；

If the arithmetic instruction is SUBE subtraction instruction, the system digit of target platform is 64, and the behaviour of SUBE subtraction instruction It counts comprising immediate, it is determined that subtraction operation code DSUBiu corresponding with the SUBE operation code.

5. according to the method described in claim 4, it is characterized in that, the ADDE addition instruction and the SUBE subtraction instruction Operand includes: first operand, second operand, input carry value；

Using the first operand, second operand and the add operation code DADDu, DADDu addition instruction is generated； Or,

Using the first operand, second operand and the subtraction operation code DSUBu, DSUBu subtraction instruction is generated； Or,

Using the first operand, second operand and the add operation code DADDiu, DADDiu addition instruction is generated； Or,

Using the first operand, second operand and the subtraction operation code DSUBiu, DSUBiu subtraction instruction is generated；

Using the input carry value, first operand and the second operand, output carry value computations are generated；

In conjunction with the DADDu addition instruction and the output carry value computations, as ADDE addition instruction in 64 targets The corresponding addition instruction of platform；Or,

In conjunction with the DSUBu subtraction instruction and the output carry value computations, as SUBE subtraction instruction in 64 targets The corresponding subtraction instruction of platform；Or,

In conjunction with the DADDiu addition instruction and the output carry value computations, as ADDE addition instruction in 64 targets The corresponding addition instruction of platform；Or,

In conjunction with the DSUBiu subtraction instruction and the output carry value computations, as SUBE subtraction instruction in 64 targets The corresponding subtraction instruction of platform.

6. according to the method described in claim 5, it is characterized in that, it is described use the input carry value, first operand with And the second operand, generate output carry value computations the step of include:

For the DADDu addition instruction, the first output carry value computations are generated；The first output carry value calculating refers to It enables for executing the operation result using the DADDu addition instruction, is operated respectively with the first operand and described second Number is compared, and determines addition carry value；The input carry value is added with the addition carry value, obtains output carry value Operation；

For the DSUBu subtraction instruction, the second output carry value computations are generated；The second output carry value calculating refers to It enables for executing the first operand and the second operand, determines that subtraction borrows value；By the input carry value It subtracts the subtraction and borrows value, obtain the operation of output carry value；

For DADDiu addition instruction, third output carry value computations are generated；The third output carry value computations For executing the operation result using the DADDiu addition instruction, respectively with the first operand and the second operand It is compared, determines addition carry value；The input carry value is added with the addition carry value, obtains output carry value Operation；

For DSUBiu subtraction instruction, the 4th output carry value computations are generated；The 4th output carry value computations For executing the first operand and the second operand, determine that subtraction borrows value；The input carry value is subtracted It goes the subtraction to borrow value, obtains the operation of output carry value.

7. method according to claim 5 or 6, which is characterized in that described to use the input carry value, first operand And the second operand, generate output carry value computations the step of further include:

Generate specific output carry value computations；If the specific output carry value computations refer to for executing ADDE addition It enables or the second operand of SUBE subtraction instruction is 0, then using input carry value as the operation of output carry value.

8. a kind of instruction conversion equipment characterized by comprising

Operating parameter determining module, for determining operand and the operation of the arithmetic instruction of the LLVM compiler intermediate code Code；

Object run code determining module, in the instruction set of the target platform, it is determining among the LLVM compiler The arithmetic instruction operation code of code and the corresponding object run code of the system digit；

Arithmetic instruction generation module generates the arithmetic instruction of target platform for using the operand and object run code.

9. device according to claim 8, which is characterized in that the target platform is MIPS platform, the arithmetic instruction It include: ADDC addition instruction and SUBC subtraction instruction；The operation code of the ADDC addition instruction is ADDC operation code；The SUBC The operation code of subtraction instruction is SUBC operation code；

The object run code determining module includes:

First operation code determines submodule, if being ADDC addition instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of ADDC addition instruction does not include immediate, it is determined that addition behaviour corresponding with the ADDC operation code Make code DADDu；

Second operation code determines submodule, if being SUBC subtraction instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of SUBC subtraction instruction does not include immediate, it is determined that subtraction behaviour corresponding with the SUBC operation code Make code DSUBu；

Third operation code determines submodule, if being ADDC addition instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of ADDC addition instruction includes immediate, it is determined that add operation corresponding with the ADDC operation code Code DADDiu；

4th operation code determines submodule, if being SUBC subtraction instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of SUBC subtraction instruction includes immediate, it is determined that subtraction operation corresponding with the SUBC operation code Code DSUBiu.

10. device according to claim 9, which is characterized in that the ADDC addition instruction and the SUBC subtraction instruction Operand include: first operand and second operand；The arithmetic instruction generation module includes:

First arithmetic instruction generates submodule, for using the first operand, the second operand and the addition Operation code DADDu generates ADDC addition instruction in the corresponding addition instruction of 64 target platforms；Or,

Second arithmetic instruction generates submodule, for using the first operand, the second operand and the subtraction Operation code DSUBu generates SUBC subtraction instruction in the corresponding subtraction instruction of 64 target platforms；Or,

Third arithmetic instruction generates submodule, for using the first operand, the second operand and the addition Operation code DADDiu generates ADDC addition instruction in the corresponding addition instruction of 64 target platforms；Or,

4th arithmetic instruction generates submodule, for using the first operand, the second operand and the subtraction Operation code DSUBiu generates SUBC subtraction instruction in the corresponding subtraction instruction of 64 target platforms.

11. device according to claim 8, which is characterized in that the target platform is MIPS platform, the arithmetic instruction It include: ADDE addition instruction and SUBE subtraction instruction；The operation code of the ADDE addition instruction is ADDE operation code；The SUBE The operation code of subtraction instruction is SUBE operation code；

The object run code determination includes:

5th operation code determines submodule, if being ADDE addition instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of ADDE addition instruction does not include immediate, it is determined that addition behaviour corresponding with the ADDE operation code Make code DADDu；

6th operation code determines submodule, if being SUBE subtraction instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of SUBE subtraction instruction does not include immediate, it is determined that subtraction behaviour corresponding with the SUBE operation code Make code DSUBu；

7th operation code determines submodule, if being ADDE addition instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of ADDE addition instruction includes immediate, it is determined that add operation corresponding with the ADDE operation code Code DADDiu；

8th operation code determines submodule, if being SUBE subtraction instruction, the system digit of target platform for the arithmetic instruction It is 64, and the operand of SUBE subtraction instruction includes immediate, it is determined that subtraction operation corresponding with the SUBE operation code Code DSUBiu.

12. device according to claim 11, which is characterized in that the ADDE addition instruction and the SUBE subtraction instruction Operand include: first operand, second operand, input carry value；

The arithmetic instruction generation module includes:

5th arithmetic instruction generates submodule, for using the first operand, second operand and the add operation Code DADDu, generates DADDu addition instruction；Or,

6th arithmetic instruction generates submodule, for using the first operand, second operand and subtraction operation Code DSUBu, generates DSUBu subtraction instruction；Or,

7th arithmetic instruction generates submodule, for using the first operand, second operand and the add operation Code DADDiu, generates DADDiu addition instruction；Or,

8th arithmetic instruction generates submodule, for using the first operand, second operand and subtraction operation Code DSUBiu, generates DSUBiu subtraction instruction；

Output carry value computations generate submodule, for using the input carry value, first operand and described the Two operands generate output carry value computations；

9th arithmetic instruction generates submodule, is used in conjunction with the DADDu addition instruction and the output carry value computations, As ADDE addition instruction in the corresponding addition instruction of 64 target platforms；Or,

Tenth arithmetic instruction generates submodule, is used in conjunction with the DSUBu subtraction instruction and the output carry value computations, As SUBE subtraction instruction in the corresponding subtraction instruction of 64 target platforms；Or,

11st arithmetic instruction generates submodule, for referring in conjunction with the DADDiu addition instruction and output carry value calculating It enables, as ADDE addition instruction in the corresponding addition instruction of 64 target platforms；Or,

12nd arithmetic instruction generates submodule, for referring in conjunction with the DSUBiu subtraction instruction and output carry value calculating It enables, as SUBE subtraction instruction in the corresponding subtraction instruction of 64 target platforms.

13. device according to claim 12, which is characterized in that the output carry value computations generate submodule packet It includes:

First output carry value computing unit, for generating the calculating of the first output carry value and referring to for the DADDu addition instruction It enables；The first output carry value computations be used for executes use the DADDu addition instruction operation result, respectively with institute It states first operand and the second operand is compared, determine addition carry value；The input carry value is added with described Method carry value is added, and obtains the operation of output carry value；

Second output carry value computing unit, for generating the calculating of the second output carry value and referring to for the DSUBu subtraction instruction It enables；The second output carry value computations are determined for executing the first operand and the second operand Subtraction borrows value；The input carry value is subtracted into the subtraction and borrows value, obtains the operation of output carry value；

Third output carry value computing unit, for generating third output carry value computations for DADDiu addition instruction； The third output carry value computations be used for executes use the DADDiu addition instruction operation result, respectively with it is described First operand and the second operand are compared, and determine addition carry value；By the input carry value and the addition Carry value is added, and obtains the operation of output carry value；

4th output carry value computing unit, for generating the 4th output carry value computations for DSUBiu subtraction instruction； The 4th output carry value computations determine subtraction for executing the first operand and the second operand Borrow value；The input carry value is subtracted into the subtraction and borrows value, obtains the operation of output carry value.

14. device according to claim 12 or 13, which is characterized in that the output carry value computations generate submodule Block further include:

Specific output carry value computing unit, for generating specific output carry value computations；The specific output carry value If it is 0 that computations, which are used to execute ADDE addition instruction or the second operand of SUBE subtraction instruction, input carry value is made For the operation of output carry value.

15. a kind of electronic equipment including memory, processor and stores the calculating that can be run on a memory and on a processor Machine program, which is characterized in that the processor performs the steps of when executing described program

Obtain the arithmetic instruction of LLVM compiler intermediate code；

Determine the system digit of target platform；

16. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the program is by processor The step of any one of claim 1 to 7 the method is realized when execution.