CN109473430A - Single layer polycrystalline structure EEPROM based on standard CMOS process - Google Patents
Single layer polycrystalline structure EEPROM based on standard CMOS process Download PDFInfo
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- CN109473430A CN109473430A CN201811456480.7A CN201811456480A CN109473430A CN 109473430 A CN109473430 A CN 109473430A CN 201811456480 A CN201811456480 A CN 201811456480A CN 109473430 A CN109473430 A CN 109473430A
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- 239000002356 single layer Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000007667 floating Methods 0.000 claims abstract description 66
- 239000003990 capacitor Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 7
- 210000004899 c-terminal region Anatomy 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of single layer polycrystalline structure EEPROM, including P-type silicon substrate, are arranged at the first N-type trap and the second N-type trap and coupled capacitor pipe and PMOS transistor of P-type silicon substrate；Coupled capacitor pipe includes the first floating gate, coupled capacitor end and the first gate oxide, and coupled capacitor end and the first gate oxide are arranged in the first N-type trap, and the first floating gate is arranged on the first gate oxide；The P that PMOS transistor includes the second floating gate, is arranged in the second N-type trap+Source doping region, P+Drain doping region, N+Substrate doped region and the second gate oxide, the second floating gate are arranged on the second gate oxide；Second floating gate is conductively connected the first floating gate by floating gate.Single layer polycrystalline structure EEPROM of the invention, by the structure for improving EEPROM, enable to bear operation voltage when erasing, it can be produced at the same time based on standard CMOS process, and not only it is confined to certain special processes, improve the compatibility of single layer polycrystalline structure EEPROM, is conducive to reduce manufacturing cost.
Description
Technical field
The invention belongs to technical field of semiconductor memory, and in particular to a kind of single layer polycrystalline knot based on standard CMOS process
Structure EEPROM.
Background technique
Electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only
Memory, referred to as " EEPROM ") with erasable performance reversible, erasable and writing speed is fast, data are not lost after power down, it is widely used in
The fields such as in-line memory, Internet of Things.
As shown in Figure 1, being the circuit diagram of conventional monolayers polycrystalline structure eeprom memory, Fig. 2 is shown shown in Fig. 1
The diagrammatic cross-section of eeprom memory.Its storage unit is formed using NMOS tube and PMOS tube, and PMOS tube is used as coupled capacitor
Pipe, NMOS tube are used as tunneltron and readout tube, and PMOS tube is arranged in N-type trap, and N-type trap is arranged on P-type silicon substrate, NMOS tube
It is arranged on P-type silicon substrate.The floating gate that PMOS tube is connected with the grid of NMOS tube as EEPROM, the N of PMOS tube+Doped region and
Two P+Doped region connects to form coupled capacitor end (C-terminal)；The P of NMOS tube+Doped region ground connection, a N+Doped region forms drain terminal,
One N+Doped region forms source.Conventional monolayers polycrystalline structure eeprom memory is when executing erasing operation, the coupling of PMOS tube
Capacitance terminal (C-terminal) plus low-voltage (0V) is closed, the source (end S) and drain terminal (end D) of NMOS tube add high pressure (10~15V), P-type silicon base
Material (Psub) is grounded (0V).For special process, the EEPROM of this structure be can work normally, but in some techniques
In, the N of NMOS tube+Source and P-type silicon substrate and N+The diode that drain terminal and P-type silicon substrate are formed cannot bear high pressure, lead
Cause the EEPROM of this structure that there is limitation in actual application.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of single layer polycrystalline structure EEPROM, by the knot for improving EEPROM
Structure enables to bear operation voltage when erasing, can be produced at the same time based on standard CMOS process, and not only office
It is limited to certain special processes, improves the compatibility of single layer polycrystalline structure EEPROM, is conducive to reduce manufacturing cost.
In order to solve the above-mentioned technical problems, the present invention provides a kind of single layer polycrystalline structure based on standard CMOS process
EEPROM, including,
P-type silicon substrate；
First N-type trap is arranged on the P-type silicon substrate；
Second N-type trap is arranged on the P-type silicon substrate；
Coupled capacitor pipe comprising the first floating gate, coupled capacitor end and the first gate oxide, the coupled capacitor end and
One gate oxide is arranged in first N-type trap, and first floating gate is arranged on first gate oxide；
PMOS transistor is used as the tunneltron and readout tube of the EEPROM；It includes the second floating gate, P+Source dopant
Area, P+Drain doping region, N+Substrate doped region and the second gate oxide；The P+Source doping region, P+Drain doping region, N+Substrate
Doped region and the second gate oxide are arranged in second N-type trap, and second floating gate is arranged on the second gate oxide；
Second floating gate is conductively connected first floating gate by floating gate.
In a preferred embodiment of the present invention, further comprise the coupled capacitor pipe be PMOS transistor comprising
N in first N-type trap is set+Doped region and two the first P+Doped region, the N+Doped region and two the first P+Doping
Area is conductively connected to form the coupled capacitor end.
It further comprise being located at the first N-type trap and the 2nd N on the P-type silicon substrate in a preferred embodiment of the present invention
The 2nd P is equipped between type trap+Doped region.
It further comprise the floating gate, the first floating gate and the second floating gate is single layer in a preferred embodiment of the present invention
Polysilicon structure.
It further comprise that first floating gate and the second floating gate are connected by floating gate conduction in a preferred embodiment of the present invention
It connects, so that the second grid oxygen that the first gate oxide capacitance and second gate oxide that first gate oxide is formed are formed
Change layer capacitance series connection；The coefficient of coup of the coupled capacitor pipe is the ratio of the first gate oxide capacitance and the second gate oxide capacitance
Value.
In a preferred embodiment of the present invention, further comprise the coupled capacitor pipe the coefficient of coup be 5~15.
Beneficial effects of the present invention: single layer polycrystalline structure EEPROM of the invention changes conventional monolayers polycrystalline structure
The structure of EEPROM designs, and is used as tunneltron and readout tube using PMOS tube, when executing erasing operation, the heavy doping P of PMOS tube+
Source and heavy doping P+There is no pressure drop between drain terminal and the first N-type trap, pressure drop load is lightly doped the be able to bear high pressure
One N-type trap and be lightly doped P-type silicon substrate formation diode structure between so that when EEPROM device is able to bear erasing
Operation high pressure, can be produced at the same time based on standard CMOS process, and certain special processes are not only confined to, with this
Improve the compatibility of single layer polycrystalline structure EEPROM, is conducive to reduce manufacturing cost.
Detailed description of the invention
Fig. 1 is the circuit diagram of conventional monolayers polycrystalline structure eeprom memory；
Fig. 2 is the diagrammatic cross-section of eeprom memory in Fig. 1；
Fig. 3 is the circuit diagram of single layer polycrystalline structure EEPROM in the preferred embodiment of the present invention；
Fig. 4 is the diagrammatic cross-section of single layer polycrystalline structure EEPROM in Fig. 3；
Fig. 5 is equivalent circuit diagram of the single layer polycrystalline structure EEPROM under programming mode in the preferred embodiment of the present invention；
Fig. 6 is the equivalent circuit diagram of single layer polycrystalline structure EEPROM in the erase mode in the preferred embodiment of the present invention.
In Fig. 3-4: CP1 → coupled capacitor pipe；CP2 → PMOS tube；S → PMOS source end；D → PMOS tube drain terminal；W→
PMOS tube N trap substrate；FG → floating gate；GND→0V；C → coupled capacitor end；The floating gate of 11a → first；The floating gate of 11b → second；12a
→ the first gate oxide；The gate oxide of 12b → second；P+→ p-type heavily doped region；N+→ N-type heavily doped region；The N of Nwell1 → the first
Type trap；The N-type trap of Nwell2 → second；Psub → P-type silicon substrate；
The gate oxide capacitance of C1 → first；The gate oxide capacitance of C2 → second.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings and specific examples, so that those skilled in the art can be with
It more fully understands the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention.
Embodiment
As shown in Figure 3-4, present embodiment discloses a kind of single layer polycrystalline structure EEPROM, can be based on standard CMOS process
Production, and it is not limited solely to specific CMOS technology, preferred structure is as follows:
It includes P-type silicon substrate Psub, the first N-type trap Nwell1, the second N-type trap Nwell2, coupled capacitor pipe CP1 and use
Make the PMOS transistor CP2 of tunneltron and readout tube.Wherein, the first N-type trap Nwell1, the second N-type trap Nwell2 pass through diffusion
Or the mode of ion implanting is formed on P-type silicon substrate Psub；Coupled capacitor pipe CP1 is arranged on the first N-type trap Nwell1,
PMOS transistor CP2 is arranged on the second N-type trap Nwell2.
Specifically, coupled capacitor pipe CP1 includes the first floating gate 11a, coupled capacitor end C and the first gate oxide 12a, it is above-mentioned
Coupled capacitor end C and the first gate oxide 12a is arranged on above-mentioned first N-type trap Nwell1, above-mentioned first floating gate 11a setting
On above-mentioned first gate oxide 12a；Above-mentioned first gate oxide 12a forms the first gate oxide capacitance, the first floating gate 11a and
First N-type trap Nwell1 is respectively formed two pole plates of the first gate oxide capacitance.
PMOS transistor CP2 includes second floating gate 11b, P+Source doping region, P+Drain doping region, N+Substrate doped region and
Second gate oxide 12b；Above-mentioned P+Source doping region, P+Drain doping region, N+Substrate doped region and the second gate oxide 12b are equal
It is formed in by way of ion implanting on above-mentioned second N-type trap Nwell2, above-mentioned second floating gate 11b is arranged in the second gate oxidation
On layer 12b；Above-mentioned second gate oxide 12b forms the second gate oxide capacitance, the second floating gate 11b and the second N-type trap Nwell2
It is respectively formed two pole plates of the second gate oxide capacitance.
Above-mentioned second floating gate 11b is conductively connected above-mentioned first floating gate 11a by floating gate FG, so that the first gate oxide capacitance
It connects with the second gate oxide capacitance.In the present embodiment technical solution, above-mentioned first floating gate 11a, the second floating gate 11b and floating gate FG
It is integrally formed using single level polysilicon material in technique, form a floating gate overall structure.The coupling of above-mentioned coupled capacitor pipe CP1
Collaboration number is the ratio of the first gate oxide capacitance and the second gate oxide capacitance.
Above-mentioned coupled capacitor pipe CP1 is used as capacitance tube, and in one embodiment, coupled capacitor pipe CP1 is directly selected
Capacitance tube, in another embodiment, coupled capacitor pipe CP1 is it is preferable to use PMOS transistor, compared to using capacitance tube, this reality
It applies in a technical solution, it is preferable to use PMOS transistors by above-mentioned coupled capacitor pipe CP1, in the premise with identical coupled capacitor
Under, the size of PMOS transistor be can be made smaller.Selecting the coupled capacitor pipe CP1 of PMOS tube includes passing through ion implanting side
Formula is formed in the N on the first N-type trap Nwell1+Doped region and two the first P+Doped region, above-mentioned N+Doped region and two the first P+
Doped region is conductively connected to form above-mentioned coupled capacitor end C.
The single layer polycrystalline structure EEPROM of the above structure, a PMOS tube are used as coupled capacitor pipe, and a PMOS tube is used as
Tunneltron and readout tube, the floating gate that the grid end of two PMOS tube is connected as EEPROM memory cell, floating gate are mainly used for storing
Charge is not connected with other parts；Two PMOS tube are in N-type trap, and N-type trap is on P-type silicon substrate, and on P-type silicon substrate
The 2nd P is equipped between the first N-type trap Nwell1 and the second N-type trap Nwell2+Doped region ground connection, the EEPROM symbol of this structure
Standardization CMOS technology.The coefficient of coup of coupled capacitor pipe CP1 is the first gate oxide capacitance and the second gate oxide capacitance
Ratio, in the present embodiment technical solution, the coefficient of coup of above-mentioned coupled capacitor pipe is 5~15, the coefficient of coup of coupled capacitor pipe
Determine the voltage dividing ability of the first gate oxide capacitance and the second gate oxide capacitance.
There are three types of operation modes, respectively programming mode, erasing mode by single layer polycrystalline structure EEPROM proposed by the present invention
And read mode, table 1 is operation voltage of the present invention under different operation modes, below in conjunction with 1 pair of table single layer polycrystalline of the present invention
The course of work of structure EEPROM is illustrated.
Table 1
| Operation mode | C | S | D | W |
| Programming | VP | 0 | 0 | 0 |
| Erasing | 0 | VE | VE | VE |
| It reads | VR | VDD | PullDown | VDD |
(1) under programming mode:
The C-terminal of coupled capacitor pipe CP1 adds program voltage VP (high pressure that program voltage VP is 10V~20V herein), PMOS tube
Source S, drain terminal D and the substrate W of CP2 adds low-voltage (0V).The first gate oxide capacitance C1 and PMOS of coupled capacitor pipe CP1
The second gate oxide capacitance C2 of pipe CP2, which connects, to be divided, since the coefficient of coup is larger (5~15), most program voltages
VP is acted on the second gate oxide capacitance C2 of PMOS tube CP2.
The application in one embodiment, choose coupled capacitor pipe CP1 the coefficient of coup be 15/2, program voltage
VP is 17V, the equivalent circuit diagram being illustrated in figure 5 under programming mode, and ideally program voltage VP has 2V load first
On gate oxide capacitance C1,15V is loaded on the second gate oxide capacitance C2.Floating gate FG (the first floating gate 11a, the second floating gate
11b, floating gate FG connection, three's potential having the same) potential be 15V, the potential of the second N-type trap Nwell2 is 0V (the 2nd N
Type trap Nwell2 is connected with the substrate W of PMOS tube CP2, has same potential 0V), the electricity in the second N-type trap Nwell2
FN tunneling effect occurs under the high electric-field intensity that son is formed between floating gate FG and the second N-type trap Nwell2 and enters floating gate FG.
(2) under erasing mode:
The C-terminal of coupled capacitor pipe CP1 adds low-voltage 0V, the source S of PMOS tube CP2, drain terminal D and substrate W to add erasing electricity
Press VE (high pressure that erasing voltage VE is 10V~20V herein).The first gate oxide capacitance C1 and PMOS of coupled capacitor pipe CP1
The second gate oxide capacitance C2 of pipe CP2, which connects, to be divided, also due to the coefficient of coup is larger (5~15), most erasings
Voltage VE is acted on the second gate oxide capacitance C2 of PMOS tube CP2.
The application in one embodiment, choose coupled capacitor pipe CP1 the coefficient of coup be 15/2, erasing voltage
VE is 17V, the equivalent circuit diagram being illustrated in figure 6 under erasing mode, and ideally erasing voltage VE has 2V load first
On gate oxide capacitance C1,15V is loaded on the second gate oxide capacitance C2.Floating gate FG (the first floating gate 11a, the second floating gate
11b, floating gate FG connection, three's potential having the same) potential be 2V, the potential of the second N-type trap Nwell2 is 15V (the 2nd N
Type trap Nwell2 is connected with the substrate W of PMOS tube CP2, has same potential 15V), the electronics in floating gate FG is in the 2nd N
FN tunneling effect occurs under the high electric-field intensity formed between type trap Nwell2 and floating gate FG, " is run out of " from floating gate FG.
When executing erasing operation, source S, the drain terminal D and substrate W of PMOS tube CP2 is connected, substrate W and the second N-type trap
Nwell2 is connected, the P of heavy doping at this time+The source S and P of heavy doping+It is not pressed between drain terminal D and the second N-type trap Nwell2
Drop, pressure drop load are being lightly doped the second N-type trap Nwell2 and are being lightly doped between the diode structure of P-type silicon substrate formation, and light
Second N-type trap Nwell2 of doping and the P-type silicon substrate Psub being lightly doped are able to bear high pressure, so that EEPROM device energy
Enough erasing voltage VE (high pressure) born when wiping can be produced at the same time based on standard CMOS process, and not only office
It is limited to certain special processes, improves the compatibility of single layer polycrystalline structure EEPROM with this, is conducive to reduce manufacturing cost.
(3) under read mode:
The C-terminal of coupled capacitor pipe CP1, which adds, reads voltage VR, and the source S and substrate W of PMOS tube CP2 powers up voltage
VDD, drain terminal D pull down Pull Down.It reads voltage VR and is less than supply voltage VDD, the external sensitive amplification of the drain terminal D of PMOS tube CP2
Circuit obtains read current, since the electron amount on floating gate will affect the threshold voltage of PMOS tube CP2, can finally pass through reading
The size of electric current determines the state of storage unit.
Embodiment described above is only to absolutely prove preferred embodiment that is of the invention and being lifted, protection model of the invention
It encloses without being limited thereto.Those skilled in the art's made equivalent substitute or transformation on the basis of the present invention, in the present invention
Protection scope within.Protection scope of the present invention is subject to claims.
Claims (6)
1. a kind of single layer polycrystalline structure EEPROM based on standard CMOS process, it is characterised in that: including,
P-type silicon substrate；
First N-type trap is arranged on the P-type silicon substrate；
Second N-type trap is arranged on the P-type silicon substrate；
Coupled capacitor pipe comprising the first floating gate, coupled capacitor end and the first gate oxide, the coupled capacitor end and the first grid
Oxide layer is arranged in first N-type trap, and first floating gate is arranged on first gate oxide；
PMOS transistor is used as the tunneltron and readout tube of the EEPROM；It includes the second floating gate, P+Source doping region, P+
Drain doping region, N+Substrate doped region and the second gate oxide；The P+Source doping region, P+Drain doping region, N+Substrate doping
Area and the second gate oxide are arranged in second N-type trap, and second floating gate is arranged on the second gate oxide；It is described
Second floating gate is conductively connected first floating gate by floating gate.
2. the single layer polycrystalline structure EEPROM based on standard CMOS process as described in claim 1, it is characterised in that: the coupling
Conjunction capacitance tube is PMOS transistor comprising the N being arranged in first N-type trap+Doped region and two the first P+Doping
Area, the N+Doped region and two the first P+Doped region is conductively connected to form the coupled capacitor end.
3. the single layer polycrystalline structure EEPROM based on standard CMOS process as described in claim 1, it is characterised in that: the P
The 2nd P is equipped on type silicon substrate between the first N-type trap and the second N-type trap+Doped region.
4. the single layer polycrystalline structure EEPROM based on standard CMOS process as described in claim 1, it is characterised in that: described floating
Grid, the first floating gate and the second floating gate are single level polysilicon structure.
5. the single layer polycrystalline structure EEPROM based on standard CMOS process as described in claim 1, it is characterised in that: described
One floating gate and the second floating gate are conductively connected by floating gate so that the first gate oxide capacitance that first gate oxide is formed and
The second gate oxide capacitance series connection that second gate oxide is formed；The coefficient of coup of the coupled capacitor pipe is the first grid oxygen
Change the ratio of layer capacitance and the second gate oxide capacitance.
6. the single layer polycrystalline structure EEPROM based on standard CMOS process as claimed in claim 5, it is characterised in that: the coupling
The coefficient of coup for closing capacitance tube is 5~15.
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| CN201811456480.7A CN109473430A (en) | 2018-11-30 | 2018-11-30 | Single layer polycrystalline structure EEPROM based on standard CMOS process |
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| CN201811456480.7A CN109473430A (en) | 2018-11-30 | 2018-11-30 | Single layer polycrystalline structure EEPROM based on standard CMOS process |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512700B1 (en) * | 2001-09-20 | 2003-01-28 | Agere Systems Inc. | Non-volatile memory cell having channel initiated secondary electron injection programming mechanism |
| TW201030947A (en) * | 2009-02-10 | 2010-08-16 | Aplus Flash Technology Inc | Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device |
| CN103378105A (en) * | 2012-04-27 | 2013-10-30 | 韩国电子通信研究院 | Non-volatile memory (nvm) and method for manufacturing thereof |
| CN104123962A (en) * | 2014-07-21 | 2014-10-29 | 中国人民解放军国防科学技术大学 | Single-grid nonvolatile storage cell with low polycrystal doping concentration |
| CN208970510U (en) * | 2018-11-30 | 2019-06-11 | 江苏集萃微纳自动化系统与装备技术研究所有限公司 | Single layer polycrystalline structure EEPROM based on standard CMOS process |
-
2018
- 2018-11-30 CN CN201811456480.7A patent/CN109473430A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6512700B1 (en) * | 2001-09-20 | 2003-01-28 | Agere Systems Inc. | Non-volatile memory cell having channel initiated secondary electron injection programming mechanism |
| TW201030947A (en) * | 2009-02-10 | 2010-08-16 | Aplus Flash Technology Inc | Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device |
| CN103378105A (en) * | 2012-04-27 | 2013-10-30 | 韩国电子通信研究院 | Non-volatile memory (nvm) and method for manufacturing thereof |
| CN104123962A (en) * | 2014-07-21 | 2014-10-29 | 中国人民解放军国防科学技术大学 | Single-grid nonvolatile storage cell with low polycrystal doping concentration |
| CN208970510U (en) * | 2018-11-30 | 2019-06-11 | 江苏集萃微纳自动化系统与装备技术研究所有限公司 | Single layer polycrystalline structure EEPROM based on standard CMOS process |
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