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CN109474558B - Wireless triggering system and method based on FPGA - Google Patents

Wireless triggering system and method based on FPGA Download PDF

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CN109474558B
CN109474558B CN201811603823.8A CN201811603823A CN109474558B CN 109474558 B CN109474558 B CN 109474558B CN 201811603823 A CN201811603823 A CN 201811603823A CN 109474558 B CN109474558 B CN 109474558B
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CN109474558A (en
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蒋伊琳
张佳
郜丽鹏
赵忠凯
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Harbin Engineering University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
    • H04B7/0413—MIMO systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J13/00—Code division multiplex systems
    • H04J13/0007—Code type
    • H04J13/0055—ZCZ [zero correlation zone]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2649—Demodulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26

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Abstract

A wireless trigger system and method based on FPGA belongs to the field of trigger control. The wireless trigger system mainly comprises an FPGA baseband processing module, a D/A digital-to-analog conversion module, a radio frequency transceiver module, an A/D analog-to-digital conversion module and a power supply module; BPSK-OFDM signals generated by the FPGA baseband processing module are subjected to up-conversion to 2.4GHz through the D/A digital-to-analog conversion module and the radio frequency transceiving module and are transmitted through the antenna, the received signals are down-converted back to baseband signals through the radio frequency transceiving module by the receiving antenna and then transmitted to the FPGA through the A/D analog-to-digital conversion module, the FPGA performs quick sliding related detection and judgment on the received signals and local signals, and if a related detection result is larger than a set threshold value, the FPGA triggers. The invention adopts a wireless triggering mode, has strong environmental adaptability and wide application range; the code group ZCZ code with good correlation characteristics is selected as a trigger signal, so that the detection method is not easily interfered by noise and has high detection success rate; the receiving end adopts a mechanism of receiving and detecting simultaneously, and the data receiving and detecting are finished simultaneously, thereby greatly shortening the triggering time.

Description

Wireless triggering system and method based on FPGA
Technical Field
The invention belongs to the field of trigger control, and particularly relates to a wireless trigger system and method based on an FPGA (field programmable gate array).
Background
In some fields with high dangerousness, places inconvenient for wired wiring, places with high requirements on mobile performance and application places with wide distribution, the traditional wired trigger cannot meet the requirements of the system.
With the advancement of wireless communication technologies, the demand for wireless triggering and control technologies is gradually increasing in various fields. In certain specific fields, wireless triggering and control techniques often place higher demands on the synchronization of the system and the reliability of data transmission. For example, in the land seismic exploration work, due to the complex terrain, the wide operation range is wide, the adoption of wired transmission is inconvenient, and in many occasions, the wireless trigger control technology can become an important auxiliary system for large-area detector network arrangement, clock synchronization and trigger control, and has important and wide potential application value. And the wireless trigger system has the advantages of powerful functions, flexible combination, good expandability, high reliability, short trigger time delay, all-weather capability and the like.
In the existing wireless trigger control system, a singlechip, a DSP and the like are often adopted as control units of a remote control system, but the wireless trigger control system is often weaker than an FPGA in terms of accurate timing control and parallel processing capacity due to the working characteristics of the wireless trigger control system. With the development of programmable logic devices such as FPGA, a good realization platform is provided for the reliable transmission of wireless data.
Disclosure of Invention
The invention aims to provide a wireless triggering system and method based on an FPGA.
The purpose of the invention is realized as follows:
a wireless trigger system based on FPGA mainly comprises an FPGA baseband processing module, a D/A digital-to-analog conversion module, a radio frequency transceiver module, an A/D analog-to-digital conversion module and a power supply module; the FPGA baseband processing module generates a digital baseband signal and transmits the digital baseband signal to the D/A digital-to-analog conversion module, the D/A digital-to-analog conversion module converts the digital baseband signal into a baseband analog signal and transmits the baseband analog signal to the radio frequency transceiving module, and the radio frequency transceiving module up-converts the baseband analog signal into a radio frequency signal and transmits the radio frequency signal through an antenna; the transmitting signal is transmitted to the radio frequency transceiving module through the channel and received by the radio frequency transceiving module, the radio frequency transceiving module down-converts the received radio frequency signal into a baseband analog signal and transmits the baseband analog signal to the A/D analog-to-digital conversion module, and the A/D analog-to-digital conversion module converts the baseband analog signal into a digital baseband signal and transmits the digital baseband signal to the FPGA baseband processing module; the FPGA baseband processing module processes the received digital baseband signal; the power supply module is respectively connected with the FPGA baseband processing module, the D/A digital-to-analog conversion module, the A/D analog-to-digital conversion module and the radio frequency transceiving module to supply power to the FPGA baseband processing module, the D/A digital-to-analog conversion module, the A/D analog-to-digital conversion module and the radio frequency transceiving module.
The invention also comprises an ultra-low clock module which provides clocks for the D/A digital-to-analog conversion module and the A/D analog-to-digital conversion module.
The invention also comprises a high-speed ADC driver and a high-speed DAC buffer, wherein the D/A digital-to-analog conversion module is connected with the radio frequency transceiver module through the high-speed DAC buffer, and the radio frequency transceiver module is connected with the A/D analog-to-digital conversion module through the high-speed ADC driver. A wireless triggering method based on FPGA comprises the following steps:
a sending end:
(1) determining the number m of sub-channels modulated by OFDM and the number n of bits modulated by each channel, and setting the width of a code element as T;
(2) generating m subcarrier frequencies f ═ f based on the number m of subchannels of the OFDM modulation1,f2,…,fm]Ith subcarrier frequency
Figure BDA0001923145650000021
c is a constant integer for adjusting the periodicity of the carrier in each code element;
(3) selecting code words with good correlation characteristics as trigger signals, converting the trigger signals into m paths of serial-parallel conversion, mapping m paths of binary bit information and m generated subcarrier frequencies in a one-to-one mode, and obtaining the waveform of the ith path of modulation signals as s through BPSK modulationi(t)＝xi×cos(2πfit) where xiMapping a digit 0 to be +1 and a digit 1 to be-1 for the symbol information mapped by the ith binary bit stream; t is an element of [0, nT ∈]；
(4) The m paths of modulation signal waveforms are superposed into a path of serial signal
Figure BDA0001923145650000022
(5) The digital serial signal is converted into an analog signal after passing through a D/A digital-to-analog conversion module, and is up-converted to 2.4GHz by a radio frequency transceiving module and is transmitted out through an antenna;
receiving end:
(6) the received radio frequency signal is converted into a baseband analog signal through down conversion, and is converted into a baseband digital signal through an A/D (analog-to-digital) conversion module, and the sampling rate is set to be fs；
(7) In one clock period of the FPGA, respectively solving the cross correlation of the received digital signals and the m paths of modulation signals generated in the step (4), and superposing and summing the m paths of cross correlation results;
receive sequences r (k) andith modulation sequence si(k) Is expressed as
Figure BDA0001923145650000023
The sum formula of the m-path cross-correlation results is
Figure BDA0001923145650000024
(8) Comparing the summation result with a set threshold, and if the summation result is greater than the set threshold, finishing triggering; otherwise, repeating the step (7) in the next clock cycle until the triggering is completed.
The trigger signal is a ZCZ code or other sequences with good correlation characteristics.
The antennas transmit single antenna reception for OFDM-based single antennas or transmit multiple antenna reception for MIMO-based multiple antennas.
The invention has the beneficial effects that:
1. a wireless triggering mode is adopted, so that the environmental adaptability is strong, and the application range is wide;
2. selecting a code group with good correlation characteristics as a trigger signal, wherein the autocorrelation result of the same code group has a sharp peak value, and the cross-correlation result of different code groups is zero, so that the code group is not easily interfered by noise and has high detection success rate;
3. and a mechanism of receiving and detecting at the receiving end is adopted, and the data receiving and the detecting are completed simultaneously, so that the time delay is shortened, and the triggering can be completed within a few microseconds.
Drawings
FIG. 1 is a diagram of a hardware system architecture of the present invention;
FIG. 2 is a block diagram of the method system of the present invention;
FIG. 3 is a simulation diagram of the correlation result of BPSK-OFDM signals according to the present invention;
FIG. 4 is a block diagram of fast search acquisition for matched filter based correlation detection;
FIG. 5 is a simulation diagram of ZCZ code correlation characteristics, wherein (a) is an autocorrelation curve of a ZCZ code, and (b) is a cross-correlation curve of the ZCZ code.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Detailed description of the preferred embodiment 1
The hardware structure of the wireless trigger system based on OFDM is shown in figure 1, and mainly comprises an FPGA main control module, an ultra-low clock jitter module, a high-speed ADC and DAC mixed signal front end, a high-speed ADC driver, a high-speed DAC buffer, and a radio frequency signal transceiving and power supply module. The front end of the high-speed ADC and DAC mixed signal comprises a D/A digital-to-analog conversion module and an A/D analog-to-digital conversion module, the ultra-low clock jitter module provides a clock for the front end of the high-speed ADC and DAC mixed signal, and the power supply module supplies power for all other modules.
Assuming that 16bit codes are sent, the codes are converted into 4bit by 4 parallel codes in a serial-parallel mode, after BPSK mapping, four parallel codes are used for modulating orthogonal carriers of 4M, 8M, 12M and 16M respectively, four parallel modulation signals are added to obtain one path of serial data and sent to a channel, Gaussian white noise is added in channel simulation, a receiving end carries out cross-correlation calculation on the received serial data and local four modulation signals, then cross-correlation results are summed to obtain a total correlation result, the process is shown in figure 2, the correlation result is obtained through simulation and is shown in figure 3, the correlation result has an obvious peak value, therefore, a reasonable threshold value is set, and whether triggering is finished or not is judged through comparison with the correlation result.
The correlation detection is performed by matching the peak values with a matched filter, and the search block diagram is shown in fig. 4. In the first clock cycle, a digital input signal is firstly input to the leftmost end of N registers M1, a local sequence is stored in a register M2, values of a memory cell of the register M1 and a memory cell of the register M2 are multiplied in parallel, a multiplication result is input into a multi-input accumulator to be summed, the summed result is transmitted into a decision device to be compared with a set threshold value, if the summed result exceeds the threshold value, a received sequence is considered to be related to the local sequence, a host machine is matched with a slave machine, and triggering is completed; otherwise, the value of the memory cell of the register M1 is shifted to the right by one memory cell in the second clock cycle, then the input signal is stored in the memory cell at the leftmost end of the register M1, then the memory cells corresponding to M1 and M2 are multiplied and accumulated, after the judgment process, if the accumulated result still does not exceed the threshold value, the operation process of the second cycle is repeated in the next clock cycle until the accumulated result exceeds the threshold value. When the signal just completely enters the register M1, whether triggering is detected by integral detection can be judged.
The OFDM technology modulates signals to multiple paths of orthogonal carriers, the orthogonality of the carriers ensures that mutual interference among subcarriers does not exist, the utilization rate of frequency spectrum can be improved and the system capacity can be increased through the modulation of the multiple paths of carriers, and compared with single carrier modulation, the triggering time can be shortened under the condition of transmitting the same number of symbols.
Specific example 2
The above specific embodiment 1 is a single antenna transceiving system based on OFDM, and on this basis, a multi-antenna transmitting and multi-antenna receiving system is introduced, that is, on the basis of OFDM technology, MIMO technology is introduced to obtain a wireless triggering system based on MIMO-OFDM.
Taking two transmitting antennas and two receiving antennas as an example, if two antennas transmit at the same frequency, signals transmitted by the two antennas are susceptible to mutual interference, and in order to overcome the interference, orthogonality of codes transmitted on the two antennas must be ensured, that is, a cross-correlation function between a code transmitted on one antenna and a code transmitted on the other antenna is zero. In order to sufficiently ensure such orthogonality, the present invention employs a ZCZ sequence excellent in correlation characteristics.
To better illustrate the correlation properties of ZCZ codes, a complete set of ZCZ codes can be expressed as:
Figure BDA0001923145650000041
{A0,A1and { B }0,B1The auto-and cross-correlation computation results of can be expressed as:
Figure BDA0001923145650000042
the ZCZ code used for radio trigger detection can be expressed as:
Figure BDA0001923145650000043
with ZCZ transmission on one antenna0Sequence, transmitting ZCZ on another antenna1And (4) sequencing.
In order to more intuitively display the orthogonality of the ZCZ codes, a simulation graph of the correlation results is shown in fig. 5, in which (a) is an autocorrelation curve of the ZCZ codes and (b) is a cross-correlation curve of the ZCZ codes.
Due to the space-time gain of the MIMO technology, the MIMO technology is introduced on the basis of the OFDM technology, and the system capacity can be doubled, so that the triggering time can be greatly shortened.

Claims (3)

1. A wireless triggering method based on FPGA is characterized by comprising the following steps:
a sending end:
(1) determining the number m of sub-channels modulated by OFDM and the number n of bits modulated by each channel, and setting the width of a code element as T;
(2) generating m subcarrier frequencies f ═ f based on the number m of subchannels of the OFDM modulation1,f2,…,fm]Ith subcarrier frequency
Figure FDA0003004766030000011
c is a constant integer for adjusting the periodicity of the carrier in each code element;
(3) selecting code words with good correlation characteristics as trigger signals, converting the trigger signals into m paths of serial-parallel conversion, mapping m paths of binary bit information and m generated subcarrier frequencies in a one-to-one mode, and obtaining the waveform of the ith path of modulation signals as s through BPSK modulationi(t)＝xi×cos(2πfit) where xiMapping a digit 0 to be +1 and a digit 1 to be-1 for the symbol information mapped by the ith binary bit stream; t is an element of [0, nT ∈]；
(4) The m paths of modulation signal waveforms are superposed into a path of serial signal
Figure FDA0003004766030000012
(5) The digital serial signal is converted into an analog signal after passing through a D/A digital-to-analog conversion module, and is up-converted to 2.4GHz by a radio frequency transceiving module and is transmitted out through an antenna;
receiving end:
(6) the received radio frequency signal is converted into a baseband analog signal through down conversion, and is converted into a baseband digital signal through an A/D (analog-to-digital) conversion module, and the sampling rate is set to be fs；
(7) In one clock period of the FPGA, respectively solving the cross correlation of the received digital signals and the m paths of modulation signals generated in the step (4), and superposing and summing the m paths of cross correlation results;
receiving sequence r (k) and ith modulation sequence si(k) Is expressed as
Figure FDA0003004766030000013
The sum formula of the m-path cross-correlation results is
Figure FDA0003004766030000014
(8) In the first clock cycle, the digital input signal is firstly input to the leftmost end of N registers M1, a local sequence is stored in a register M2, simultaneously, the register M1 is multiplied by the value of a storage unit of the register M2 in parallel, the multiplied result is input into a multi-input accumulator to be summed, the summed result is compared with a set threshold value, and if the summed result is larger than the set threshold value, the triggering is finished; otherwise, the value of the memory cell of the register M1 is shifted to the right by one memory cell in the second clock cycle, then the input signal is stored in the memory cell at the leftmost end of the register M1, then the memory cells corresponding to M1 and M2 are multiplied and accumulated, after the judgment process, if the accumulated result still does not exceed the threshold value, the operation process of the second cycle is repeated in the next clock cycle until the accumulated result exceeds the threshold value.
2. The wireless triggering method based on the FPGA according to claim 1, characterized in that: the trigger signal is a ZCZ code or other sequences with good correlation characteristics.
3. The wireless trigger method based on FPGA according to claim 1 or 2, characterized in that: the antennas transmit single antenna reception for OFDM-based single antennas or transmit multiple antenna reception for MIMO-based multiple antennas.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104378129A (en) * 2014-11-26 2015-02-25 成都中远信电子科技有限公司 Land-to-air wideband communication system for unmanned aerial vehicle
CN104980382A (en) * 2015-06-29 2015-10-14 上海华为技术有限公司 Data processing method and apparatus of multiple cell-shared radio remote units (RRU)
CN107395219A (en) * 2017-07-10 2017-11-24 西安电子科技大学 A kind of high-speed radiocommunication system and method based on FPGA

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7548787B2 (en) * 2005-08-03 2009-06-16 Kamilo Feher Medical diagnostic and communication system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104378129A (en) * 2014-11-26 2015-02-25 成都中远信电子科技有限公司 Land-to-air wideband communication system for unmanned aerial vehicle
CN104980382A (en) * 2015-06-29 2015-10-14 上海华为技术有限公司 Data processing method and apparatus of multiple cell-shared radio remote units (RRU)
CN107395219A (en) * 2017-07-10 2017-11-24 西安电子科技大学 A kind of high-speed radiocommunication system and method based on FPGA

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