CN109461734A - The manufacturing method of semiconductor devices and the manufacturing method of memory - Google Patents
The manufacturing method of semiconductor devices and the manufacturing method of memory Download PDFInfo
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- CN109461734A CN109461734A CN201811223084.XA CN201811223084A CN109461734A CN 109461734 A CN109461734 A CN 109461734A CN 201811223084 A CN201811223084 A CN 201811223084A CN 109461734 A CN109461734 A CN 109461734A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000010410 layer Substances 0.000 claims abstract description 158
- 239000011229 interlayer Substances 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims description 56
- 238000005530 etching Methods 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 238000007667 floating Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 1
- 238000011049 filling Methods 0.000 abstract description 21
- 150000002500 ions Chemical class 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 239000012528 membrane Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- -1 germanium ion Chemical class 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- 230000037430 deletion Effects 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical group [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of manufacturing method of semiconductor devices and the manufacturing methods of memory, the manufacturing method of the semiconductor devices includes the substrate of the device region provided including being formed with first grid structure and the external zones for being formed with second grid structure, forms the first side wall in the first and second gate structure sidewalls；The first source-drain area is formed in the substrate of first grid structure two sides；Covering first grid structure and second grid structure and the first interlayer dielectric layer for filling the gap between two adjacent first grid structures are formed on device region and external zones, form the second side wall in the side wall of second grid structure；The second source-drain area is formed in the substrate of second grid structure two sides；The second interlayer dielectric layer of the first interlayer dielectric layer of covering, first grid structure and second grid structure is formed on device region and external zones.The present invention reduces the filling cavities of interlayer dielectric layer, improve the ability in the gap between interlayer dielectric layer filling gate structure.
Description
Technical field
The present invention relates to ic manufacturing technology fields, a kind of manufacturing method more particularly to semiconductor devices and
The manufacturing method of memory.
Background technique
With the continuous diminution of the device size of memory, the size between grid and grid is smaller and smaller, inter-level dielectric
The filling of layer becomes a very important problem.The substrate that (MTP) memory can repeatedly be programmed is typically divided into edge
(Periphery) area and the area device (cell).It is formed with stack grid structure on the device region (also referred to as cellular region),
This stack grid structure generally comprise tunnel oxide (tunnel OX), the floating grid for storing charge, silica/
Nitrogenize dielectric layer and for controlling the control gate of data access between silicon/oxidative silicon (Oxide-Nitride-Oxide, ONO) grid.
In the marginal zone, (also referred to as external zones) is formed with selection grid, and the selection grid is located at opening for device region for logic control
Close the unlatching and closure of device (such as metal-oxide-semiconductor).
Gate stack and the side wall of selection grid are formed with side wall, for respectively to device region and marginal zone carry out source-drain electrode from
Sub- injection technology step, and then source-drain electrode is formed in the substrate for being located at device region and external zones respectively, later simultaneously to described
Substrate carries out inter-level dielectric (Interlayer dielectric, ILD) layer fill process, after interlayer dielectric layer is formed, executes
The technique of conductive contact plug is formed in interlayer dielectric layer so that source-drain electrode is drawn.
The study found that when carrying out interlayer dielectric layer filling to substrate by above-mentioned processing step, it is adjacent due to device region
Two stack grid structures between gap it is smaller, and each heap is also needed to form before interlayer dielectric layer
The side wall of stacked gate structure, this meeting is so that the gap between adjacent two stack grid structures is smaller, lesser heap
Gap between stacked gate structure is easy to be situated between in the interlayer for being located at above-mentioned gap location when executing interlayer dielectric layer fill process
Cavity is formed in matter layer, also needs to form conductive contact plug due to subsequent, the formation of conductive contact plug includes being initially formed to pass through
Wear the contact hole of interlayer dielectric layer, the backward contact hole in fill metal, and cavity presence will cause contact hole and connect
Connection between contact hole, to influence the performance of device.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing method of semiconductor devices and the manufacturing methods of memory, to solve
Certainly there is the problem of cavity blemish in the interlayer dielectric layer in the gap between adjacent two gate stack on device region.
To solve the above-mentioned problems, the invention is realized by the following technical scheme:
A kind of manufacturing method of semiconductor devices, comprising: provide substrate, the substrate includes device region and external zones, institute
It states and is formed with multiple first grid structures on device region, at least one second grid structure is formed on the external zones；Institute
It states first grid structure and second grid structure side wall forms the first side wall；Ion implanting is carried out to the device region, in institute
It states and forms the first source-drain area in the substrate of first grid structure two sides；The first interlayer Jie is formed on the device region and external zones
Matter layer, first interlayer dielectric layer cover the first grid structure and second grid structure and fill adjacent two first
Gap between gate structure；The second side wall is formed in the side wall of the second grid structure；Ion is carried out to the external zones
Injection, to form the second source-drain area in the substrate of second grid structure two sides；And in the device region and external zones
The second interlayer dielectric layer of upper formation, second interlayer dielectric layer cover first interlayer dielectric layer, first grid structure and
Second grid structure.
Optionally, first interlayer dielectric layer is formed using furnace process and uses high-density plasma chemical gas phase
Depositing operation forms the second interlayer dielectric layer.
Optionally, first interlayer dielectric layer is identical as the material of the second interlayer dielectric layer.
Optionally, the material of first interlayer dielectric layer and the second interlayer dielectric layer be titanium dioxide optionally, formed
The step of first side wall includes: to be sequentially depositing etching barrier layer and the first side wall medium layer over the substrate；And it is logical
Self-aligned etching technique is crossed, it will be on the first grid structural top, second grid structural top and the etching barrier layer
The first side wall medium layer remove, be respectively formed described first with the side wall in the first grid structure and second grid structure
Side wall.
Optionally, the material of the etching barrier layer is silica, and the material of first side wall medium layer is nitridation
Silicon.
Optionally, the step of forming second side wall includes: by Self-aligned etching technique, by the first grid knot
On structure top, second grid structural top, the substrate surface area between adjacent first grid structure and second grid
And the first interlayer dielectric layer in external zones substrate surface area and etching barrier layer are removed, and by first side wall top
First interlayer dielectric layer in portion is removed, and forms second side wall with the side wall in the first side wall of the second grid structure.
Optionally, it is formed after the second interlayer dielectric layer, further includes: be situated between in first interlayer dielectric layer and the second interlayer
Conductive contact plug is formed in matter layer, the conductive contact plug is electrically connected with first source-drain area and the second source-drain area.
On the other hand, a kind of manufacturing method of memory, including method, semi-conductor device manufacturing method as described above.
Optionally, the first grid structure includes the tunnel oxide, floating grid, grid being sequentially stacked on device region
Between dielectric layer and control gate；The second grid structure includes the gate oxide and polysilicon layer being sequentially stacked on external zones.
The present invention has following technical effect that
The present invention is initially formed the first side wall of device region grid curb wall and external zones grid, then to device region carry out from
Son injection forms the first source-drain area, first time interlayer dielectric layer fill process is carried out using furnace process later, so that device region
Gate structure between gap filled as far as possible, later formed external zones grid the second side wall, the first of external zones grid
Side wall and the second side wall have collectively constituted external zones grid curb wall, carry out ion implanting to external zones and form the second source-drain area, then
Second of interlayer dielectric layer fill process is carried out, covering periphery is ultimately formed by the fill process of above-mentioned interlayer dielectric layer twice
The interlayer dielectric layer in area and device region grid.The present invention due to formed external zones grid the second side wall before just to device region
Gap between grid has carried out primary filling, can improve under the premise of not changing the fill process condition of interlayer dielectric layer
Interlayer dielectric layer fills the ability in the gap between gate structure, reduces the filling cavity of interlayer dielectric layer, and then improve device
Performance.
Detailed description of the invention
Fig. 1 is the flow diagram of the manufacturing method of semiconductor devices provided in an embodiment of the present invention；
Fig. 2 a~Fig. 2 f is that the device profile structure in the manufacturing process of semiconductor devices provided in an embodiment of the present invention is shown
It is intended to.
Specific embodiment
A kind of manufacturing method of semiconductor devices of the invention is carried out below in conjunction with flow chart and schematic diagram more detailed
Description, which show a preferably embodiments of the invention, it should be appreciated that those skilled in the art can modify and be described herein
The present invention and still realize advantageous effects of the invention.Therefore, following description should be understood as those skilled in the art
Member's is widely known, and is not intended as limitation of the present invention.
For clarity, not describing whole features of a practical embodiment.In the following description, it is not described in detail well known function
Energy and structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that in any one embodiment of reality
Exploitation in, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related quotient
The limitation of industry changes into another embodiment by an embodiment.Additionally, it should think that this development may be multiple
It is miscellaneous and time-consuming, but to those skilled in the art it is only routine work.
Inventor needs same the study found that after external zones and device region form grid curb wall and carry out source-drain electrode injection
When interlayer dielectric layer filling carried out to external zones and device region, and due to adjacent two stack grid structure of device region it
Between gap it is smaller, easily cause in the gap between the two neighboring grid of device region occur cavity, and then influence device
Energy.Based on above-mentioned discovery, the present invention is by the technique of stepped depositions interlayer dielectric layer to solve the above problems, that is, is initially formed device
Then first side wall of part area grid curb wall and external zones grid carries out ion implanting to device region and forms the first source-drain area, it
The filling of first time interlayer dielectric layer is carried out using furnace process afterwards, forms the second side wall of external zones grid, external zones grid later
The first side wall and the second side wall of pole have collectively constituted external zones grid curb wall, due in the second side wall for forming external zones grid
Primary filling just has been carried out to the gap between device region grid before, has been realized in the fill process item for not changing interlayer dielectric layer
Under the premise of part, the ability in the gap between interlayer dielectric layer filling gate structure can be improved, the filling of interlayer dielectric layer is reduced
The purpose of device performance to prevent cavity from leading to the connection between contact hole, and is improved in cavity.
To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing
Further instruction.It should be noted that attached drawing is all made of very simplified form and using non-accurate ratio, only to side
Just, the purpose of one embodiment of the invention is lucidly aided in illustrating.
As shown in Figure 1, being comprised the following processes the present embodiment provides a kind of manufacturing method of semiconductor devices:
S1: substrate is provided, the substrate includes device region and external zones, and multiple first grids are formed on the device region
Structure is formed with second grid structure on the external zones；
S2: the first side wall is formed in the side wall of the first grid structure and second grid structure；
S3: ion implanting is carried out to the device region, to form the first source and drain in the substrate of first grid structure two sides
Area；
S4: the first interlayer dielectric layer is formed on the device region and external zones, first interlayer dielectric layer will be adjacent
Two first grid structures between gap filling, and cover the first grid structure and second grid structure；
S5: the second side wall is formed in the side wall of the second grid structure；
S6: ion implanting is carried out to the external zones, to form the second source and drain in the substrate of second grid structure two sides
Area；
S7: the second interlayer dielectric layer, the second interlayer dielectric layer covering are formed on the device region and external zones
The first grid structure and second grid structure.
In the present embodiment, substep carries out the filling of the first interlayer dielectric layer and the second interlayer dielectric layer, thus can not change
Under the premise of becoming existing interlayer dielectric layer fill process parameter, realize between improving between interlayer dielectric layer filling gate structure
The purpose of the ability of gap.
Referring specifically to Fig. 2 a~Fig. 2 f, the manufacturing method that semiconductor devices in the embodiment of the present invention is shown respectively is walked
Rapid corresponding device profile structural schematic diagram.
As shown in Figure 2 a, a substrate 100 is provided.The material of the substrate 100 can for silicon, germanium, SiGe or silicon carbide etc.,
It is also possible to cover silicon (SOI) perhaps germanium on insulator (geoi) (GOI) or can also be other materials, such as arsenic on insulator
Change III, V compounds of group such as gallium.The substrate 100 may include the design requirement depending on memory or other semiconductor devices
Various doped regions.It can also include isolation structure (such as shallow trench isolation, STI) in the substrate 100 so that each area is isolated
Domain and/or the semiconductor devices formed over the substrate.
In the present embodiment, substrate 100 is silicon substrate.The substrate 100 includes device region (also referred to as cellular region) 101 He
External zones (also referred to as marginal zone) 102.Multiple first grid structures 200, the external zones are formed on the device region 101
One or more second grid structures 201 are formed on 102.
Wherein, the first grid structure 200 is stack grid structure, forms the process example of the first grid structure
In this way the following steps are included: firstly, being formed with gate stack (being not shown in Fig. 2 a), the grid on the device region 101
Lamination includes e.g. the tunnel oxide film being sequentially stacked on the device region 101 from the bottom to top, floating grid film, grid
Between dielectric film and control gate film, dielectric film and control gate film can between tunnel oxide film, floating grid film, grid
It is modified additions and deletions according to actual device requirement and manufacture craft；Then, using well known to a person skilled in the art exposures
The techniques such as light and development define the position of first grid structure 200, and etch the gate stack on the device region 101, with
First grid structure 200 is formed on the device region 101, the first grid structure 200 includes being sequentially stacked on above-mentioned device
Tunnel oxide 2001 (being obtained by etching tunnel oxide film), floating grid 2002 in part area 101 is (floating by etching
Grid film obtains), dielectric layer 2003 (being obtained by etching grid lamination) and control gate 2004 (pass through etching control gate between grid
Film obtains).
The tunnel oxide film can use silica single layer structure, can also use oxide-nitride-oxide
(ONO) structure.The forming method of the tunnel oxide film includes low-pressure chemical vapor deposition (LPCVD), high-density plasma
The suitable technique such as chemical vapor deposition (HDPCVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxide.This reality
It applies in example, the tunnel oxide film uses silica single layer structure, and thermal oxidation method can be used and formed, thickness is for example several
Ten Izods are right.
Dielectric film can use oxide-nitride-oxide (ONO) structure between the grid.Dielectric is thin between the grid
The forming method of film include low-pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), etc. from
Daughter enhances the suitable technique such as chemical vapor deposition (PECVD), thermal oxide.In the present embodiment, low pressure chemical gas can be first used
Phase depositing operation forms one layer of silicon oxide layer on floating grid film, is then being aoxidized using low-pressure chemical vapor deposition process
One layer of silicon nitride layer is formed on silicon layer, and another layer of oxygen is then formed on silicon nitride layer using low-pressure chemical vapor deposition process again
SiClx layer, the overall thickness of dielectric film is for example between tens angstroms to several hundred angstroms between the grid.
It can also be referred to as selection grid in the second grid structure 201 that the external zones 102 is formed, the selection grid is used for
The unlatching and closure of the switching device (such as metal-oxide-semiconductor) in logic control device area.Form the process of the second grid structure 201
E.g. include the following steps: firstly, forming a gate dielectric membrane (being not shown in Fig. 2 a) on the external zones 102, later
Polysilicon membrane (being not shown in Fig. 2 a) is formed on the gate dielectric membrane, the material of the gate dielectric membrane is titanium dioxide
Silicon；Then, lithography and etching technique is carried out to the polysilicon membrane and gate dielectric membrane, to be formed above external zones 102
It is (thin by etches polycrystalline silicon including the gate dielectric layer (being obtained by etching gate dielectric membrane) 2011 stacked gradually and polysilicon layer
Film obtains) 2012 second grid structure 201.The polysilicon layer can be polysilicon (the undoped poly- to undope
Silicon), e.g. formed using chemical vapor deposition process.The polysilicon layer is also possible to the polysilicon being lightly doped
(lightly-doped poly-silicon) is e.g. formed using (In-situ) doping process in situ, alternatively, being initially formed
The polysilicon (undoped poly-silicon) to undope, is then additionally doped technique, thus formed be lightly doped it is more
Crystal silicon (lightly-doped poly-silicon).The polysilicon layer can also be the polysilicon that undopes and be lightly doped
(the undoped poly-silicon+lightly-doped poly- of composite construction made of polysilicon stacks from bottom to top
silicon).When polysilicon layer is the polysilicon being lightly doped, it is preferable that Doped ions in the polysilicon being lightly doped with
The source region being subsequently formed is identical with the conduction type of the Doped ions in drain region.In the present embodiment, the first grid structure
200 top surface is higher than the top surface of second grid structure 201.
Then, as shown in Figure 2 b, the first side is formed in the first grid structure 200 and second grid structure 201
Wall 301.In the present embodiment, above-mentioned first side wall 301 can be used to prevent larger dose source and drain injection get too close to channel with
It is passed through to the source and drain that may occur.
Specifically, etching barrier layer 300 can be formed on substrate 100 and the first side wall medium layer (is not shown in Fig. 2 a
Out), and to first side wall medium layer it performs etching, to form the first side wall 301.Wherein, the covering of etching barrier layer 300 the
One gate structure 200, second grid structure 201 and substrate 100, the first side wall 301 are then made only in 200 He of first grid structure
The side wall of second grid structure 201.The material of first side wall medium layer can be silica, silicon oxynitride or silicon nitride
One of, or be any combination of silica, silicon oxynitride or silicon nitride, for example can be ON (silica-nitridation
Silicon) lamination or ONO (oxide-nitride-oxide) lamination.In the present embodiment, the material of the etching barrier layer 300 is
Silica, the material of the first side wall medium layer are silicon nitride.Thermal oxide (wet oxidation or dry oxidation) technique, original can be used
The techniques such as position steam generation technique (ISSG), chemical vapor deposition (CVD) technique or atom layer deposition process are in the substrate 100
Global surface on sequentially form etching barrier layer 300 and the first side wall medium layer.Can by be not necessarily to light shield Self-aligned etching,
First side wall medium layer at 100 top of first grid structure 200 and 201 top of second grid structure and substrate is etched away,
To form the first side wall 301 in the side wall of the side wall of the first grid structure 200 and second grid 201.
Wherein, etching barrier layer 300, which is used as, etches away positioned at 201 top of first grid structure 200 and second grid structure
And the top of substrate 100 the first side wall medium layer when stop-layer.The described any two adjacent but first grid knots that do not connect
Structure 200 (side wall of the first grid structure 200 has been covered with etching barrier layer 300 and the first side wall 301 at this time) can be formed
Gap a between grid, gap a is subsequent between the grid need to fill interlevel dielectric material.Positioned at device region 101 and external zones 102 it
Between or positioned at external zones 102 two neighboring second grid structure 201 (if external zones 102 forms multiple second grid knots
Structure 201) between interval also fill interlayer dielectric layer material, but since above-mentioned interval is larger, comparatively fill inter-level dielectric
It is not easy to the problem of cavity blemish occur when layer material.It should be understood that the term " gap " occurred herein indicates same layer in device
Interval region between material figure, and can be equal with term " linear slit " or " gap " meaning.
Then, as shown in Figure 2 c, ion implanting is carried out to the device region 101, at 200 liang of each first grid structure
The first source-drain area 400 is formed in the substrate of side.
Specifically, the first source-drain area 400 can be formed as follows: firstly, on 100 surface of substrate (referred to herein as
On the surface of etching barrier layer 300 and the first side wall 301) the first mask layer (e.g. coating photoresist) is formed, and utilize light
Carving technology defines the first source and drain areas to its graphical (only exposing the first source and drain areas) with this；Then, ion implanting is utilized
N-type or p-type Doped ions correspondence are injected into above-mentioned first source and drain region by technology, to form the first source-drain area 400；Most
Afterwards, the photoresist on 100 surface of substrate is removed.In the present embodiment, injection phosphorus and arsenic ion in the first source and drain of Xiang Suoshu region
First source-drain area 400 is formed, phosphorus is being injected and when arsenic ion since the substrate of device region can be destroyed, positioned at the lining of device region
Etching barrier layer 300 on bottom surface is when to phosphorus and arsenic ion is injected in the first source and drain region, for protecting substrate
It will not be destroyed.
As shown in Figure 2 d, it is formed with the first interlayer dielectric layer 302 on the device region 101 and external zones 102, described
One interlayer dielectric layer 302 fills gap a between the grid formed by two adjacent first grid structures 201 as far as possible, and covers
Lid etching barrier layer 300 and the second side wall 301.The maximum gauge of first interlayer dielectric layer 302 is, for example, 1000 angstroms~
10000 angstroms.In the present embodiment, the material of first interlayer dielectric layer 302 is silica, and furnace can be selected in fill process
Plumber's skill, i.e., by being passed through oxygen and silane (SiH4) into boiler tube, by thermally decomposing the silane in the device region 101
It is the first interlayer dielectric layer 302 of silica with formation material on external zones 102；This method has relatively brilliant filling perforation energy
Many advantages, such as power, growth temperature be low, reliable electrology characteristic.
As shown in Figure 2 e, the second side wall 302 ' is formed in the side wall of the second grid structure 201.Specifically, can pass through
Following steps form the second side wall 302 ': the Self-aligned etching by being not necessarily to light shield, and removal is located at first grid structure 200 and pushes up
Portion, 201 top of second grid structure, the substrate table between adjacent first grid structure 200 and second grid structure 201
Etching barrier layer 300 on the region of face and in the substrate surface area of external zones 102 and it is located at the etching barrier layer 300
On the first interlayer dielectric layer 302, and first interlayer dielectric layer 302 at removal the first side wall 301 top, in second grid
Second side wall 302 ' is formed on the side wall of first side wall 301 of structure 201.
With continued reference to Fig. 2 e, ion implanting is carried out to the external zones 102, in the lining of 201 two sides of second grid structure
The second source-drain area 401 is formed in bottom.Specifically, the second source-drain area 401 can be formed as follows: firstly, in 100 table of substrate
(the e.g. coating photoetching of the second mask layer is formed on face (referred to herein as on the global surface of device region 101 and external zones 102)
Glue), and the second source and drain areas is defined with this to its graphical (only exposing the second source and drain areas) using photoetching process；Then,
N-type or p-type Doped ions correspondence are injected into above-mentioned second source and drain region using ion implantation technique, to form the second source
Drain region 401；Finally, the photoresist on removal 100 surface of substrate.It in the present embodiment, is infused into the second source and drain region
Enter germanium ion and arsenic ion forms second source-drain area 401, injects germanium ion and when arsenic ion due to will not be to external zones
The substrate surface etching barrier layer 300 that has an impact, and be located on the substrate surface of external zones can to the germanium ion of injection and
Arsenic ion generates barrier effect, therefore injects in the second source and drain region germanium ion and when arsenic ion, need to remove position
In the etching barrier layer 300 on external zones substrate surface.
Then, as shown in figure 2f, the second interlayer dielectric layer 303 is formed on the device region 101 and external zones 102,
Second interlayer dielectric layer 303 covers first interlayer dielectric layer 302, the first grid structure 200 and second grid
Structure 201.Second interlayer dielectric layer 303 has flat surface.First interlayer dielectric layer 302 and the second interlayer are situated between
The overall thickness of matter layer 303 is, for example, 3000 angstroms~20000 angstroms.Second interlayer dielectric layer 303 and the first interlayer dielectric layer 302
Material is identical, such as: the two is silica.
In the present embodiment, the material of second interlayer dielectric layer 303 is silica.Height can be selected in its fill process
Density plasma chemical vapor deposition (HDP CVD) method, this method have relatively brilliant porefilling capability, stable deposit
Many advantages, such as quality, reliable electrology characteristic, the gap filling work being widely used in 0.25 micron of electricity device below
Skill.
With continued reference to Fig. 2 f, based on the above embodiment, the invention also discloses a kind of manufacturing methods of memory, using such as
The manufacturing method of semiconductor devices described above, over the substrate formed interlayer dielectric layer (including first interlayer be situated between
Matter layer 302 and the second interlayer dielectric layer 303), then, conductive contact plug 500 is formed in the interlayer dielectric layer.
As a unrestricted example, the conductive contact plug 500 is formed as follows: firstly, photoetching
Define the forming region of the conductive contact plug 500；Then, using dry etch process to the conductive contact plug
The interlayer dielectric layer of 500 forming region performs etching, to form contact hole.Filling metal is formed in the contact hole
For connecting the conductive contact plug 500 of back segment metal layer.
In conclusion the present invention optimizes process sequence, will carry out interlayer to substrate by considering from the angle of process integration
The process of media filler is completed by substep, that is, is initially formed the first side wall of device region grid curb wall and external zones grid, then
Ion implanting is carried out to device region and forms the first source-drain area, first time interlayer dielectric layer fill process is carried out later, so that device
Gap between the gate structure in area is filled as far as possible, re-forms the second side wall of external zones grid later, external zones grid
First side wall and the second side wall have collectively constituted external zones grid curb wall, carry out ion implanting to external zones and form the second source and drain
Area, then second of interlayer dielectric layer fill process is carried out, it is ultimately formed and is covered by the fill process of above-mentioned interlayer dielectric layer twice
The interlayer dielectric layer of lid external zones and device region grid.The present invention is due to just right before the second side wall for forming external zones grid
Gap between device region grid has carried out primary filling, realizes the premise in the fill process condition for not changing interlayer dielectric layer
Under, the ability in the gap between interlayer dielectric layer filling gate structure can be improved, the filling cavity of interlayer dielectric layer is reduced, can prevent
Only cavity leads to the connection between contact hole, and improves the purpose of device performance.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a kind of manufacturing method of semiconductor devices characterized by comprising
Substrate is provided, the substrate includes device region and external zones, and multiple first grid structures, institute are formed on the device region
It states and is formed at least one second grid structure on external zones；
The first side wall is formed in the first grid structure and second grid structure side wall；
Ion implanting is carried out to the device region, to form the first source-drain area in the substrate of first grid structure two sides；
The first interlayer dielectric layer is formed on the device region and external zones, first interlayer dielectric layer covers the first grid
Pole structure and second grid structure simultaneously fill the gap between two adjacent first grid structures；
The second side wall is formed in the side wall of the second grid structure；
Ion implanting is carried out to the external zones, to form the second source-drain area in the substrate of second grid structure two sides；
And
The second interlayer dielectric layer is formed on the device region and external zones, second interlayer dielectric layer covers the first layer
Between dielectric layer, first grid structure and second grid structure.
2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that form described using furnace process
One interlayer dielectric layer and use high density plasma CVD technique form the second interlayer dielectric layer.
3. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that first interlayer dielectric layer and
The material of two interlayer dielectric layers is identical.
4. the manufacturing method of semiconductor devices as claimed in claim 3, which is characterized in that first interlayer dielectric layer and
The material of two interlayer dielectric layers is silica.
5. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the step of forming first side wall
Include:
It is sequentially depositing etching barrier layer and the first side wall medium layer over the substrate；And
By Self-aligned etching technique, the first grid structural top, second grid structural top and the etching are hindered
The first side wall medium layer in barrier is removed, and is respectively formed institute with the side wall in the first grid structure and second grid structure
State the first side wall.
6. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that the material of the etching barrier layer is
Silica, the material of first side wall medium layer are silicon nitride.
7. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that the step of forming second side wall
Include:
By Self-aligned etching technique, by the first grid structural top, second grid structural top, positioned at adjacent first
The first inter-level dielectric in substrate surface area between gate structure and second grid and in external zones substrate surface area
Layer and etching barrier layer are removed, and the first interlayer dielectric layer at the top of first side wall is removed, in the second gate
The side wall of first side wall of pole structure forms second side wall.
8. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that formed the second interlayer dielectric layer it
Afterwards, further includes:
In first interlayer dielectric layer and the second interlayer dielectric layer formed conductive contact plug, the conductive contact plug with
First source-drain area and the electrical connection of the second source-drain area.
9. a kind of manufacturing method of memory, which is characterized in that including semiconductor such as described in any item of the claim 1 to 8
Device making method.
10. the manufacturing method of memory as claimed in claim 9, the first grid structure includes being sequentially stacked on device region
On tunnel oxide, floating grid, dielectric layer and control gate between grid；The second grid structure includes being sequentially stacked on periphery
Gate oxide and polysilicon layer in area.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110098113A (en) * | 2019-04-17 | 2019-08-06 | 武汉新芯集成电路制造有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110190058A (en) * | 2019-05-27 | 2019-08-30 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
| CN112614843A (en) * | 2020-12-16 | 2021-04-06 | 上海华力微电子有限公司 | Semiconductor structure and preparation method thereof |
| CN113327886A (en) * | 2021-05-28 | 2021-08-31 | 上海华力微电子有限公司 | Method for preventing gap from being formed in interlayer medium filling process |
| CN113658918A (en) * | 2021-08-17 | 2021-11-16 | 福建省晋华集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110098113A (en) * | 2019-04-17 | 2019-08-06 | 武汉新芯集成电路制造有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110190058A (en) * | 2019-05-27 | 2019-08-30 | 武汉新芯集成电路制造有限公司 | Semiconductor devices and its manufacturing method |
| CN112614843A (en) * | 2020-12-16 | 2021-04-06 | 上海华力微电子有限公司 | Semiconductor structure and preparation method thereof |
| CN112614843B (en) * | 2020-12-16 | 2024-01-26 | 上海华力微电子有限公司 | Semiconductor structure and preparation method thereof |
| CN113327886A (en) * | 2021-05-28 | 2021-08-31 | 上海华力微电子有限公司 | Method for preventing gap from being formed in interlayer medium filling process |
| CN113658918A (en) * | 2021-08-17 | 2021-11-16 | 福建省晋华集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
| CN113658918B (en) * | 2021-08-17 | 2023-05-23 | 福建省晋华集成电路有限公司 | Method for manufacturing semiconductor device and semiconductor device |
| CN113690144A (en) * | 2021-09-15 | 2021-11-23 | 长江存储科技有限责任公司 | MOS transistor, manufacturing method thereof and three-dimensional memory comprising MOS transistor |
| CN113690144B (en) * | 2021-09-15 | 2024-02-27 | 长江存储科技有限责任公司 | MOS transistor, manufacturing method thereof and three-dimensional memory comprising MOS transistor |
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Application publication date: 20190312 |