CN109459910B - Sub-resolution auxiliary graph setting method for metal layer process hot spots - Google Patents
Sub-resolution auxiliary graph setting method for metal layer process hot spots Download PDFInfo
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- CN109459910B CN109459910B CN201811396619.3A CN201811396619A CN109459910B CN 109459910 B CN109459910 B CN 109459910B CN 201811396619 A CN201811396619 A CN 201811396619A CN 109459910 B CN109459910 B CN 109459910B
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- 239000002184 metal Substances 0.000 title claims abstract description 127
- 238000000034 method Methods 0.000 title claims abstract description 96
- 230000000694 effects Effects 0.000 claims abstract description 8
- 238000012937 correction Methods 0.000 claims abstract description 7
- 230000003287 optical effect Effects 0.000 claims abstract description 7
- 238000012216 screening Methods 0.000 claims abstract description 4
- 238000013461 design Methods 0.000 claims description 20
- 238000005457 optimization Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
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- 238000013500 data storage Methods 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention discloses a sub-resolution auxiliary graph setting method for metal layer process hot spots, which comprises the following steps: screening out a metal edge area of a metal layer process hot spot; generating a mark for the screened metal edge; performing conventional regular optical proximity effect correction on the metal layer layout; and judging the lengths of the adjacent sides of the marked metal sides, and optimizing the parameters of the sub-resolution auxiliary graph according to different lengths of the adjacent sides. The method provided by the invention optimizes the process hot spot with a smaller process window in the metal layer, adds the sub-resolution auxiliary graph and optimizes the parameters of the sub-resolution auxiliary graph, so that the process window can be effectively increased, the problem of metal wire short circuit caused by the smaller process window is avoided, the process risk is reduced, and the product yield is improved.
Description
Technical Field
The invention belongs to the field of manufacturing of microelectronic and semiconductor integrated circuits, and particularly relates to a method for setting a sub-resolution auxiliary graph for a metal layer process hotspot.
Background
With the rapid development of semiconductor manufacturing technology, in order to achieve faster operation speed, larger data storage capacity and more functions of semiconductor devices, semiconductor chips are developed towards higher integration level; the higher the integration of semiconductor chips, the smaller the Critical Dimension (CD) of semiconductor devices, and the process node of 28nm and below is reached. With the extension of nodes, the minimum design rule of a metal layer becomes smaller and smaller, a plurality of hot spot areas with smaller process windows are hidden in layout design, the size of a graph is continuously close to the capacity limit of a machine table of a photoetching machine, and the photoetching wavelength (193nm) used in the photoetching process is far larger than the characteristic size.
For these hot spot regions of the layout, there are generally two processing modes: one method is to stretch the layout, although the operation is simple, the controllability is not good, and the ideal effect can be achieved by repeated adjustment; the other method is to add Sub-resolution assist patterns (SRAF) in the layout, and the patterns of the assist patterns are not transferred to the semiconductor device at the later stage of actual exposure, so that the spatial frequency and the spatial image of the patterns can be effectively improved, the focusing depth of the patterns close to the exposure is increased, and the process window of a hot spot area is improved.
Two ways of adding the sub-resolution auxiliary pattern are as follows: one is sub-resolution auxiliary graph adding based on rules, namely, a set of sub-resolution auxiliary graph adding rules is established, and sub-resolution auxiliary graphs are added around a main graph; and the other is the addition of the sub-resolution auxiliary graph based on the model, namely the sub-resolution auxiliary graph with the best effect is obtained through iterative fitting operation after the model is established.
For the above-mentioned smaller and smaller size of the hot spot region, the parameter selection of the sub-resolution auxiliary pattern to be added becomes more and more important, and the conventional rule-based sub-resolution auxiliary pattern cannot meet the strict process window requirement. However, the model-based sub-resolution auxiliary graph adding method has long computation time for running scripts, has high requirements on computing resources, generally occupies a large amount of time and software and hardware computing resources, and the added graph has a complex shape, so that the cost and difficulty for manufacturing a mask and verifying the safety of the sub-resolution auxiliary graph are increased.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for setting a sub-resolution auxiliary graph aiming at a metal layer process hotspot, which can effectively increase the process window of a metal layer.
In order to solve the technical problem, the method for setting the sub-resolution auxiliary graph aiming at the metal layer process hotspot comprises the following steps:
step 1, screening out a metal edge area of a metal layer process hotspot;
step 2, generating marks on the screened metal edges;
step 3, performing conventional regular optical proximity effect correction on the metal layer layout;
and 4, judging the lengths of the adjacent sides of the marked metal sides, optimizing the parameters of the sub-resolution auxiliary graph according to different lengths of the adjacent sides, and adding the optimized sub-resolution auxiliary graph.
In step 1, the metal edge region is provided with a through hole for connecting other layers of the layout, and the distance between the through hole and the metal edge of the region is the minimum design rule or is greater than the minimum design rule but the distance difference is not more than 10 nm.
Further, the distance between the through hole and the metal edge of the area is not more than 30 nm.
Further, the through holes comprise an upper through hole layer and a lower through hole layer, and the side length of the upper through hole layer and the side length of the lower through hole layer are the minimum design rule.
In step 1, among different metal layer process hot spots located in the same layer, the distance between the screened metal edges is the minimum design rule, or is greater than the minimum design rule but the distance difference is not more than 10nm, and the width of one metal layer process hot spot in the direction perpendicular to the metal edge is not less than 140 nm.
In step 4, the adjacent side of the metal side is perpendicular to the marked metal side, and the length of the adjacent side is not more than 50 nm.
Preferably, in step 4, parameters of the sub-resolution auxiliary pattern are optimized according to lengths of adjacent sides of the marked metal sides, distances between the screened metal sides, and widths of metal layer process hot spots in a direction perpendicular to the metal sides.
Wherein the parameters of the sub-resolution auxiliary pattern include a distance between the sub-resolution auxiliary pattern and the metal edge to be marked, a length and a width of the sub-resolution auxiliary pattern.
Preferably, after step 4, model-based OPC is performed on the new layout with the sub-resolution auxiliary pattern added.
The invention optimizes the process hot spot with smaller process window in the metal layer, adds the sub-resolution exposure auxiliary graph and optimizes the parameters thereof, can effectively enlarge the process window, avoids the problem of metal wire short circuit caused by smaller process window, reduces process risk and improves the product yield.
Drawings
FIG. 1 is an original layout of a metal layer and upper and lower via layers;
FIG. 2 is an improved layout of metal layers and upper and lower via layers;
fig. 3 is a flowchart of a sub-resolution auxiliary pattern setting method of the present invention.
Wherein the reference numerals are as follows:
m11 first Process hotspot zone M12 second Process hotspot zone
L11 Metal edge of first Process Hot Spot region L12 Metal edge of second Process Hot Spot region
C1 upper via layer C2 lower via layer
L12-1 first adjacent edge L12-2 second adjacent edge
S the distance between the metal edge of the first process hot spot area and the metal edge of the second process hot spot area
D width of second process hot spot region in direction perpendicular to metal edge L12
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The method for setting the sub-resolution auxiliary graph aiming at the metal layer process hotspot mainly occurs in the integrated circuit design OPC (Optical Proximity Correction) layout processing and graph enhancing process, as shown in FIG. 3, and comprises the following steps:
step 1, screening out a metal edge area of a metal layer process hotspot;
in different metal layer process hot spots located on the same layer, the distance between the screened metal edges is the minimum design rule, or is larger than the minimum design rule but the distance difference is not more than 10nm, wherein the width of one metal layer process hot spot in the direction vertical to the metal edge of the metal layer process hot spot is not less than 140 nm;
the metal edge region is internally provided with through holes for connecting other layers of the layout, the through holes comprise an upper through hole layer and a lower through hole layer, and the distance between each through hole and the metal edge of the region is the minimum design rule or is greater than the minimum design rule but the distance difference is not more than 10 nm;
preferably, the side length of the upper through hole layer and the lower through hole layer is the minimum design rule, and the distance between the through hole and the metal side of the region where the through hole is located is not more than 30 nm;
step 2, generating marks on the screened metal edges;
step 3, performing conventional regular optical proximity effect correction on the metal layer layout;
step 4, judging the lengths of the adjacent sides of the marked metal sides, optimizing the parameters of the sub-resolution auxiliary graph according to different lengths of the adjacent sides, and adding the optimized sub-resolution auxiliary graph;
the adjacent edge of the metal edge is vertical to the marked metal edge, and the length of the adjacent edge is not more than 50 nm;
preferably, the parameters of the sub-resolution auxiliary graph are optimized according to the lengths of the adjacent edges of the marked metal edges, the distance between the screened metal edges and the width of the metal layer process hot spot in the direction perpendicular to the metal edges.
Preferably, the optimization method specifically comprises the following steps:
firstly, defining a rectangular area by taking a marked metal edge and an adjacent edge of the metal edge as edges;
secondly, defining an area boundary formed by removing the rectangular area from a metal layer process hot spot area where the marked metal edge is positioned as a target layer;
and thirdly, adding a sub-resolution auxiliary graph SRAF, and enabling the minimum distance between the sub-resolution auxiliary graph and the target layer to be a set minimum value, wherein the set minimum value can be obtained through experiments.
Preferably, after step 4, model-based OPC is performed on the new layout with the sub-resolution auxiliary pattern added.
Wherein the parameters of the sub-resolution auxiliary pattern include a distance between the sub-resolution auxiliary pattern and the metal edge to be marked, a length and a width of the sub-resolution auxiliary pattern.
First embodiment
As shown in fig. 1, the original layout of the metal layer and the upper and lower via layers in the process hot spot region is screened out.
Wherein, the first process hot spot region M11 and the second process hot spot region M12 are the same layer metal, the distance S between the metal edge L11 of the first process hot spot region M11 and the metal edge L12 of the second process hot spot region M12 is the minimum design rule, the width D of the second process hot spot region M12 in the direction perpendicular to the metal edge L12 is 140nm, the upper via layer C1 in the first process hot spot region M11 is communicated with the upper layer circuit, the lower via layer C2 in the second process hot spot region M12 is communicated with the lower layer circuit, and the upper via layer C1 is tangent to the metal edge L11 of the first process hot spot region (i.e., one side of the upper via layer C1 is attached to the metal edge L11 of the first process hot spot region), and the lower via layer C2 is tangent to the metal edge L12 of the second process hot spot region (i.e., one side of the lower via layer C2 is tangent to the metal edge L12 of the second process hot spot region), so as to satisfy the minimum design rule of the metal layer and the upper and lower via layers.
In this embodiment, a mark is generated on the metal edge L12 of the selected wider process hot spot region M12.
After performing the conventional regular OPC, the lengths of the first adjacent edge L12-1 and the second adjacent edge L12-2 of the marked metal edge L12 are determined, and in this embodiment, the lengths of the adjacent edges are about 10 nm.
The parameters of the SRAF are optimized according to the adjacent edge length, width D, and distance S between metal edge L11 and metal edge L12, thereby determining the distance between the SRAF and metal edge L12, the length and width of the SRAF, and adding the optimized SRAF (in this embodiment, negative SRAF) to the metal layer.
As shown in fig. 2, the optimization method specifically includes: defining a rectangular area by taking the marked metal edge L12 and adjacent edges L12-1 and L12-2 of the metal edge L12 as edges, such as a diagonal area in FIG. 2; defining the area boundary formed by removing the rectangular area in the metal layer process hot spot area M12 where the marked metal edge L12 is located as a target layer; the sub-resolution auxiliary pattern SRAF is added so that the minimum distance from the sub-resolution auxiliary pattern to the target layer is a set minimum value, which can be obtained by an experiment. Since the actual pattern includes an outwardly protruding rectangular area, the addition of the sub-resolution auxiliary pattern SRAF for the target layer to both the marked metal edge L12 and the adjacent edges L12-1, L12-2 does not violate the minimum rule, while also achieving adjustable optimization of the distance parameter of the SRAF to the protruding marked metal edge L12.
And finally, performing subsequent model type optical proximity effect correction.
Of course, the optimization of the SRAF parameters, the distance between the metal edge L11 and the metal edge L12, the width of one edge perpendicular to the metal edge, the length of the adjacent edge of the metal edge, etc. are determined by considering the actual process capability.
The method optimizes the process hot spot with a smaller process window in the metal layer, optimizes the wider metal area and adds the sub-resolution exposure auxiliary graph with optimized parameters, obtains the increase of the insulation area between the metal wire and the metal wire by the simulation result, can effectively enlarge the process window, avoids the problem of short circuit of the metal wire caused by the smaller process window, reduces the process risk and improves the product yield.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.
Claims (8)
1. A sub-resolution auxiliary graph setting method for a metal layer process hotspot is characterized by comprising the following steps:
step 1, screening out a metal edge area of a metal layer process hotspot;
step 2, generating marks on the screened metal edges;
step 3, performing conventional regular optical proximity effect correction on the metal layer layout;
step 4, judging the lengths of the adjacent sides of the marked metal sides, optimizing the parameters of the sub-resolution auxiliary graph according to the lengths of the adjacent sides of the marked metal sides, the distance between the screened metal sides and the width of the metal layer process hot spot in the direction vertical to the metal sides of the metal layer process hot spot, and adding the optimized sub-resolution auxiliary graph;
the optimization method specifically comprises the following steps:
firstly, defining a rectangular area by taking a marked metal edge and an adjacent edge of the metal edge as edges;
secondly, defining an area boundary formed by removing the rectangular area from a metal layer process hot spot area where the marked metal edge is positioned as a target layer;
and thirdly, adding a sub-resolution auxiliary graph, and enabling the minimum distance between the sub-resolution auxiliary graph and the target layer to be a set minimum value.
2. The method for setting the sub-resolution auxiliary pattern for the metal layer process hot spot according to claim 1, wherein in step 1, the metal edge region has a via hole connecting other layers of the layout, and the distance between the via hole and the metal edge of the region is the minimum design rule or greater than the minimum design rule but the distance difference is not more than 10 nm.
3. The method as claimed in claim 2, wherein the distance between the via hole and the metal edge of the region is not more than 30 nm.
4. The method as claimed in claim 2, wherein the through holes include an upper via layer and a lower via layer, and the side length of the upper via layer and the lower via layer is a minimum design rule.
5. The method as claimed in claim 1, wherein in step 1, the distance between the metal edges screened from different metal layer process hot spots located in the same layer is the minimum design rule, or is greater than the minimum design rule but the distance difference is not more than 10nm, and the width of one metal layer process hot spot in the direction perpendicular to the metal edge is not less than 140 nm.
6. The method for setting the sub-resolution auxiliary pattern for the metal layer process hot spot as claimed in claim 1, wherein in step 4, the adjacent edge of the metal edge is perpendicular to the marked metal edge, and the length of the adjacent edge is not more than 50 nm.
7. The method as claimed in claim 1, wherein the parameters of the sub-resolution auxiliary pattern include a distance between the sub-resolution auxiliary pattern and a metal edge to be marked, and a length and a width of the sub-resolution auxiliary pattern.
8. The method for setting the sub-resolution auxiliary pattern for the metal layer process hotspot according to claim 1, wherein after the step 4, the new layout with the sub-resolution auxiliary pattern added is subjected to model-based optical proximity effect correction.
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| CN116776782B (en) * | 2023-08-25 | 2023-11-10 | 宁波联方电子科技有限公司 | Metal level EDA display device and method in integrated circuit process manual |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106094424A (en) * | 2016-07-22 | 2016-11-09 | 上海华力微电子有限公司 | Redundant pattern adding method with auxiliary figure with low resolution |
| CN107065430A (en) * | 2017-03-10 | 2017-08-18 | 上海集成电路研发中心有限公司 | A kind of rule-based Sub-resolution assist features adding method |
| CN107885028A (en) * | 2017-12-28 | 2018-04-06 | 上海华力微电子有限公司 | The method that auxiliary figure with low resolution determines in OPC modelings |
| CN107908893A (en) * | 2017-11-29 | 2018-04-13 | 上海华力微电子有限公司 | The domain processing method of missing technique hot spot at the top of a kind of metal layer photoresist |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106094424A (en) * | 2016-07-22 | 2016-11-09 | 上海华力微电子有限公司 | Redundant pattern adding method with auxiliary figure with low resolution |
| CN107065430A (en) * | 2017-03-10 | 2017-08-18 | 上海集成电路研发中心有限公司 | A kind of rule-based Sub-resolution assist features adding method |
| CN107908893A (en) * | 2017-11-29 | 2018-04-13 | 上海华力微电子有限公司 | The domain processing method of missing technique hot spot at the top of a kind of metal layer photoresist |
| CN107885028A (en) * | 2017-12-28 | 2018-04-06 | 上海华力微电子有限公司 | The method that auxiliary figure with low resolution determines in OPC modelings |
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