CN109427812A - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN109427812A CN109427812A CN201710751228.8A CN201710751228A CN109427812A CN 109427812 A CN109427812 A CN 109427812A CN 201710751228 A CN201710751228 A CN 201710751228A CN 109427812 A CN109427812 A CN 109427812A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000003475 lamination Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000009825 accumulation Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- 239000011810 insulating material Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000001447 compensatory effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
A kind of semiconductor structure includes a substrate, a lamination, a hole and an active structure.Lamination is disposed on the substrate.Lamination is made of multiple conductive layers alternating with each other and multiple insulating layers.The conductive layer includes one i-th layer of conductive layer and the jth layer conductive layer that is arranged in above i-th layer of conductive layer, and i-th layer of conductive layer has thickness ti, jth layer conductive layer is with thickness tj, tjGreater than ti.Hole passes through lamination.Hole has the diameter D for respectively corresponding i-th layer of conductive layer and jth layer conductive layeriWith diameter Dj, DjGreater than Di.Active structure is arranged in hole.Active structure includes a channel layer.The channel layer is arranged along the one side wall of hole, and is isolated with the conductive layer of lamination.
Description
Technical field
The present invention relates to a kind of semiconductor structure and its manufacturing methods.It include compensatory lamination the present invention is more particularly directed to one kind
The semiconductor structure and its manufacturing method of structure.
Background technique
In order to reduce volume, reduce weight, increase power density and improve portability etc. reason, three-dimensional (3D) half
Conductor structure is developed.In the typical process of some 3 D semiconductor structures, it can be formed and be stacked in including multiple layers
On substrate, and one or more holes and/or channel are subsequently formed across lamination.Since technique limits, described hole and/or channel
There may be inclined side wall, thus, along a vertical direction of hole and/or channel, size and area are gradually changed.This can
The deviation on some equipment energy characteristics, the deviation especially on electric properties can further be caused.With the number in lamination middle layer
Mesh increases, which may will become the problem of will affect device performance and operation.
Summary of the invention
The present invention be directed to the offer of compensatory laminated construction, which compensates for along the one vertical of hole and/or channel
Influence caused by different sizes and area on direction.
According to some embodiments, a kind of semiconductor structure is provided.Such semiconductor structure includes a substrate, a lamination, one
Hole and an active structure.Lamination is disposed on the substrate.Lamination is by multiple conductive layers and multiple insulating layer structures alternating with each other
At.The conductive layer includes one i-th layer of conductive layer and the jth layer conductive layer that is arranged in above i-th layer of conductive layer, and i-th layer is led
Electric layer has thickness ti, jth layer conductive layer is with thickness tj, tjGreater than ti.Hole passes through lamination.Hole, which has, respectively corresponds i-th
The diameter D of layer conductive layer and jth layer conductive layeriWith diameter Dj, DjGreater than Di.Active structure is arranged in hole.Active structure packet
Include a channel layer.The channel layer is arranged along the one side wall of hole, and is isolated with the conductive layer of lamination.
According to some embodiments, a kind of manufacturing method of semiconductor structure is provided.Such manufacturing method includes the following steps.
Firstly, forming a lamination on a substrate.Lamination is made of multiple sacrificial layers alternating with each other and multiple insulating layers.The sacrifice
Layer includes one i-th layer of sacrificial layer and the jth layer sacrificial layer being formed in above i-th layer of sacrificial layer, and i-th layer of sacrificial layer has thickness
ti, jth layer sacrificial layer is with thickness tj, tjGreater than ti.A hole is formed across lamination.Hole, which has, respectively corresponds i-th layer of sacrifice
The diameter D of layer and jth layer sacrificial layeriWith diameter Dj, DjGreater than Di.An active structure is formed in hole.Active structure includes one
Channel layer.The channel layer is formed along the one side wall of hole, and is separated with the sacrificial layer of lamination.
More preferably understand to have to the above-mentioned and other aspect of the present invention, hereafter spy enumerates embodiment, and cooperates appended attached
Detailed description are as follows for figure:
Detailed description of the invention
Fig. 1 shows according to the embodiment one illustrative semiconductor structure.
Fig. 2 shows another exemplary semiconductor's structures according to the embodiment.
Fig. 3 shows the influence of the diameter and passage length of hole on the one hand.
Fig. 4 A~4B shows the influence of the diameter of hole on the other hand.
Fig. 5 A~5H shows an illustrative manufacturing method of semiconductor structure according to the embodiment.
[symbol description]
100,200: semiconductor structure
102: substrate
104,204: lamination
106、106(0)、106(1)、106(2)、106(3)、...、106(i)、...、106(j)、...、106(n-2)、
106(n-1)、206(0)、206(1)、206(2)、206(3)、...、206(i)、...、206(j)、...、206(n-2)、206
(n-1): conductive layer
108: insulating layer
110: coating
112: hole
114: active structure
116: channel layer
118: accumulation layer
120: insulating materials
122: conducting element
304: lamination
306(0)、306(1)、306(2)、306(3)、...、306(i)、...、306(j)、...、306(n-2)、306(n-
1): sacrificial layer
352: ion implantation technology
354: opening
356: metal material
358: high dielectric constant material
360: ion implantation technology
362: conducting element
Ai、Aj: conductive area
Di、Dj: diameter
G(1)、G(2)、...、Group
L0、L1、L2、L3、...、Li、...、Lj、...、Ln-2、Ln-1、L’0、L’1、L’2、L’3、...、L’i、...、L
’j、...、L’n-2、L’n-1: passage length
t0、t1、t2、t3、...、ti、...、tj、...、tn-2、tn-1、t’0、t’1、t’2、t’3、...、t’i、...、t
’j、...、t’n-2、t’n-1: thickness
θ: angle
Specific embodiment
A variety of different embodiments are described in detail below in conjunction with appended attached drawing.Appended attached drawing is served only for
Describe and explain purpose, rather than limitation purpose.For the sake of clarity, element may and be painted not according to actual ratio.This
Outside, some elements and/or component symbol may be omitted from attached drawing.In the present invention, when describing an element in the singular,
Also allow to include the case where the more than one element.It is contemplated that the element and feature in an embodiment, it can be advantageous
Ground is included in another embodiment, without further elucidated above.
Fig. 1 is please referred to, according to the embodiment one illustrative semiconductor structure 100 is shown.Semiconductor structure 100 includes one
Substrate 102, a lamination 104, a hole 112 and an active structure 114.Lamination 104 is arranged on substrate 102.Lamination 104 by
Multiple conductive layers 106 (106 (0)~106 (n-1)) alternating with each other and multiple insulating layers 108 are constituted.Conductive layer 106 includes one
I-th layer of conductive layer 106 (i) and the jth layer conductive layer 106 (j) being arranged above i-th layer of conductive layer 106 (i), i-th layer of conduction
106 (i) of layer have thickness ti, jth layer conductive layer 106 (j) is with thickness tj, tjGreater than ti.Hole 112 passes through lamination 104.Hole
Hole 112 has the diameter D for respectively corresponding i-th layer of conductive layer 106 (i) He jth layer conductive layer 106 (j)iWith diameter Dj, DjIt is greater than
Di.Active structure 114 is arranged in hole 112.Active structure 114 includes a channel layer 116.Channel layer 116 is along hole 112
One side wall setting, and be isolated with the conductive layer of lamination 104 106.
In some embodiments, on substrate 102, lamination is further arranged in a coating 110 to the setting of lamination 104
On 104, and hole 112 passes through coating 110 and lamination 104.In some embodiments, the side of substrate 102 and hole 112
Angle, θ between wall is less than 90 °, and e.g., about 87 °.Hole 112 can have the diameter become larger from the bottom up.In some realities
It applies in example, the diameter of hole 112 is between 80 nanometers and 130 nanometers.For example, hole 112 can have 80 to receive in bottom
The diameter of rice, and there is 130 nanometers of diameter on top.Accordingly, conductive layer 106 can have the thickness gradually to thicken from the bottom up
Degree, details will be described in subsequent paragraph.In some embodiments, conductive layer 106 may include a metal material and a Gao Jie electricity
Constant material.According to some embodiments, semiconductor structure 100 can be a memory construction.In such embodiments, active structure
114 can further include an accumulation layer 118.Accumulation layer 118 is arranged between channel layer 116 and lamination 104.Accumulation layer 118 may include
One trapping layer (is not painted).More specifically, in some embodiments, accumulation layer 118 may include from the side wall of hole 112 sequentially
A mask layer (not being painted), a trapping layer (not being painted) and the tunneling layer (not being painted) being arranged, and can be by monoxide-nitrogen
Compound-oxide (ONO) lamination is formed.Multiple storage units are by between active structure 114 and the conductive layer 106 of lamination 104
Intersection point is defined, and the storage unit constitutes a part of a 3-dimensional memory cell array.In some embodiments, active structure
114 can further include an insulating materials 120.Insulating materials 120 is filled into the remaining space of hole 112.In some embodiments,
One conducting element 122 may be provided on insulating materials 120.In some embodiments, the conductive layer 106 is multiple wordline, is had
Source structure 114 is couple to a bit line by conducting element 122.
The configuration detail of conductive layer 106 will be described now.Specifically, conductive layer 106 can be one the 0th layer from the bottom up
Conductive layer 106 (0) is to one (n-1)th layer of conductive layer 106 (n-1).0th layer of conductive layer 106 (0) is to (n-1)th layer of 106 (n- of conductive layer
1) it is respectively provided with thickness t0To tn-1, t0≤t1≤...≤tn-2≤tn-1.In addition, in addition, the 0th layer of conductive layer 106 (0) is to (n-1)th
Layer conductive layer 106 (n-1) can provide passage length L respectively0To Ln-1, L0≤L1≤...≤Ln-2≤Ln-1.According to some implementations
Example, passage length L0To Ln-1It is defined in a vertical direction, in full text of the invention, vertical direction means substantially perpendicular to base
One direction of plate 102.To each passage length (L0To Ln-1) it is substantially equal to corresponding thickness (t0To tn-1).In some realities
It applies in example, thickness t0To tn-1, it is inconjunction with passage length L0To Ln-1, between 20 nanometers and 60 nanometers.For example, thickness
t0With passage length L0It can be 20 nanometers, and thickness tn-1With passage length Ln-1It can be 60 nanometers.
As long as being capable of providing compensation function, so that deviation is fallen within the acceptable range, thickness t0To tn-1, it is inconjunction with logical
Road length L0To Ln-1, can configure in any suitable manner.In some embodiments, as shown in Figure 1, each conductive layer 106
It is thicker than the conductive layer 106 for being located at 106 lower section of each conductive layer.In other words, t0< t1< ... < tn-2< tn-1.Change speech
It, L0< L1< ... < Ln-2< Ln-1。
In further embodiments, conductive layer 106 divides for multiple groups, and the conductive layer 106 in each group has identical
Thickness, and be thicker than the conductive layer 106 in the group below each group.In such embodiments, for 0
To at least integer an i, t among n-2i=ti+1.In other words, at least integer an i, L among 0 to n-2i=Li+1。
Referring to figure 2., show this kind of embodiment one of special category.In this special category, conductive layer
106 are divided into multiple groups, the thickness having the same of conductive layer 106 in each group, and are thicker than positioned at each group
Conductive layer 106 in the group of lower section.For example, conductive layer 106 can be divided intoA group, electricity are each group
Including m conductive layer, t '0=t '1=...=t 'm-1< t 'm... < t 'n-m=...=t 'n-2=t 'n-1.In other words, conductive layer
106 can be divided intoA group, L '0=L '1=...=L 'm-1< ... < L 'n-m=...=L 'n-2=L 'n-1.In Fig. 2 institute
In the semiconductor structure 200 shown, m 2.In other words, in lamination 204, conductive layer 206 (0) to 206 (n-1) is divided intoA group
Group G (1) arrivesGroup G (1) is arrivedAmong each include two among conductive layer 206 (0) to 206 (n-1), t '0=
t’1< t '2=t '3< ... < t 'n-2=t 'n-1, L '0=L '1< L '2=L '3< ... < L 'n-2=L 'n-1。
According to the lamination of above-described embodiment, such as lamination 104 or 204, referred to as compensatory laminated construction in the present invention.?
On the one hand, biggish hole diameter means lesser electric field, to have lower program/erase speed and more poor volume
Journey/erasing ability.This is reflected in trend shown in Fig. 3.In contrast, biggish passage length causes biggish electric field, thus
There are higher program/erase speed and preferable program/erase ability.Therefore, in semiconductor structure according to the embodiment,
It influences, can be compensated by biggish passage length caused by program/erase operation of the biggish hole diameter for device,
It is reached by thicker conductive layer.Thus, it is possible to provide preferable stability.
In addition, biggish hole diameter means that the conductive area of corresponding conductive layer is smaller, to reduce conductance
(conductance).For example, as shown in Figure 4 A and 4 B shown in FIG., hole 1122 corresponds to conductive layer 106 (j) with biggish
Diameter Dj.Therefore, the conductive area A of conductive layer 106 (j)jLess than the conductive area A of conductive layer 106 (i)i.This is unfavorable for being arranged
Electric current in the conductive layer of higher position (higher position) passes through, as shown in Figure 4 A and 4 B shown in FIG..It for example, is word in conductive layer
In the case where line, it may occur however that the attenuating (degradation) of word line resistance.However, such case can be by the thickness of conductive layer
Degree is compensated.In other words, influence caused by conductance of the biggish hole diameter for conductive layer, can be by thicker conductive layer
Thickness is compensated.
Referring now to Fig. 5 A~5H, an illustrative manufacturing method of semiconductor structure according to the embodiment is shown.Figure
5A~5H is painted by replacing the technique of sacrificial layer to form semiconductor structure as shown in Figure 1.However, other techniques can also be used
In formation semiconductor structure according to the embodiment.For example, it can directly be formed by multiple conductive layers alternating with each other and more
The lamination that a insulating layer is constituted, and not formed sacrificial layer.It is further possible to form other semiconductor junctions according to the embodiment
Structure, such as semiconductor structure shown in Fig. 2.
As shown in Figure 5A, a substrate 102 is provided.Substrate 102 can be silicon substrate.It can carry out ion implantation technology.Form one
Lamination 304 on substrate 102, e.g. by depositing operation, lamination 304 by multiple sacrificial layers alternating with each other (306 (0) to
306 (n-1)) and the composition of multiple insulating layers 108.Insulating layer 108 can be formed of oxide, thickness having the same.Sacrificial layer 306
(0) it can be formed to 306 (n-1) by nitride.Sacrificial layer 306 (0) includes one i-th layer of sacrificial layer 306 (i) and shape to 306 (n-1)
At the jth layer sacrificial layer 306 (j) above i-th layer of sacrificial layer 306 (i), i-th layer of sacrificial layer 306 (i) has thickness ti, the
J layers of sacrificial layer 306 (j) have thickness tj, tjGreater than ti.More specifically, sacrificial layer 306 (0) can be respectively provided with to 306 (n-1)
Thickness t0To tn-1, t0≤t1≤...≤tn-2≤tn-1.In fig. 5, sacrificial layer 306 (0) is depicted as sacrificing to 306 (n-1)
Each is thicker than the institute below each among the sacrificial layer 306 (0) to 306 (n-1) among layer 306 (0) to 306 (n-1)
State sacrificial layer namely t0< t1< ... < tn-2< tn-1.However, in further embodiments, sacrificial layer 306 (0) to 306 (n-
1) there can be the thickness gradually changed in a manner of group.In such embodiments, at least integer an i, t among 0 to n-2i
=ti+1.For example, sacrificial layer can be divided intoA group namely each group include m sacrificial layer, t0=t1=...
=tm-1< tm... < tn-m=...=tn-2=tn-1.In some embodiments, thickness t0To tn-1Between 20 nanometers and 60 nanometers
Between.For example, thickness t0It can be 20 nanometers, and thickness tn-1It can be 60 nanometers.In some embodiments, one can be formed to cover
Cap rock 110 is on lamination 304.Coating 110 can be formed of oxide.
As shown in Figure 5 B, it forms a hole 112 and forms a lamination 304, e.g. pass through etch process.For example, hole
Hole 112 can have to be about the one side wall of 87 ° of angle tilt.Hole 112 have respectively correspond i-th layer of sacrificial layer 306 (i) and
The diameter D of jth layer sacrificial layer 306 (j)iWith diameter Dj, DjGreater than Di.In some embodiments, the diameter of hole 112 is between 80
Between nanometer and 130 nanometers.For example, hole 112 can have 80 nanometers of diameter in bottom, and have 130 to receive on top
The diameter of rice.
As shown in Figure 5 C, an active structure 114 is formed in hole 112.Active structure 114 includes a channel layer 116.It is logical
Channel layer 116 is formed along the side wall of hole 112, and is separated with the sacrificial layer of lamination 304 306 (0) to 306 (n-1).Channel
Layer 116 can be isolated by any suitable insulating materials with lamination 304.In some embodiments, an accumulation layer 118 provide every
From function.Accumulation layer 118 may include a trapping layer (not being painted).It also specifically says, in some embodiments, accumulation layer 118 can
Including be set in sequence from the side wall of hole 112 a mask layer (not being painted), a trapping layer (not being painted a) and tunneling layer is (not
It is painted), and can be formed by monoxide-Nitride Oxide (ONO) lamination.According to some embodiments, active structure 114
Formation can be by being initially formed an ONO lamination (that is, accumulation layer 118) on the side wall of hole 112.Then, a polycrystalline is formed
Silicon layer thereon, as channel layer 116.A fillable insulating materials 120, such as oxide, to the remaining space of hole 112
In.Therefore, an all around gate (gate-all-around) structure is just formed.In some embodiments, one can further be formed
Conducting element 122 is on insulating materials 120.Then, as shown in Figure 5 D, ion implantation technology 352 can be carried out, to provide for position
The connection of line.Dopant can be arsenic.
Then, replace sacrificial layer 306 (0) to 306 (n-1) with multiple conductive layers 106.As shown in fig. 5e, an opening is formed
354 pass through lamination 304, e.g. pass through etch process.As illustrated in figure 5f, sacrificial layer 306 (0) is removed to 306 by opening 354
(n-1), e.g. pass through etch process.Then, conductive layer 106 is formed.According to some embodiments, conductive layer 106 may include one
Metal material 356 and a high dielectric constant material 358.As depicted in fig. 5g, in some embodiments, high dielectric constant material can be formed
The upper side and lower side and circular active structure 114 of material 358 in insulating layer 108.High dielectric constant material 358 can be Al2O3.Then,
Metal material 356 is filled into the remainder for removing space caused by sacrificial layer 306 (0) to 306 (n-1).Metal material
356 can be tungsten.In some embodiments, to provide wordline.
In some embodiments, opening 354 provides the source region for being used for semiconductor structure, and can carry out an ion implanting
Technique 360, to form source area.Dopant can be arsenic.Then, as illustrated in fig. 5h, be capable of forming a conducting element 362 (namely
Source conductive element) in opening 354.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (10)
1. a kind of semiconductor structure, comprising:
One substrate；
One lamination, on the substrate, which is made of multiple conductive layers alternating with each other and multiple insulating layers, described to lead for setting
Electric layer includes one i-th layer of conductive layer and the jth layer conductive layer that is arranged in above i-th layer of conductive layer, i-th layer of conductive layer tool
There is thickness ti, the jth layer conductive layer is with thickness tj, tjGreater than ti；
One hole, passes through the lamination, which has the diameter D for respectively corresponding i-th layer of conductive layer and the jth layer conductive layeriWith
Diameter Dj, DjGreater than Di；And
One active structure is arranged in the hole, which includes:
One channel layer is arranged along the one side wall of the hole, and is isolated with the conductive layer of the lamination.
2. semiconductor structure as described in claim 1, wherein the hole has the diameter become larger from the bottom up, described to lead
Electric layer has the thickness gradually to thicken from the bottom up.
3. semiconductor structure as claimed in claim 2, wherein respectively the conductive layer is thicker than below described respectively conductive layer
The conductive layer.
4. semiconductor structure as claimed in claim 2, wherein the conductive layer is divided into multiple groups, it is respectively described in the group
Conductive layer thickness having the same, and it is thicker than the conductive layer in the group below described respectively group.
5. semiconductor structure as claimed in claim 2, wherein the conductive layer is divided into multiple groups, each institute in the group
Conductive layer thickness having the same is stated, and is thicker than the conductive layer in the group below described respectively group.
6. semiconductor structure as described in claim 1, wherein one the 0th layer of conductive layer of the conductive layer from the bottom up is to one
N-1 layers of conductive layer, the 0th layer of conductive layer provide passage length L to (n-1)th layer of conductive layer respectively0To Ln-1, L0≤L1≤…≤
Ln-2≤Ln-1。
7. semiconductor structure as claimed in claim 6, wherein L0< L1< ... < Ln-2< Ln-1。
8. semiconductor structure as claimed in claim 6, wherein at least integer an i, L among 0 to n-2i=Li+1。
9. semiconductor structure as claimed in claim 6, wherein the conductive layer is divided intoA group, L0=L1=...=
Lm-1< ... < Ln-m=...=Ln-2=Ln-1。
10. a kind of manufacturing method of semiconductor structure, comprising:
Form a lamination on a substrate, which is made of multiple sacrificial layers alternating with each other and multiple insulating layers, described sacrificial
Domestic animal layer includes one i-th layer of sacrificial layer and the jth layer sacrificial layer being formed in above i-th layer of sacrificial layer, i-th layer of sacrificial layer tool
There is thickness ti, the jth layer sacrificial layer is with thickness tj, tjGreater than ti；
A hole is formed across the lamination, which has the diameter for respectively corresponding i-th layer of sacrificial layer and the jth layer sacrificial layer
DiWith diameter Dj, DjGreater than Di；And
An active structure is formed in the hole, which includes:
One channel layer is formed along the one side wall of the hole, and is separated with the sacrificial layer of the lamination.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110265404A (en) * | 2019-06-28 | 2019-09-20 | 长江存储科技有限责任公司 | For the laminated construction of three-dimensional storage, three-dimensional storage and preparation method thereof |
| CN110289259A (en) * | 2019-06-27 | 2019-09-27 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN110349971A (en) * | 2019-06-28 | 2019-10-18 | 长江存储科技有限责任公司 | For the laminated construction of three-dimensional storage, three-dimensional storage and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100078701A1 (en) * | 2008-09-30 | 2010-04-01 | Samsung Electronics Co., Ltd. | Three-dimensional microelectronic devices including repeating layer patterns of different thicknesses |
| US20110012188A1 (en) * | 2009-07-14 | 2011-01-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| CN102122661A (en) * | 2009-12-16 | 2011-07-13 | 三星电子株式会社 | Semiconductor devices and methods for fabricating the same |
| US20140084358A1 (en) * | 2012-09-27 | 2014-03-27 | Woo-Sung Lee | Nonvolatile memory device and method for fabricating the same |
| US20140332873A1 (en) * | 2013-05-13 | 2014-11-13 | SK Hynix Inc. | Semiconductor device |
-
2017
- 2017-08-28 CN CN201710751228.8A patent/CN109427812A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100078701A1 (en) * | 2008-09-30 | 2010-04-01 | Samsung Electronics Co., Ltd. | Three-dimensional microelectronic devices including repeating layer patterns of different thicknesses |
| US20110012188A1 (en) * | 2009-07-14 | 2011-01-20 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| CN102122661A (en) * | 2009-12-16 | 2011-07-13 | 三星电子株式会社 | Semiconductor devices and methods for fabricating the same |
| US20140084358A1 (en) * | 2012-09-27 | 2014-03-27 | Woo-Sung Lee | Nonvolatile memory device and method for fabricating the same |
| US20140332873A1 (en) * | 2013-05-13 | 2014-11-13 | SK Hynix Inc. | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110289259A (en) * | 2019-06-27 | 2019-09-27 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN110289259B (en) * | 2019-06-27 | 2020-09-29 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN110265404A (en) * | 2019-06-28 | 2019-09-20 | 长江存储科技有限责任公司 | For the laminated construction of three-dimensional storage, three-dimensional storage and preparation method thereof |
| CN110349971A (en) * | 2019-06-28 | 2019-10-18 | 长江存储科技有限责任公司 | For the laminated construction of three-dimensional storage, three-dimensional storage and preparation method thereof |
| CN110265404B (en) * | 2019-06-28 | 2020-10-23 | 长江存储科技有限责任公司 | Laminated structure for three-dimensional memory, three-dimensional memory and preparation method thereof |
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