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CN109411475B - Memory and forming method thereof - Google Patents

Memory and forming method thereof Download PDF

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Publication number
CN109411475B
CN109411475B CN201811335682.6A CN201811335682A CN109411475B CN 109411475 B CN109411475 B CN 109411475B CN 201811335682 A CN201811335682 A CN 201811335682A CN 109411475 B CN109411475 B CN 109411475B
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layer
stress
memory
isolation
source contact
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CN109411475A (en
Inventor
姚兰
吕震宇
胡禺石
陈俊
郭美澜
方原
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention relates to a memory and a forming method thereof, wherein the memory comprises: the memory structure comprises a substrate, wherein a memory stack structure is formed on the surface of the substrate and comprises insulating layers and control gate structure layers which are alternately stacked; a common source contact through the storage stack structure; an isolation layer between the storage stack structure and the common source contact, the isolation layer comprising at least one dielectric layer capable of blocking F diffusion. The performance of the memory is improved.

Description

Memory and forming method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.
Background
In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.
In the 3D NAND flash memory structure, a memory array structure is arranged on the surface of a substrate, and an array common source contact part penetrating through the memory array structure is formed in the memory array structure. The array common source contact part is isolated from the storage array structure through an insulating layer.
However, in the prior art, the insulating layer between the array common-source contact and the memory array structure is easily damaged, which causes a short circuit between the array common-source contact and the control gate in the memory array structure, and thus reduces the reliability of the memory.
Disclosure of Invention
The invention aims to provide a memory and a forming method thereof, and the performance of the memory is improved.
To solve the above problems, an aspect of the present invention provides a memory, including: the memory structure comprises a substrate, wherein a memory stack structure is formed on the surface of the substrate and comprises insulating layers and control gate structure layers which are alternately stacked; a common source contact through the storage stack structure; an isolation layer between the storage stack structure and the common source contact, the isolation layer comprising at least one dielectric layer capable of blocking F diffusion.
Optionally, the material of the dielectric layer includes at least one of silicon nitride or aluminum oxide.
Optionally, the thickness of the dielectric layer is 2nm to 10 nm.
Optionally, the isolation layer includes at least one stress layer adjacent to the dielectric layer, and the stress layer and the dielectric layer have stresses in opposite directions.
Optionally, the isolation layer includes a first stress layer and a second stress layer, and the dielectric layer is located between the first stress layer and the second stress layer.
Optionally, the material of the first stress layer and the second stress layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.
Optionally, the material of the common source contact includes tungsten.
Optionally, a portion of the isolation layer protrudes towards the storage stack structure and is in contact with the control gate structure layer.
Optionally, a source doped region is formed in the substrate, and the common source contact is connected to the source doped region.
Optionally, the memory is a 3D NAND memory.
In order to solve the above problem, the technical solution of the present invention further provides a method for forming a memory, including: providing a substrate; forming a stacked structure on the surface of the substrate, wherein the stacked structure comprises insulating layers and sacrificial layers which are alternately stacked; forming a gate line isolation trench penetrating the storage stack structure; removing the sacrificial layer between the adjacent insulating layers along the grid line isolation groove, and forming a control grid structure layer between the adjacent insulating layers; forming an isolation layer on the surface of the side wall of the grid line isolation groove, wherein the isolation layer at least comprises a dielectric layer capable of blocking F diffusion; and forming a common source contact part filling the grid line isolation groove.
Optionally, the material of the dielectric layer includes at least one of silicon nitride or aluminum oxide.
Optionally, the thickness of the dielectric layer is 2nm to 10 nm.
Optionally, the isolation layer includes at least one stress layer adjacent to the dielectric layer, and the stress layer and the dielectric layer have stresses in opposite directions.
Optionally, the isolation layer includes a first stress layer and a second stress layer, and the dielectric layer is located between the first stress layer and the second stress layer.
Optionally, the material of the first stress layer and the second stress layer includes at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.
Optionally, the reactant used in the process of forming the common source contact includes F element.
Optionally, the material of the common source contact includes tungsten, and the reactant used in forming the common source contact includes WF6。
Optionally, before forming the isolation layer, the method further includes etching back the control gate structure layer so that the side wall of the gate line isolation groove protrudes out of the side face of the control gate structure layer; and part of the isolation layer protrudes out of the side wall of the grid line separation groove and is in contact with the control grid structure layer.
According to the memory, the isolation layer is formed between the storage stack structure and the common source contact part, the isolation layer at least comprises the dielectric layer capable of blocking F diffusion, the isolation layer can be prevented from being damaged by residual F ions and/or F atoms in the common source contact part, and the isolation layer always has high electrical isolation characteristics.
Drawings
Fig. 1 to 5 are schematic structural diagrams illustrating a memory formation process according to an embodiment of the invention;
FIG. 6 is a diagram illustrating a memory structure according to an embodiment of the present invention;
fig. 7 to 8 are schematic structural diagrams illustrating a memory formation process according to an embodiment of the invention.
Detailed Description
The following describes in detail a specific embodiment of the memory and the forming method thereof according to the present invention with reference to the accompanying drawings. In a specific embodiment of the present invention, the memory is a 3D NAND memory.
Referring to fig. 1, a substrate 100 is provided, and a stack structure 110 is formed on a surface of the substrate 100.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The stack structure 110 includes an insulating layer 111 and a sacrificial layer 112 stacked on each other in a direction perpendicular to the surface of the substrate 100. In one embodiment, the material of the insulating layer 111 is silicon oxide, and the material of the sacrificial layer 112 is silicon nitride; in other embodiments, other suitable materials for the insulating layer 111 and the sacrificial layer 112 may be used. The stacked structure 110 may be formed by alternately depositing the insulating layer 111 and the sacrificial layer 112 on the surface of the substrate 100 in sequence by using a chemical vapor deposition process.
After the stacked structure 110 is formed, a trench hole structure penetrating through the stacked structure 110 to the surface of the substrate 100 is further formed, the trench hole structure includes a trench hole penetrating through the stacked structure 110, an epitaxial semiconductor layer 131 located on the surface of the substrate 100 at the bottom of the trench hole, a functional sidewall 132 covering the surface of the sidewall of the trench hole, a trench dielectric layer 133 filling the trench hole, and a conductive plug 134 located at the top of the trench dielectric layer 133 and connected to the functional sidewall 132. The sidewall of the channel hole structure is connected to the insulating layer 111 and the sacrificial layer 112.
Further comprising forming a capping layer 120 on top of the stacked structure 110 covering the stacked structure 110 and the channel hole structure. The capping layer 120 is made of silicon oxide or other mask material to protect the stack structure 110.
Referring to fig. 2, a gate line spacer 200 is formed to penetrate the memory stack structure 110.
The gate line spacer 200 penetrates the stacked structure 110 to the surface of the substrate 100. In a specific embodiment, a dry etching process may be used to etch the stacked structure 100 to the surface of the substrate 200, and the gate line spacer 200 is formed in the stacked structure 110. In this embodiment, the stack structure 110 is vertically etched by using a reactive plasma etching process to form the gate line spacing groove 200.
The sidewalls of the gate line spacer 200 expose the sidewalls of the insulating layer 111 and the sacrificial layer 112.
After the gate line spacer 200 is formed, a source doped region 201 is formed in the substrate 100 at the bottom of the gate line spacer 200 to serve as a common source between the memory strings of the memory.
Referring to fig. 3, the sacrificial layer 112 (see fig. 2) between the adjacent insulating layers 111 is removed along the sidewalls of the gate line trenches 200, and a control gate structure layer is formed between the adjacent insulating layers 111.
The sacrificial layer 112 may be removed using a wet etch process. In this specific embodiment, the material of the sacrificial layer 112 is silicon nitride, and the sacrificial layer 112 is etched by using a phosphoric acid solution.
Because the channel hole structure, the insulating layer 111 and the functional sidewall 132 of the channel hole structure are formed in the stacked structure 110, after the sacrificial layer 112 is removed, the channel hole structure can support the insulating layer 111, so that a gap is formed between adjacent insulating layers 111.
After removing the insulating layer 111, a control gate structure layer is formed in the gap.
The control gate structure layer comprises a gate dielectric layer 301 covering the inner wall surface of the gap and a gate layer 302 filling the gap. The gate dielectric layer 301 and the gate electrode layer 302 may be formed by an atomic layer deposition process, respectively. In a specific embodiment, the gate dielectric layer 301 is made of a dielectric material with a relatively high dielectric coefficient, such as silicon oxide, hafnium oxide, or zirconium oxide; the gate layer 302 is made of a conductive material, and includes at least one of polysilicon, tungsten, titanium nitride, gold, silver, or platinum.
The control gate structure layers and the insulating layers 111, which are alternately stacked, constitute a storage stack structure 300.
Referring to fig. 4, an isolation layer 401 is formed on the sidewall surface of the gate line trench 200, where the isolation layer 401 at least includes a dielectric layer capable of blocking F diffusion.
In this embodiment, the isolation layer 401 only includes a single dielectric layer capable of blocking F (fluorine) diffusion, and in the embodiment of the present invention, the F (fluorine) includes at least one of F ions or F atoms, and the F diffusion includes diffusion of at least one of F ions and F atoms. The dielectric layer is made of a material having a high dielectric coefficient, can be used as an electrical isolation layer, and cannot react or exchange atoms with F ions and/or F atoms, for example, cannot react with HF, so that the isolation performance is prevented from being reduced due to corrosion of HF.
In this embodiment, the material of the isolation layer 401 is silicon nitride. In other embodiments, the material of the isolation layer 401 may also be aluminum oxide or other dielectric materials.
In an embodiment of the present invention, the thickness of the isolation layer 401 may be 2nm to 10 nm. The thickness of the isolation layer 401 may be adjusted according to the dielectric coefficient of the material used, so that the isolation layer 401 has sufficient electrical isolation performance. The isolation layer 401 may be formed using an atomic layer deposition process so that a deposition thickness of the isolation layer 401 can be accurately controlled and the isolation layer 401 has high step coverage.
In other specific embodiments, the isolation layer 401 may further include two or more dielectric layers capable of blocking diffusion of F ions and/or F atoms, for example, the isolation layer 401 is a composite layer including a silicon nitride layer and an aluminum oxide layer. The dielectric layer material generally needs to have high chemical stability and compactness, and can avoid reacting with F atoms or ions, so as to prevent F from diffusing into the isolation layer 401.
Referring to fig. 5, a common source contact 500 is formed to fill the gate line spacer 200 (see fig. 4).
The bottom of the common source contact 500 is connected to the source doped region 201. The common source contact 500 is made of a conductive material, and the isolation layer 401 serves as an electrical isolation layer between the gate layer 302 and the common source contact 500 in the control gate structure layer, so as to avoid a short circuit between the common source contact 500 and the gate layer 302.
The common source contact 500 is formed using a chemical vapor deposition process or an atomic layer deposition process. The material of the common source contact 500 is usually W, and during deposition, WF is usually used6As a precursor reactant, F-containing by-products such as HF are produced during the deposition process. In the process of forming the common source contact, since the depth of the gate line spacer 200 is large, a hole or other defects may be generated in the common source contact 500, which may result in WF6And/or HF etc. remain inside the common source contact 500. In other embodiments, the common-source contact 500 may be made of other conductive materials, and during the formation of the common-source contact 500, other precursor gases containing F may be used, which may cause residual F atoms and/or F ions and/or F atoms in the common-source contact 500, and the F atoms and/or F ions and/or F atoms are prone to diffuse to the outside.
Since the isolation layer 401 includes at least one dielectric layer capable of blocking diffusion of F ions and/or F atoms, the dielectric layer can block diffusion of F atoms and/or F ions, and the isolation characteristic of the isolation layer 401 is maintained, so that a short circuit problem between the common source contact 500 and the gate layer 302 is avoided, and thus the performance of the formed memory is improved.
In other specific embodiments, the isolation layer may also have one less stress layer, and the stress direction of the stress layer is opposite to the stress direction of the dielectric layer.
Referring to fig. 6, in another embodiment of the present invention, an isolation layer between the common source contact 500 and the memory stack structure 300 includes a first stress layer 601, a second stress layer 602, and a dielectric layer 603 located between the first stress layer 601 and the second stress layer 602, wherein the dielectric layer 603 is capable of blocking diffusion of F ions and/or F atoms.
Compared with the isolation material such as silicon oxide commonly used in the prior art, the material of the dielectric layer 603 has higher stress, so as to avoid the problem that the structure of the memory is warped due to the stress of the dielectric layer 603 and further improve the isolation performance of the isolation layer. The first stress layer 601 and the second stress layer 602 are both made of insulating materials, and at least include one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. The magnitude and direction of the stress in the respective material layers can be adjusted by adjusting the formation processes of the first stress layer 601, the second stress layer 602, and the dielectric layer 603.
In this specific embodiment, the first stress layer 601 and the second stress layer 602 are both made of silicon oxide, and the dielectric layer 603 is made of silicon nitride.
In another embodiment, the materials of the first stress layer 601 and the second stress layer 602 are the same as the materials of the dielectric layer 603, and are both silicon nitride. However, the forming process parameters of the first stress layer 601 and the second stress layer 602 are different from the forming process parameters of the dielectric layer 603, so that the first stress layer 601, the second stress layer 602 and the dielectric layer 603 have different densities and stresses.
In other specific embodiments, the materials of the first stress layer 601 and the second stress layer 602 may be the same or different, and each of the materials includes at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.
Fig. 7 to 8 are schematic structural diagrams illustrating a memory formation process according to another embodiment of the invention.
Referring to fig. 7, on the basis of the structure of fig. 3, the control gate structure layer is etched back to form an opening 701. The opening 701 serves as a part of the gate line spacer 200, so that the sidewall of the gate line spacer 200 protrudes from the side surface of the control gate structure layer.
Specifically, in this embodiment, the gate layer 302 in the control gate structure layer is etched back to form the opening 701. The depth of the opening 701 may be 10nm to 30 nm. The gate layer 302 may be etched back using a wet etch process.
Referring to fig. 8, an isolation layer 800 is formed on the sidewall of the gate line spacer 200 and the opening 701, and the common source contact 801 is filled in the gate line spacer 200.
Part of the isolation layer 800 is filled in the opening 701, and part of the isolation layer 800 protrudes out of the side wall of the gate line spacer and contacts with the control gate structure layer, so that the thickness of the isolation layer 800 between the common source contact portion 801 and the gate layer 302 is larger, and the electrical isolation performance of the common source contact portion 801 and the gate layer 302 can be improved.
The embodiment of the invention also provides a memory formed by adopting the method. The memory is a 3DNAND memory.
Fig. 5 is a schematic structural diagram of a memory according to an embodiment of the invention.
The memory includes: the memory structure comprises a substrate 100, wherein a storage stack structure 300 is formed on the surface of the substrate 100, and the storage stack structure 300 comprises insulating layers 111 and control gate structure layers which are alternately stacked; a common source contact 500 through the memory stack structure; an isolation layer 401 located between the storage stack structure 300 and the common source contact 500, wherein the isolation layer 401 comprises at least one dielectric layer capable of blocking diffusion of F ions and/or F atoms.
The substrate 100 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI, a GOI, or the like; according to the actual requirements of the device, a suitable semiconductor material may be selected as the substrate 100, which is not limited herein. In this embodiment, the substrate 100 is a single crystal silicon wafer.
The insulating layer 111 is made of silicon oxide, and the control gate structure layer includes a gate dielectric layer 301 and a gate layer 302. The gate dielectric layer 301 is made of dielectric materials with higher dielectric coefficients, such as silicon oxide, hafnium oxide, zirconium oxide and the like; the gate layer 302 is made of a conductive material, and includes at least one of polysilicon, tungsten, titanium nitride, gold, silver, or platinum.
A trench hole structure is further formed in the storage stacked structure 300, and the trench hole structure includes a trench hole penetrating through the storage stacked structure 300, an epitaxial semiconductor layer 131 on the surface of the substrate 100 at the bottom of the trench hole, a functional sidewall 132 covering the surface of the sidewall of the trench hole, a trench dielectric layer 133 filling the trench hole, and a conductive plug 134 located at the top of the trench dielectric layer 133 and connected to the functional sidewall 132. The sidewall of the channel hole structure is connected with the insulating layer 111 and the control gate structure layer.
A capping layer 120 is also included overlying the storage stack structure 300 and the trench hole structure. The capping layer 300 is made of silicon oxide or other mask material, and is used for protecting the memory stack structure 300.
In this embodiment, the isolation layer 401 comprises only a single layer of dielectric layer capable of blocking diffusion of F ions and/or F atoms. The dielectric layer is made of a material having a high dielectric coefficient, can be used as an electrical isolation layer, and cannot react or exchange atoms with F ions and/or F atoms, for example, cannot react with HF, so that the isolation performance is prevented from being reduced due to corrosion of HF.
In this embodiment, the material of the isolation layer 401 is silicon nitride. In other embodiments, the material of the isolation layer 401 may also be aluminum oxide or other dielectric materials.
In an embodiment of the present invention, the thickness of the isolation layer 401 may be 2nm to 10 nm. The thickness of the isolation layer 401 may be adjusted according to the dielectric coefficient of the material used, so that the isolation layer 401 has sufficient electrical isolation performance.
In other specific embodiments, the isolation layer 401 may further include two or more dielectric layers capable of blocking diffusion of F ions and/or F atoms, for example, the isolation layer 401 is a composite layer including a silicon nitride layer and an aluminum oxide layer. The dielectric layer material generally needs to have high chemical stability and compactness, and can avoid reacting with F atoms or ions, so as to prevent F from diffusing into the isolation layer 401.
The substrate 100 has a source doped region 201 therein, and the bottom of the common source contact 500 is connected to the source doped region 201. The common source contact 500 is made of a conductive material, and the isolation layer 401 serves as an electrical isolation layer between the gate layer 302 and the common source contact 500 in the control gate structure layer, so as to avoid a short circuit between the common source contact 500 and the gate layer 302.
The common-source contact 500 is formed by using a precursor reactant containing F, which tends to leave F atoms and/or F atoms in the common-source contact 500. In one embodiment, the material of the common-source contact 500 comprises W, and the precursor reactant is WF6. The isolation layer 401 at least includes a dielectric layer capable of blocking diffusion of F ions and/or F atoms, so that the dielectric layer can block diffusion of F atoms and/or F ions, and the isolation characteristic of the isolation layer 401 is maintained, thereby avoiding a short circuit problem between the common source contact 500 and the gate layer 302, and improving performance of the formed memory.
In other specific embodiments, the isolation layer may also have one less stress layer, and the stress direction of the stress layer is opposite to the stress direction of the dielectric layer.
Fig. 6 is a schematic structural diagram of a memory according to another embodiment of the present invention.
In this embodiment, the isolation layer between the storage stack structure 300 and the common source contact 500 includes a first stress layer 601, a second stress layer 602, and a dielectric layer 603 located between the first stress layer 601 and the second stress layer 602, wherein the dielectric layer 603 is capable of blocking diffusion of F ions and/or F atoms.
Compared with the isolation material such as silicon oxide commonly used in the prior art, the material of the dielectric layer 603 has higher stress, so as to avoid the problem that the structure of the memory is warped due to the stress of the dielectric layer 603 and further improve the isolation performance of the isolation layer. The first stress layer 601 and the second stress layer 602 are both made of insulating materials, and at least include one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. The magnitude and direction of the stress in the respective material layers can be adjusted by adjusting the formation processes of the first stress layer 601, the second stress layer 602, and the dielectric layer 603.
In this specific embodiment, the first stress layer 601 and the second stress layer 602 are both made of silicon oxide, and the dielectric layer 603 is made of silicon nitride.
In another embodiment, the first stress layer 601 and the second stress layer 602 are made of the same material as the dielectric layer 603, and are made of silicon nitride, but have different densities and stresses.
In other specific embodiments, the materials of the first stress layer 601 and the second stress layer 602 may be the same or different, and each of the materials includes at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.
Please refer to fig. 8, which is a schematic structural diagram of a memory according to another embodiment of the present invention.
In this embodiment, an isolation layer 800 is formed between the memory stack structure 300 and the common source contact 801. And the distance between the sidewall of the gate layer 302 and the common source contact portion 801 is greater than the distance between the insulating layer 111 and the common source contact portion 801, so that the isolation layer 800 is partially located between the adjacent insulating layers 111, protrudes toward the storage stack structure, and is in contact with the control gate structure layer.
The thickness of the isolation layer 800 between the common source contact 801 and the gate layer 302 is large, which can improve the electrical isolation performance between the common source contact 801 and the gate layer 302.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (15)

1. A memory, comprising:
the memory structure comprises a substrate, wherein a memory stack structure is formed on the surface of the substrate and comprises insulating layers and control gate structure layers which are alternately stacked;
a common source contact through the storage stack structure;
the isolation layer is positioned between the storage stack structure and the common source contact part and at least comprises a dielectric layer capable of blocking F diffusion, the isolation layer further comprises a first stress layer and a second stress layer, the dielectric layer is positioned between the first stress layer and the second stress layer, and the stress directions of the first stress layer and the second stress layer are opposite to the stress direction of the dielectric layer.
2. The memory of claim 1, wherein the material of the dielectric layer comprises at least one of silicon nitride or aluminum oxide.
3. The memory of claim 1, wherein the dielectric layer has a thickness of 2nm to 10 nm.
4. The memory of claim 1, wherein the isolation layer comprises at least one stress layer adjacent to the dielectric layer, the stress layer having an opposite direction stress from the dielectric layer.
5. The memory of claim 1, wherein a material of the common source contact comprises tungsten.
6. The memory of claim 1, wherein a portion of the isolation layer protrudes toward the storage stack structure and contacts the control gate structure layer.
7. The memory of claim 1, wherein a source doped region is formed within the substrate, and wherein the common source contact is connected to the source doped region.
8. The memory of claim 1, wherein the memory is a 3D NAND memory.
9. A method for forming a memory, comprising:
providing a substrate;
forming a stacked structure on the surface of the substrate, wherein the stacked structure comprises insulating layers and sacrificial layers which are alternately stacked;
forming a gate line isolation trench penetrating the storage stack structure;
removing the sacrificial layer between the adjacent insulating layers along the grid line isolation groove, and forming a control grid structure layer between the adjacent insulating layers;
forming an isolation layer on the surface of the side wall of the grid line isolation groove, wherein the isolation layer at least comprises a dielectric layer capable of blocking F diffusion, and further comprises a first stress layer and a second stress layer, the dielectric layer is positioned between the first stress layer and the second stress layer, and the stress directions of the first stress layer and the second stress layer are opposite to the stress direction of the dielectric layer;
and forming a common source contact part filling the grid line isolation groove.
10. The method of claim 9, wherein the material of the dielectric layer comprises at least one of silicon nitride or aluminum oxide.
11. The method of claim 9, wherein the dielectric layer has a thickness of 2nm to 10 nm.
12. The method of claim 9, wherein the material of the first stress layer and the second stress layer comprises at least one of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride.
13. The method as claimed in claim 9, wherein the reactant used in forming the common source contact includes F element.
14. The method of claim 13, wherein the common source contact comprises tungsten and the reactant used in forming the common source contact comprises WF6。
15. The method of claim 9, further comprising etching back the control gate structure layer before forming the isolation layer, such that sidewalls of the gate line trenches protrude from sides of the control gate structure layer; and part of the isolation layer protrudes out of the side wall of the grid line separation groove and is in contact with the control grid structure layer.
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