CN109411468B - Silicon controlled electrostatic protector - Google Patents
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- CN109411468B CN109411468B CN201811253429.6A CN201811253429A CN109411468B CN 109411468 B CN109411468 B CN 109411468B CN 201811253429 A CN201811253429 A CN 201811253429A CN 109411468 B CN109411468 B CN 109411468B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 230000001012 protector Effects 0.000 title description 2
- 238000002347 injection Methods 0.000 claims abstract description 117
- 239000007924 injection Substances 0.000 claims abstract description 117
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007943 implant Substances 0.000 claims description 45
- 238000002513 implantation Methods 0.000 claims description 42
- 230000003071 parasitic effect Effects 0.000 claims description 39
- 230000010354 integration Effects 0.000 abstract description 5
- 238000012423 maintenance Methods 0.000 abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 2
- 150000004706 metal oxides Chemical class 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 7
- 230000001960 triggered effect Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000740 bleeding effect Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thyristors (AREA)
Abstract
The invention provides a silicon controlled electrostatic protection device which comprises a substrate, a buried oxide layer, an N well and a P well, wherein a first P + injection region, a first polysilicon gate, a second P + injection region and a fourth N + injection region are arranged in the N well, a first N + injection region, a second polysilicon gate, a second N + injection region and a fourth P + injection region are arranged in the P well, the third P + injection region and the third N + injection region are bridged at the junction between the N well and the P well, the first P + injection region is connected with an anode, the first N + injection region is connected with a cathode, the first P + injection region, the first polysilicon gate, the second P + injection region and the N well form a PMOS (P-channel metal oxide semiconductor) tube, and the first N + injection region, the second polysilicon gate, the second N + injection region and the P well form an NMOS (N-channel metal oxide semiconductor) tube. The invention has the advantages of low trigger voltage, high maintenance voltage, simple structure, easy integration, high robustness and the like, and is suitable for electrostatic protection of devices and circuits.
Description
Technical Field
The invention relates to the technical field of integrated circuit electrostatic protection, in particular to a silicon controlled electrostatic protection device.
Background
With the development of moore's law, the integration level of the chip is continuously improved, and the power consumption and performance are greatly improved. However, as bulk silicon technology has evolved to 28nm, technology complexity and manufacturing costs have increased dramatically, and fully depleted silicon-on-insulator (FDSOI) has come into play. Under the same technical node, the FDSOI technology can effectively reduce the manufacturing process, reduce the power consumption of a chip, improve the yield of products and has stronger radiation resistance. Due to the advantages of price, power consumption, performance and the like, the FDSOI gradually becomes a mainstream technology in the application of the internet of things and the like.
Electrostatic Discharge (ESD) is the leading cause of integrated circuit failure. Because the FDSOI has the characteristic of full-medium isolation, when the device is bombarded by static electricity, the static current cannot be discharged to the ground end through the buried oxide layer, so the static protection capability of the FDSOI device is much poorer than that of a bulk silicon device. Generally, an SCR path is implemented by injecting N + impurities into a P-well and P + impurities into an N-well, using lateral parasitic PNP and lateral parasitic NPN structures.
However, the bulk silicon of the FDSOI device is thin, the N + implantation region and the P + implantation region both extend into the surface of the buried oxide layer, and the formed positive feedback structure has a small current amplification factor. The trigger point of the traditional FDSOI electrostatic protection device is positioned at the junction of a P well and an N well, and has higher trigger voltage, when the trigger voltage exceeds the source-drain breakdown voltage of the device, the device can be burnt, and the current can not be effectively discharged.
Disclosure of Invention
In view of the above situation, the present invention is directed to solve the problem of the conventional electrostatic protection device that the device is burned out due to a high trigger voltage.
The invention provides a silicon controlled electrostatic protection device, which comprises a substrate, a buried oxide layer arranged in the substrate, an N well and a P well arranged in the buried oxide layer, a first P + injection region, a first polysilicon gate, a second P + injection region and a fourth N + injection region are arranged in the N well, a first N + injection region, a second polysilicon gate, a second N + injection region and a fourth P + injection region are arranged in the P well, the third P + injection region and the third N + injection region are bridged at the junction between the N well and the P well, the first P + injection region is connected with an anode, the first N + injection region is connected with a cathode, the first P + injection region, the first polysilicon gate, the second P + injection region and the N well form a PMOS tube, the first N + injection region, the second polysilicon gate, the second N + injection region and the P well form an NMOS tube.
When positive pulse appears on the anode, avalanche breakdown occurs at the junction of the N trap-P + injection region and the junction of the N + injection region-P trap, the generated holes move to the cathode with lower potential, and the electrons move to the anode with higher potential; meanwhile, the embedded NMOS tube is triggered to inject hole current into the P well, so that the potential of the P well is effectively improved; the embedded PMOS tube is triggered to inject electron current into the N trap, so that the potential of the N trap is effectively reduced. Because three current leakage paths from the anode to the cathode are provided, the leakage current intensity is greatly increased, the secondary failure current is improved, and the better ESD robustness can be maintained. Compared with the conventional FDSOI silicon controlled rectifier device structure, the NMOS tube and the PMOS tube are embedded on the SCR path, so that the static electricity discharge efficiency is improved, meanwhile, a plurality of SCR paths are added, the current discharge speed is improved, and the FDSOI silicon controlled rectifier device structure has the advantages of low trigger voltage, high maintenance voltage, easiness in integration, high robustness and the like.
In addition, the silicon controlled electrostatic protection device provided by the invention can also have the following additional technical characteristics:
the silicon controlled electrostatic protection device, wherein the first P + injection region, the N well and the second P + injection region constitute a first PNP type transistor, and the N well, the second P + injection region, the third P + injection region, the fourth P + injection region, the P well and the first N + injection region constitute a first NPN type transistor.
The silicon controlled electrostatic protection device comprises a first N + injection region, an N trap, a second P + injection region, a third P + injection region, a fourth P + injection region and a P trap, wherein the first N + injection region and the N trap form a first forward diode, a parasitic resistor in the N trap forms a first N trap parasitic resistor, and the second P + injection region, the third P + injection region, the fourth P + injection region and the parasitic resistor in the P trap form a first P trap parasitic resistor.
The silicon controlled electrostatic protection device, wherein the first P + injection region, the N well, the fourth N + injection region, the third N + injection region, the second N + injection region, and the P well form a second PNP type transistor, and the second N + injection region, the P well, and the first N + injection region form a second NPN type transistor.
The silicon controlled electrostatic protection device is characterized in that the first N + injection region and the P well form a second forward diode, parasitic resistors in the N well, the fourth N + injection region, the third N + injection region and the second N + injection region form a second N well parasitic resistor, and parasitic resistors in the P well form a second P well parasitic resistor.
The silicon controlled electrostatic protection device is characterized in that the first P + injection region, the N well and the P well form a third PNP type transistor, and the N well, the P well and the first N + injection region form a third NPN type transistor.
The silicon controlled electrostatic protection device is characterized in that a parasitic resistor in the N trap forms a third N trap parasitic resistor, and a parasitic resistor in the P trap forms a third P trap parasitic resistor.
The silicon controlled electrostatic protection device comprises three electrostatic discharge paths from an anode to a cathode, wherein the first path is the first P + injection region, the N well, the second P + injection region, the third P + injection region, the fourth P injection region, the P well and the first N + injection region, the second path is the first P + injection region, the N well, the fourth N + injection region, the third N + injection region, the second N + injection region, the P well and the first N + injection region, and the third path is the first P + injection region, the N well, the P well and the first N + injection region.
The silicon controlled electrostatic protection device, wherein the first P + injection region, the N well, the second P + injection region, the third P + injection region, the fourth P + injection region and the P well form a first PNPN type silicon controlled structure, and the first P + injection region, the N well, the fourth N + injection region, the third N + injection region, the second N + injection region, the P well and the first N + injection region form a second PNPN type silicon controlled structure.
The silicon controlled electrostatic protection device is characterized in that the first P + injection region, the N well, the P well and the first N + injection region form a third PNPN type silicon controlled structure.
Drawings
FIG. 1 is a cross-sectional view of a conventional FDSOI SCR electrostatic protection device;
FIG. 2 is a layout of the FDSOI SCR electrostatic protection device according to the present invention;
FIG. 3 is a cross-sectional view of the SCR ESD protection device of FIG. 2 taken along line A-A' of the present invention;
FIG. 4 is a cross-sectional view of the SCR ESD protection device shown in FIG. 2 taken along line B-B' of the present invention;
FIG. 5 is a cross-sectional view of the SCR ESD protection device of FIG. 2 taken along the line C-C' according to the present invention;
FIG. 6 is an equivalent circuit diagram of a first bleed path of the present invention;
FIG. 7 is an equivalent circuit diagram of a second bleed path of the present invention;
fig. 8 is an equivalent circuit diagram of a third bleed circuit of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must be in a particular orientation, constructed or operated in a particular manner, and is not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the prior art, the bulk silicon of the FDSOI device is very thin, an N + injection region and a P + injection region both extend into the surface of a buried oxide layer, and a formed positive feedback structure has smaller current amplification factor. The trigger point of the traditional FDSOI electrostatic protection device is positioned at the junction of a P well and an N well, and has higher trigger voltage, when the trigger voltage exceeds the source-drain breakdown voltage of the device, the device can be burnt, and the current can not be effectively discharged.
In order to solve the technical problem, the present invention provides a silicon controlled electrostatic protection device, which is referred to fig. 1 to 8, and the silicon controlled electrostatic protection device provided by the present invention includes a substrate 01, a buried oxide layer 02 disposed in the substrate 01, an N well 11 disposed in the buried oxide layer 02, and a P well 12. It is to be noted that the substrate 01 is a P-type silicon substrate.
Referring to fig. 2 to 5, specifically, the N-well 11 is sequentially provided with: a first P + implant region 13, a first polysilicon gate 14, a second P + implant region 15, and a fourth N + implant region 22. The P-well 12 is provided with: a second N + implant region 20, a second polysilicon gate 19, a first N + implant region 18, and a fourth P + implant region 17. The third P + implantation region 16 and the third N + implantation region 21 bridge the boundary position between the P well 12 and the N well 11, the first P + implantation region 13 is connected to the anode, and the first N + implantation region 18 is connected to the cathode.
For the silicon controlled electrostatic protection device provided by the invention, three electrostatic discharge paths are respectively shown in a sectional view along the tangent line A-A ', a sectional view along the tangent line B-B ' and a sectional view along the tangent line C-C '. Fig. 6, 7 and 8 are equivalent circuit diagrams corresponding to each other.
Specifically, fig. 6 is an equivalent circuit of the first bleeder circuit, and the first P + injection region 13, the N well 11 and the second P + injection region 15 form a first PNP transistor Qp1The N well 11, the second P + implantation region 15, the third P + implantation region 16, the fourth P + implantation region 17, the P well 12, and the first N + implantation region 18 constitute a first NPN transistor Qn 1. The first P + implantation region 13, the N well 11, the second P + implantation region 15, and the first polysilicon gate 14 form a PMOS transistor Mp.
Meanwhile, the P-well 12 and the first N + implantation region 18 form a forward diode D2. In the above-mentioned N wellThe parasitic resistance of (2) constitutes a first N-well parasitic resistance Rnw1(ii) a The parasitic resistances of the second P + implantation region 15, the third P + implantation region 16, the fourth P + implantation region 17 and the P-well 12 form a first P-well parasitic resistance Rpw1。
For a first bleeding path, the corresponding paths are as follows in sequence: a first P + implantation region 13, an N well 11, a second P + implantation region 15, a third P + implantation region 16, a fourth P implantation region 17, a P well 12, and a first N + implantation region 18.
Referring to fig. 7, fig. 7 is an equivalent circuit of the second bleed path, in which the first P + injection region 13, the N well 11, the fourth N + injection region 22, the third N + injection region 21, the second N + injection region 20 and the P well 12 form a second PNP transistor Qp2, and the second N + injection region 20, the P well 12 and the first N + injection region 18 form a second NPN transistor Qn 2. The first N + implant region 18, the second polysilicon gate 19, the second N + implant region 20 and the P-well 12 form an NMOS transistor Mn. The first P + implant region 13 and the N-well 11 constitute a forward diode D1. Parasitic resistances in the N-well 11, the fourth N + implantation region 22, the third N + implantation region 21 and the second N + implantation region 20 constitute a second N-well parasitic resistance Rnw2, and a parasitic resistance of the P-well 12 constitutes a second P-well parasitic resistance Rpw 2.
For the second bleeding path, the corresponding paths are as follows in sequence: the first P + implantation region 13, the N well 11, the fourth N + implantation region 22, the third N + implantation region 21, the second N + implantation region 20, the P well 12, and the first N + implantation region 18.
Referring to fig. 8, fig. 8 is an equivalent circuit of the third bleeder circuit, in which the first P + injection region 13, the N well 11 and the P well 12 form a third PNP transistor Qp 3. The N well 11, the P well 12 and the first N + implantation region 18 form a third NPN transistor Qn 3. The parasitic resistance in the N-well 11 constitutes a third N-type parasitic resistance Rnw3, and the parasitic resistance of the P-well 12 constitutes a third P-type parasitic resistance Rpw 3.
For the third bleeding path, the corresponding paths are as follows in sequence: the first P + implantation region 13, the N-well 11, the P-well 12, and the first N + implantation region 18.
In practical application, when positive pulse occurs to the anode, avalanche breakdown occurs to the N trap-P + junction and the N + -P trap junction, a generated hole moves to the cathode with lower potential, an electron moves to the anode with higher potential, and meanwhile, an embedded NMOS tube is triggered to inject hole current into the P trap 12, so that the potential of the P trap is effectively improved; the embedded PMOS tube can be triggered to inject electron current into the N well 11, so that the potential of the N well is effectively reduced.
Taking the first bleed path as an example, the holes generated by avalanche breakdown generate a voltage drop across the first P-type parasitic resistance Rpw1, which also results in an increase in the potential in the P-well 12. When the potential rises to be greater than the turn-on voltage, the first NPN transistor Qn1 is induced to turn on. The electrons generated by the avalanche breakdown cause a decrease in the potential of the N-well 11, inducing the first PNP transistor Qp1 to turn on. Qn1 and Qp1 form a positive feedback loop so that the bleed current is continuously increased. Because three current leakage paths from the anode to the cathode are provided, the leakage current intensity is greatly increased, the secondary failure current is improved, and the better ESD robustness can be maintained. Compared with the conventional FDSOI silicon controlled rectifier device structure, the NMOS and the PMOS are embedded on the SCR path, so that the electrostatic discharge efficiency is improved, meanwhile, a plurality of SCR paths are added, the current discharge speed is improved, and the FDSOI silicon controlled rectifier device structure has the advantages of low trigger voltage, high maintenance voltage, easiness in integration, high robustness and the like, is simple in structure, does not increase a mask and has generality.
The first P + injection region 13, the N well 11, the second P + injection region 15, the third P + injection region 16, the fourth P + injection region 17 and the P well 12 constitute a first PNPN type thyristor structure, and the first P + injection region 13, the N well 11, the fourth N + injection region 22, the third N + injection region 21, the second N + injection region 20, the P well 12 and the first N + injection region 18 constitute a second PNPN type thyristor structure. The first P + injection region 13, the N well 11, the P well 12, and the first N + injection region 18 constitute a third PNPN type thyristor structure.
When positive pulse appears on the anode, avalanche breakdown occurs at the junction of the N trap-P + injection region and the junction of the N + injection region-P trap, the generated holes move to the cathode with lower potential, and the electrons move to the anode with higher potential; meanwhile, the embedded NMOS tube is triggered to inject hole current into the P well, so that the potential of the P well is effectively improved; the embedded PMOS tube is triggered to inject electron current into the N trap, so that the potential of the N trap is effectively reduced. Because three current leakage paths from the anode to the cathode are provided, the leakage current intensity is greatly increased, the secondary failure current is improved, and the better ESD robustness can be maintained. Compared with the conventional FDSOI silicon controlled rectifier device structure, the NMOS tube and the PMOS tube are embedded on the SCR path, so that the static electricity discharge efficiency is improved, meanwhile, a plurality of SCR paths are added, the current discharge speed is improved, and the FDSOI silicon controlled rectifier device structure has the advantages of low trigger voltage, high maintenance voltage, easiness in integration, high robustness and the like.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention, which are described in more detail and detail, but are not to be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. The silicon controlled electrostatic protection device is characterized by comprising a substrate, a buried oxide layer arranged in the substrate, an N well and a P well which are arranged in the buried oxide layer, a first P + injection region, a first polysilicon gate, a second P + injection region and a fourth N + injection region are arranged in the N well, a first N + injection region, a second polysilicon gate, a second N + injection region and a fourth P + injection region are arranged in the P well, the third P + injection region and the third N + injection region are bridged at the junction between the N well and the P well, the first P + injection region is connected with an anode, the first N + injection region is connected with a cathode, the first P + injection region, the first polysilicon gate, the second P + injection region and the N well form a PMOS tube, the first N + injection region, the second polysilicon gate, the second N + injection region and the P well form an NMOS tube.
2. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, and the second P + implant region form a first PNP type transistor, and the N-well, the second P + implant region, the third P + implant region, the fourth P + implant region, the P-well, and the first N + implant region form a first NPN type transistor.
3. The scr electrostatic protection device of claim 2, wherein the first P + implant region and the N-well form a first forward diode, wherein a parasitic resistance in the N-well forms a first N-well parasitic resistance, and wherein the second P + implant region, the third P + implant region, the fourth P + implant region, and a parasitic resistance in the P-well form a first P-well parasitic resistance.
4. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, the fourth N + implant region, the third N + implant region, the second N + implant region, and the P-well form a second PNP transistor, and the second N + implant region, the P-well, and the first N + implant region form a second NPN transistor.
5. The SCR electrostatic protection device of claim 4, wherein said first N + implant region and said P-well constitute a second forward diode, and wherein parasitic resistances in said N-well, said fourth N + implant region, said third N + implant region, and said second N + implant region constitute a second N-well parasitic resistance, and wherein parasitic resistances in said P-well constitute a second P-well parasitic resistance.
6. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, and the P-well form a third PNP transistor, and the N-well, the P-well, and the first N + implant region form a third NPN transistor.
7. The SCR electrostatic protection device of claim 6, wherein said parasitic resistance in said N-well constitutes a third N-well parasitic resistance and said parasitic resistance in said P-well constitutes a third P-well parasitic resistance.
8. The scr electrostatic protection device of claim 1, wherein three electrostatic discharge paths exist from an anode to a cathode, a first path being the first P + implant region, the N-well, the second P + implant region, the third P + implant region, the fourth P implant region, the P-well, and the first N + implant region, a second path being the first P + implant region, the N-well, the fourth N + implant region, the third N + implant region, the second N + implant region, the P-well, and the first N + implant region, and a third path being the first P + implant region, the N-well, the P-well, and the first N + implant region.
9. The silicon controlled electrostatic protection device according to claim 1, wherein the first P + implantation region, the N well, the second P + implantation region, the third P + implantation region, the fourth P + implantation region, the P well, and the first N + implantation region constitute a first PNPN type silicon controlled structure, and the first P + implantation region, the N well, the fourth N + implantation region, the third N + implantation region, the second N + implantation region, the P well, and the first N + implantation region constitute a second PNPN type silicon controlled structure.
10. The scr electrostatic protection device of claim 1, wherein the first P + implant region, the N-well, the P-well, and the first N + implant region form a third PNPN type scr structure.
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| CN111725204B (en) * | 2019-07-18 | 2023-05-26 | 中国科学院上海微系统与信息技术研究所 | ESD protection device with bidirectional SCR structure |
| CN111725206B (en) * | 2019-07-29 | 2023-11-21 | 中国科学院上海微系统与信息技术研究所 | PMOS triggered SCR device, manufacturing method of SCR device and SCR electrostatic protection circuit |
| CN111627902B (en) * | 2020-06-04 | 2022-06-24 | 电子科技大学 | Programmable overvoltage protection device with SGT and thyristor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1337744A (en) * | 2000-08-08 | 2002-02-27 | 三菱电机株式会社 | Semiconductor device |
| CN108336082A (en) * | 2017-01-18 | 2018-07-27 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection devices and electrostatic discharge protective circuit |
| CN108493186A (en) * | 2018-02-28 | 2018-09-04 | 南京邮电大学 | A kind of PMOS triggers the SCR type ESD protection devices of simultaneously pincers drawing builtin voltage |
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| US9368486B2 (en) * | 2014-02-17 | 2016-06-14 | Allegro Microsystems, Llc | Direct connected silicon controlled rectifier (SCR) having internal trigger |
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| CN1337744A (en) * | 2000-08-08 | 2002-02-27 | 三菱电机株式会社 | Semiconductor device |
| CN108336082A (en) * | 2017-01-18 | 2018-07-27 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection devices and electrostatic discharge protective circuit |
| CN108493186A (en) * | 2018-02-28 | 2018-09-04 | 南京邮电大学 | A kind of PMOS triggers the SCR type ESD protection devices of simultaneously pincers drawing builtin voltage |
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