CN109411423B - 半导体封装件及包括半导体封装件的电子装置 - Google Patents
半导体封装件及包括半导体封装件的电子装置 Download PDFInfo
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明提供一种半导体封装件及包括半导体封装件的电子装置。所述半导体封装件包括:基板,包括天线;发热元件,设置在所述基板的第一表面上并且连接到所述天线;散热部,结合到所述发热元件;以及信号传输部,设置在所述基板的所述第一表面上并且被构造为将所述基板电连接到主基板。所述散热部可包括连接到所述发热元件的传热部以及将所述传热部和所述主基板彼此连接的散热端子。
Description
本申请要求于2017年8月16日在韩国知识产权局提交的第10-2017-0103390号韩国专利申请的优先权和权益,所述韩国专利申请的全部公开内容出于所有目的通过引用被包含于此。
技术领域
以下描述涉及一种半导体封装件及包括半导体封装件的电子装置。
背景技术
为了以高速处理高质量、高容量数据,增大了半导体封装件的频带。例如,在用于无线通信的半导体封装件的情况下,考虑使用27GHz或更大的毫米波带的技术。
由于在毫米波带中频率的波长减小至毫米,因此当使用传统的半导体封装结构时性能可能会劣化。
因此,需要一种在超高频带下有效地工作的半导体封装件。
发明内容
提供本发明内容以按照简化形式介绍选择的构思,以下在具体实施方式中进一步描述所述构思。本发明内容并不意在确定要求保护的主题的关键特征或必要特征,本发明内容也不意在用于帮助确定要求保护的主题的范围。
在一个总体方面,一种半导体封装件包括:基板,包括天线;发热元件,设置在所述基板的第一表面上并且连接到所述天线;散热部,结合到所述发热元件;以及信号传输部,设置在所述基板的所述第一表面上并且将所述基板电连接到主基板,其中,所述散热部包括连接到所述发热元件的传热部以及将所述传热部和所述主基板彼此连接的散热端子。
所述传热部可具有平板形状或块形状并且可包括金属。
所述半导体封装件还可包括设置在所述信号传输部的一侧上并且连接到所述主基板的连接端子,其中,所述散热端子可包括与所述连接端子的材料相同的材料,并且具有与所述连接端子的尺寸大体相同的尺寸。
所述半导体封装件还可包括大体包围所述信号传输部和所述发热元件的密封部。
所述传热部可嵌在所述密封部中,并且所述散热端子可穿过所述密封部并且可连接到所述传热部。
所述传热部可包括一个或更多个结合槽,并且所述密封部的一部分可设置在所述一个或更多个结合槽中。
所述一个或更多个结合槽可包括穿过所述传热部的孔,并且所述一个或更多个结合槽可被设置为分布在所述传热部的区域上。
所述传热部可包括台阶,所述台阶设置在所述传热部的结合到所述发热元件的第一表面和结合到所述散热端子的第二表面中的至少一个表面的边缘中。
所述传热部的一部分可暴露于所述密封部的外部,并且所述散热端子可连接到所述传热部的暴露于所述密封部的外部的所述一部分。
所述传热部可包括外壳,所述外壳包括内部空间,并且所述发热元件可设置在所述外壳的所述内部空间中。
所述外壳可包括一个或更多个通孔,并且所述密封部可通过所述通孔设置在所述外壳的所述内部空间中。
所述信号传输部可包括:连接导体,包括连接到所述基板的一端和通过连接端子连接到所述主基板的另一端;以及绝缘部,包围所述连接导体。
所述信号传输部可包括在所述密封部中熔化并且固化的焊球。
所述半导体封装件还可包括插设在所述发热元件和所述传热部之间的结合层。
在一个总体方面,一种电子装置包括:半导体封装件,包括基板和散热部,所述基板包括设置在所述基板的一个表面上的发热元件和信号传输部,所述散热部结合到所述发热元件;以及主基板,其中,所述半导体封装件设置在所述主基板的第一表面上,其中,所述散热部包括连接到所述发热元件的传热部以及将所述传热部和所述主基板彼此连接的散热端子,并且所述主基板包括连接到所述散热端子的一个或更多个散热过孔。
所述电子装置还可包括结合到所述主基板的第二表面的散热构件,其中,所述散热过孔可穿过所述主基板并且可连接到所述散热构件。
所述电子装置还可包括设置在所述基板上的天线。
所述天线可发送和/或接收毫米波长带的无线电信号。
通过下面的具体实施方式、附图以及权利要求,其它特征和方面将显而易见。
附图说明
图1是根据实施例的半导体封装件的截面图。
图2是沿着图1的线I-I’截取的截面图。
图3是图2中示出的信号传输部的变型示例的示图。
图4是用于制造图1中示出的半导体封装件的方法的示图。
图5是图2中示出的传热部的变型示例的示图。
图6至图9是根据实施例的半导体封装件中的每个的截面图。
图10是根据实施例的电子装置的示图。
在整个附图和具体实施方式中,相同的标号指示相同的元件。附图可不按照比例绘制,为了清楚、说明以及方便起见,可夸大附图中元件的相对尺寸、比例和描绘。
具体实施方式
提供以下具体实施方式,以帮助读者获得对在此描述的方法、设备和/或系统的全面理解。然而,在理解了本申请的公开内容之后,在此描述的方法、设备和/或系统的各种改变、修改及等同物将是显而易见的。例如,在此描述的操作的顺序仅仅是示例,且不限于在此阐述的示例,而是除了必须按照特定顺序发生的操作之外,可做出在理解了本申请的公开内容之后将是显而易见的改变。此外,为了增加清楚性和简洁性,可省略本领域中已知的特征的描述。
在此描述的特征可按照不同的形式实施,并且将不被解释为局限于在此描述的示例。更确切地说,已经提供在此描述的示例,仅为了示出在理解了本申请的公开内容之后将是显而易见的实现在此描述的方法、设备和/或系统的多种可行方式中的一些可行方式。
在整个说明书中,当诸如层、区域或基板的元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时,该元件可直接“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件,或者可存在介于它们之间的一个或更多个其它元件。相比之下,当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件、“直接结合到”另一元件时,可不存在介于它们之间的其它元件。
如在此使用的,术语“和/或”包括相关所列项中的任何一个和任何两个或更多个的任何组合。
虽然诸如“第一”、“第二”和“第三”的术语可在此用于描述各种构件、组件、区域、层或部分,但是这些构件、组件、区域、层或部分不受这些术语限制。更确切地说,这些术语仅用于将一个构件、组件、区域、层或部分与另一构件、组件、区域、层或部分区分开。因此,在不脱离示例的教导的情况下,在此描述的示例中的涉及到的第一构件、组件、区域、层或部分还可被称为第二构件、组件、区域、层或部分。
为了方便描述,在此可使用诸如“在……之上”、“上方”、“在……之下”以及“下方”的空间相对术语来描述如附图中所示的一个元件与另一元件的关系。这样的空间相对术语意于除了包含附图中描绘的方位之外还包含装置在使用或操作中的不同方位。例如,如果附图中的装置被翻转,则被描述为“在”另一元件“之上”或“上方”的元件将随后“在”另一元件“之下”或“下方”。因此,术语“在……之上”根据装置的空间方位包括“在……之上”和“在……之下”两种方位。装置还可以以其它方式被定位(例如,旋转90度或处于其它方位),并且可对在此使用的空间相对术语做出相应的解释。
在此使用的术语仅是为了描述各种示例,而不被用来限制本公开。除非上下文另外清楚地指明,否则单数形式也意于包含复数形式。术语“包含”、“包括”以及“具有”列举存在陈述的特征、数量、操作、构件、元件和/或它们的组合,但不排除存在或添加一个或更多个其它特征、数量、操作、构件、元件和/或它们的组合。
由于制造技术和/或公差,可发生附图中所示出的形状的变化。因此,在此描述的示例不限于附图中示出的特定的形状,而是包括制造过程中发生的形状上的改变。
在此描述的示例的特征可以以在理解了本申请的公开内容之后将显而易见的各种方式进行组合。此外,虽然在此描述的示例具有多种构造,但是在理解了本申请的公开内容之后将显而易见的其它构造是可行的。
图1是根据实施例的半导体封装件的截面图,图2是沿着图1的线I-I’截取的截面图。
参照图1和图2,根据实施例的半导体封装件100(使用毫米波带发送和接收无线电信号的半导体封装件)包括基板10、电路部1、信号传输部20、密封部50和散热部30。
基板10可以是通过重复地堆叠绝缘层和布线层形成的多层基板。然而,按照需要,也可使用其中布线层形成在一个绝缘层的背对的表面上的双面基板。
基板10的布线层包括一个或更多个天线12。天线12可设置在基板10的上表面(第一表面)和侧表面中的任意一个上以及基板的内部。此外,天线12可包括偶极天线、单极天线和贴片天线中的至少一种。
在实施例中,天线12意指辐射体,但也可被理解为包括将辐射体和电子元件彼此连接的布线。此外,根据实施例的天线12可发射和/或接收毫米(mm)波带的射频(RF)信号。
布线层将电路部1和天线12彼此电连接。布线层可通过诸如铜(Cu)、镍(Ni)、铝(Al)、银(Ag)或金(Au)的具有导电性的金属而形成。
根据实施例,电路部1和天线12之间的距离可相对短于使用低频带的传统的半导体封装件中的电路部和天线之间的距离。为此,根据实施例,天线12形成在基板10的第一表面上,并且电路部1安装在基板10的第二表面上。结果,显著地减小了信号电力损耗,并且减小了反射特性的劣化。
可使用本领域中已知的各种类型的基板(例如,印刷电路板、柔性基板、陶瓷基板、玻璃基板等)作为基板10。
电路部1包括一个或更多个元件,并且安装在基板10的背对的表面中的至少一个上。这里,该元件包括有源元件和无源元件二者。
此外,电路部1可包括在操作中产生大量热的发热元件1a和至少一个普通元件1b。发热元件1a可包括其上形成有端子的有效表面和无效表面(有效表面的背对的表面),并且可安装在基板10的表面中的其上没有设置天线12的第二表面上。
例如,在如图1所示的天线12设置在基板10的上表面上的情况下,发热元件1a可按照倒装芯片结合结构安装在基板10的下表面(第二表面)上。在这种情况下,发热元件1a和基板10之间的间隙可填充有底部填充树脂。
发热元件1a可包括多个模拟组件(MAC)、基带信号处理电路等,但不限于此。
信号传输部20设置在基板10的背对的表面中的其上设置有电路部1的第二表面上,并且具有比电路部1高的安装高度。因此,与电路部1相比,信号传输部20从基板10进一步向下突出。
此外,信号传输部20包括具有电连接到基板10的一端的连接导体21以及保护连接导体21的绝缘部22。
连接导体21设置在密封部50中并穿过密封部50,并且具有结合到基板10的一端和连接到连接端子24的另一端。因此,连接导体21还可形成为具有各种形式,只要其电连接在基板10和连接端子24之间即可。
连接导体21可利用导电材料形成,并且可利用例如铜、金、银、铝或它们的合金形成。
绝缘部22设置在连接导体21的表面上,以保护连接导体21。因此,绝缘部22可填埋连接导体21,并且仅使连接导体21的背对的端部暴露于外部。绝缘部22可利用绝缘树脂材料形成。然而,绝缘部22不限于此。
例如,可使用印刷电路板(PCB)作为如上所述构造的信号传输部20,或信号传输部20可被构造为与印刷电路板(PCB)相似的形式。然而,信号传输部20不限于此,而是可按照以下将描述的实施例进行各种变型。
同时,由于根据实施例的信号传输部20嵌在密封部50中,因此密封部50也可用作绝缘部22。因此,根据需要,信号传输部20还可仅包括连接导体21,同时可省略绝缘部22。
连接端子24可结合到连接导体21的另一端。
当半导体封装件100安装在主基板90上时,连接端子24将半导体封装件100和主基板90彼此物理连接并且彼此电连接。连接端子24可利用诸如焊料的导电粘合剂形成,但不限于此。
同时,如图2所示,根据实施例的信号传输部20形成为沿着基板10的轮廓的四边形环的形状。然而,本公开的构造不限于此,而是可进行各种变型。
图3是图2中示出的信号传输部的变型示例的示图。
参照图3,信号传输部20可形成为棒状,或可形成为弯曲的线状。此外,信号传输部20还可形成为其中连接端子24以列布置的块状。然而,信号传输部20可进行各种变型,例如,可形成为圆形、椭圆形或不规则形状。
再次参照图1和图2,将描述散热部30。
散热部30结合到发热元件1a的无效表面,以将从发热元件1a产生的热散发到外部。
为此,散热部30包括传热部32和散热端子34。
传热部32可形成为平板形式或块形式,并且传热部32的第一表面可结合到发热元件1a的无效表面。此外,一个或更多个散热端子34可结合到传热部32的第二表面。
因此,从发热元件1a传导到传热部32的第一表面的热可通过传热部32的第二表面传递到散热端子34。
传热部32可利用各种材料形成,只要该材料具有高的导热性即可。例如,传热部32可利用金属构件形成,并且可利用诸如铜(Cu)、镍(Ni)、钛(Ti)、金(Au)、锡(Sn)等材料形成。然而,传热部32的材料不限于此,而是还可使用诸如石墨的具有导热性的非金属。
传热部32可通过结合层35结合到发热元件1a。
结合层35可通过使用诸如环氧树脂的树脂类粘合剂涂覆发热元件1a的无效表面或传热部32的第一表面而形成。在这种情况下,结合层35利用非导电材料形成。
然而,结合层35的材料不限于此,而是结合层35还可通过在无效表面上形成金属薄膜层而形成。在这种情况下,传热部32可通过诸如焊接等方法结合到结合层35。
同时,当传热部32具有粘合性质时,可省略结合层。
根据实施例,传热部32形成为四边形平板的形式,并且可具有比发热元件1a的无效表面的面积大的面积。然而,传热部32的形状或尺寸不限于此,而是可根据需要进行各种变型。
散热端子34可结合到传热部32的第二表面。
散热端子34可利用与连接端子24的材料相同的材料形成。因此,在制造过程中,散热端子34可与连接端子24一起共同地结合到主基板90。
此外,散热端子34和连接端子24可通过使用相同的构件利用相同的方法形成。例如,散热端子34和连接端子24可通过将形成为相同尺寸的焊球分别结合到传热部32和连接导体21而形成。因此,散热端子34可形成为具有与连接端子24的尺寸相同或相似的尺寸。
密封部50可形成在基板10的第二表面上。因此,密封部50设置为填埋安装在基板10的第二表面上的电路部1和信号传输部20。
密封部50填充在构成电路部1的各个元件1a和1b之间,从而防止元件1a和1b之间发生电短路,围住元件1a和1b的外部,将元件1a和1b固定在基板10上,并且安全地保护元件1a和1b免于外部冲击。
此外,密封部50填埋信号传输部20,从而将信号传输部20稳定地固定到基板10,并且保护信号传输部20免于外部冲击。
当形成密封部50时,如图2所示,仅连接端子24和散热端子34可从半导体封装件100的下表面暴露于密封部50的外部。
密封部50可利用绝缘材料形成。根据实施例,可使用环氧塑封料(EMC),但是密封部50的材料不限于此。
同时,图1中示出的主基板90(其上安装有半导体封装件100的基板)可以指的是各种应用(例如,便携式终端、计算机、膝上型电脑、TV等)中包括的电路板。因此,可使用诸如印刷电路板、柔性基板、陶瓷基板、玻璃基板等各种已知的基板作为主基板90。
电极焊盘91和92可形成在主基板90的第一表面上。电极焊盘91和92包括连接到连接端子24的信号焊盘91和连接到散热端子34的散热焊盘92。
接下来,将描述用于制造根据实施例的半导体封装件的方法。
图4示出了用于制造图1中所示的半导体封装件的方法。
参照图4,在根据实施例的半导体封装件中,首先,在包括天线12的基板10的第二表面上形成电路部1,并且在基板10的第二表面上设置信号传输部20(S1)。电路部1和信号传输部20通过诸如焊料的导电粘合剂而共同地安装在基板10上。
此外,在发热元件1a的无效表面上设置传热部32。如上所述,传热部32通过结合层35结合到发热元件1a。
接下来,形成填埋整个电路部1和整个信号传输部20的密封部50(S2)。密封部50可通过对EMC传递模塑(transfer-molding)而形成,但不限于此。
接下来,形成通路孔55,以使信号传输部20的一部分和传热部32的一部分暴露(S3)。通路孔55可使用激光钻孔而形成。因此,通路孔55可形成为朝向底部具有较小的截面面积的圆锥形状。
接下来,可通过在通路孔55中形成连接端子24和散热端子34完成半导体封装件100。通过在通路孔55中设置焊球然后使设置的焊球熔化并且固化来使连接端子24和散热端子34分别结合到连接导体21和传热部32。
如上所述构造的根据实施例的半导体封装件100通过传热部32和散热端子34将热从发热元件1a散发到主基板90。因此,与现有技术相比,可改善半导体封装件的散热特性。
同时,根据本申请的半导体封装件不限于以上描述的实施例,而是可进行各种变型。
图5是示出图2中所示的传热部的变型示例的示图。
参照图5,传热部32可具有沿着与结合层35接触的第一表面的边缘形成的台阶33。
设置这样的台阶33,以显著减小在制造传热部32的过程中产生的毛刺(burr)B的影响。
传热部32可通过各种方法形成,例如,通过压制处理形成。在这种情况下,毛刺B可形成在传热部32的第一表面的边缘部分中。
在如上所述形成毛刺B的情况下,由于在将结合层35涂覆到传热部32上的过程中与毛刺B干涉而导致精确度下降,因此可能会发生可靠性问题。
因此,根据实施例,通过在该边缘部分中通过压制处理然后执行切割工艺形成第一台阶33来制造传热部32。在这种情况下,如图5所示,由于毛刺B位于台阶33的厚度范围内,因此在将结合层35涂覆在传热部32的第一表面上的过程中不会与毛刺B产生干涉。
同时,图5中示出的本实施例以示例的方式示出了台阶33形成在传热部32的第一表面和第二表面二者中的情况。然而,台阶33的位置不限于此,而是台阶还可仅形成在第一表面和第二表面中的形成有毛刺B的一个表面中。
此外,根据实施例,传热部32包括一个或更多个结合槽36。
结合槽36可具有穿过传热部32的孔,并且可填充有密封部50。由此,传热部32可更稳定地结合到密封部50。
当传热部32结合到发热元件1a时,结合槽36可用作基准标记。因此,在制造半导体封装件的过程中,传热部32和发热元件1a可更准确地彼此结合。
同时,在结合槽36没有用作基准标记的情况下,结合槽36可形成为槽的形式,而非通孔的形式。
结合槽36形成在传热部32的每个末端部分中。然而,结合槽36不限于此,而是可根据需要设置在各个位置中,并且可根据传热部32的厚度或面积而设置多个结合槽。例如,结合槽可分布在传热部的整个区域上或传热部的整个区域的一部分上。
图6至图8是根据实施例的半导体封装件中的每个的截面图。
首先,参照图6,在根据实施例的半导体封装件中,传热部32可形成为具有与发热元件1a的无效表面的面积相同或相似的面积。
此外,根据实施例的发热元件1a可以为具有比以上描述的实施例中的发热元件的厚度厚的元件。从而,传热部32具有比以上描述的实施例中的传热部的厚度薄的厚度。
在传热部32需要形成为具有薄的厚度的示例中,传热部32通过诸如沉积或镀覆方法形成在发热元件1a的无效表面上,但不限于此。
此外,根据实施例的传热部32的一部分可暴露于密封部50的外部。因此,散热端子34设置在传热部32的暴露于密封部50的外部的部分处。
在根据实施例的半导体封装件中,传热部32的散热端子34结合到其的整个第二表面暴露于密封部50的外部。然而,各种变型是可行的。例如,在于传热部32的第二表面中形成台阶之后,可仅使第二表面的一部分暴露。
同时,在散热端子34结合到传热部32的暴露的第二表面的示例中,散热端子34可在将散热端子34结合到传热部32的过程中熔化,并且可沿着传热部32的第二表面扩散。在这种情况下,难以使散热端子34保持图6中示出的球的形状。
因此,根据实施例的半导体封装件包括在传热部32的第二表面上限定散热端子34的位置的绝缘层38。绝缘层38大体设置在传热部32的暴露于外部的整个第二表面上,并且按照仅形成有散热端子34的部分被去除的形式来形成,例如,绝缘层38可通过阻焊剂形成。
因此,根据实施例的用于制造半导体封装件的方法包括如下操作:形成密封部50以完全填埋信号传输部20和传热部32,然后去除密封部50的一部分,以使传热部32的第二表面暴露。去除密封部50的一部分的操作可通过抛光操作来执行。
此外,半导体封装件可通过执行如下操作来完成:在传热部32的第二表面上形成绝缘层38,其中,绝缘层38上形成有散热端子34的部分被去除;在密封部50中形成通路孔55;将连接端子24和散热端子34结合到信号传输部20和传热部32。这里,根据需要,形成通路孔55的操作可在形成绝缘层38的操作之前执行。
参照图7,在根据实施例的半导体封装件中,传热部32形成为盖形式。更详细地讲,传热部32形成为包括内部空间的碗形式,并且以将发热元件1a容纳在该内部空间中的形式结合到发热元件1a。
因此,发热元件1a的无效表面结合到传热部32的内部空间的底表面。
传热部32的侧壁可结合到基板10。然而,传热部32的侧壁不限于此,而是还可根据需要被构造为与基板10分开。在此使用的术语“分开”可通常意味着不接触。
此外,一个或更多个通孔36a形成在传热部32中。设置通孔36a以将密封部50设置在传热部32的内部空间中。当设置通孔36a时,在制造密封部50的过程中,密封部50的熔化的树脂、原材料通过通孔被引入到传热部32的内部空间中,从而填充传热部32的内部空间。
同时,虽然未示出,但是与图6的上述情况相似,根据实施例的传热部32也可暴露于密封部50的外部。
参照图8,根据实施例的半导体封装件可使用诸如焊球的导电构件23构成信号传输部20。在这种情况下,信号传输部20不是一体地形成,导电构件设置为彼此分开。此外,降低了用于制造信号传输部20的成本。
在用于制造根据实施例的半导体封装件的方法中,在将分开制造的导电构件23安装在基板10的第二表面上之后,形成围住导电构件23的密封部50。这里,由于当导电构件23被设置为彼此分开时在导电构件23之间形成空间,因此密封部50的熔化的树脂、原材料容易通过这样的空间流动。因此,容易制造密封部50。
随后的制造工艺可按照与以上描述的实施例相似的方式执行。
然而,根据本申请的用于制造半导体封装件的方法不限于上述的方法,而是如图9所示,导电构件23还可通过在基板10的第二表面上首先形成密封部50、形成完全穿过密封部50的通路孔然后在通路孔中填充导电材料而制成。在这种情况下,通路孔可使用激光钻孔而形成,膏体的形式的导电材料可填充在通路孔中,然后熔化并固化,或可通过镀覆方式形成在通路孔中。
此外,在图9中示出的半导体封装件中,散热端子34没有直接结合到传热部32,而是在设置穿过密封部50的散热过孔34a之后,散热端子34结合到散热过孔34a。
散热过孔34a可在形成导电构件23的操作中同时形成。此外,散热端子34可在将连接端子24结合到导电构件23的操作中同时结合到散热过孔34a。
同时,虽然未示出,但是焊盘可形成在散热过孔34a的散热端子34结合到其的结合表面上。此外,散热端子34和散热过孔34a可利用相同的材料形成,但不限于此。
图10是示意性地示出根据实施例的电子装置的示图。
参照图10,在根据实施例的电子装置中,图1中示出的半导体封装件100安装在主基板90上。然而,电子装置不限于此,还可使用其它实施例中描述的半导体封装件。
主基板90(如上所述的其上安装有半导体封装件100的基板)可指应用(例如,便携式终端、计算机、膝上型电脑、TV等)中包括的电路板。因此,可使用诸如印刷电路板、柔性基板、陶瓷基板、玻璃基板等各种已知的基板作为主基板90。
电极焊盘91和92形成在主基板90的第一表面上。电极焊盘91和92包括连接到连接端子24的信号焊盘91和连接到散热端子34的散热焊盘92。
此外,一个或更多个散热过孔95设置在主基板90中。
散热过孔95设置为穿过主基板90,并且具有连接到散热焊盘92的一端。此外,散热过孔95的另一端暴露于主基板90的第二表面,并且连接到散热构件80。
散热构件80结合到主基板90的第二表面并且连接到散热过孔95。因此,从散热过孔95传递的热通过散热构件80被排放到外部。
可使用热沉(heat sink)作为散热构件80,但是散热构件不限于此。此外,可根据需要省略散热构件80。
例如,在发热元件通过结合线电连接到基板的情况下,传热部可结合到发热元件的有效表面。
此外,以上描述的实施例可彼此结合。例如,图8中示出的导电构件可全部应用于其它实施例中公开的半导体封装件。
如上所述,根据实施例,半导体封装件和具有半导体封装件的电子装置可将发热元件的热通过传热部和散热端子散发到主基板。因此,与现有技术相比,改善了半导体封装件的散热特性。
虽然本公开包括具体的示例,但是在理解了本申请的公开内容之后将显而易见的是,在不脱离权利要求及其等同物的精神和范围的情况下,可在这些示例中做出形式上和细节上的各种改变。在此描述的示例将仅被视为描述性含义,而非出于限制的目的。每个示例中的特征或方面的描述将被认为是可适用于其它示例中的类似特征或方面。如果以不同的顺序执行描述的技术,和/或如果以不同的方式组合描述的系统、架构、装置或者电路中的组件和/或用其它组件或者它们的等同物进行替换或者补充描述的系统、架构、装置或者电路中的组件,则可获得适当的结果。因此,本公开的范围不由具体实施方式限定,而是由权利要求及其等同物限定,并且在权利要求及其等同物的范围内的所有变型将被解释为包含于本公开中。
Claims (16)
1.一种半导体封装件,包括:
基板,包括天线;
发热元件,设置在所述基板的第一表面上并且连接到所述天线;
传热部,结合到所述发热元件;
信号传输部,设置在所述基板的所述第一表面上并且将所述基板电连接到主基板;
密封部,形成在所述基板的所述第一表面上;以及
散热端子,将所述传热部和所述主基板彼此连接,
其中,所述信号传输部、所述发热元件和所述传热部嵌在所述密封部中,并且
其中,所述散热端子从所述密封部突出,并且所述散热端子中的每个包括被所述密封部包围的第一部分和暴露于所述密封部的表面上并且与所述主基板接触的第二部分,
其中,所述传热部包括台阶,所述台阶设置在所述传热部的结合到所述发热元件的第一表面的边缘中。
2.根据权利要求1所述的半导体封装件,其中,所述传热部具有平板形状或块形状,并且包括金属。
3.根据权利要求1所述的半导体封装件,所述半导体封装件还包括设置在所述信号传输部的一侧上并且连接到所述主基板的连接端子,
其中,所述散热端子包括与所述连接端子的材料相同的材料,并且具有与所述连接端子的尺寸大体相同的尺寸。
4.根据权利要求1所述的半导体封装件,其中,所述传热部完全嵌在所述密封部中,并且
所述散热端子穿过所述密封部并且连接到所述传热部。
5.根据权利要求4所述的半导体封装件,其中,所述传热部包括一个或更多个结合槽,并且
所述密封部的一部分设置在所述一个或更多个结合槽中。
6.根据权利要求5所述的半导体封装件,其中,所述一个或更多个结合槽包括穿过所述传热部的孔,并且
所述一个或更多个结合槽被设置为分布在所述传热部的区域上。
7.根据权利要求2所述的半导体封装件,其中,所述台阶还设置在所述传热部的结合到所述散热端子的第二表面的边缘中。
8.根据权利要求1所述的半导体封装件,其中,所述传热部包括外壳,所述外壳包括内部空间,并且
所述发热元件设置在所述外壳的所述内部空间中。
9.根据权利要求8所述的半导体封装件,其中,所述外壳包括一个或更多个通孔,并且
所述密封部通过所述通孔设置在所述外壳的所述内部空间中。
10.根据权利要求1所述的半导体封装件,其中,所述信号传输部包括:连接导体,包括连接到所述基板的一端和通过连接端子连接到所述主基板的另一端;以及绝缘部,包围所述连接导体。
11.根据权利要求1所述的半导体封装件,其中,所述信号传输部包括在所述密封部中熔化并且固化的焊球。
12.根据权利要求1所述的半导体封装件,所述半导体封装件还包括插设在所述发热元件和所述传热部之间的结合层。
13.一种电子装置,包括:
半导体封装件,包括基板、发热元件、信号传输部、密封部和传热部,其中,所述发热元件、所述信号传输部和所述密封部设置在所述基板的一个表面上,所述传热部结合到所述发热元件;以及
主基板,其中,所述半导体封装件设置在所述主基板的第一表面上,
其中,所述半导体封装件还包括将所述传热部和所述主基板彼此连接的散热端子,并且
所述主基板包括连接到所述散热端子的一个或更多个散热过孔,
其中,所述信号传输部、所述发热元件和所述传热部嵌在所述密封部中,并且
其中,所述散热端子从所述密封部突出,并且所述散热端子中的每个包括被所述密封部包围的第一部分和暴露于所述密封部的表面上并且与所述主基板接触的第二部分,
其中,所述传热部包括台阶,所述台阶设置在所述传热部的结合到所述发热元件的第一表面的边缘中。
14.根据权利要求13所述的电子装置,所述电子装置还包括结合到所述主基板的第二表面的散热构件,
其中,所述散热过孔穿过所述主基板并且连接到所述散热构件。
15.根据权利要求13所述的电子装置,所述电子装置还包括设置在所述基板上的天线。
16.根据权利要求15所述的电子装置,其中,所述天线发送和/或接收毫米波长带的无线电信号。
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Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11569198B2 (en) * | 2018-01-03 | 2023-01-31 | Intel Corporation | Stacked semiconductor die architecture with multiple layers of disaggregation |
US11694976B2 (en) * | 2018-10-11 | 2023-07-04 | Intel Corporation | Bowl shaped pad |
US11101226B2 (en) * | 2019-02-22 | 2021-08-24 | DustPhotonics Ltd. | Method for conveying high frequency module and a high-frequency module |
US10985118B2 (en) | 2019-02-22 | 2021-04-20 | Xsight Labs Ltd. | High-frequency module |
EP3716321A1 (en) * | 2019-03-29 | 2020-09-30 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded semiconductor component and embedded highly conductive block which are mutually coupled |
CN110138391B (zh) * | 2019-05-20 | 2021-03-02 | 维沃移动通信有限公司 | 一种移动终端 |
KR102377811B1 (ko) * | 2019-08-09 | 2022-03-22 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
US11145610B2 (en) * | 2019-12-30 | 2021-10-12 | Unimicron Technology Corp. | Chip package structure having at least one chip and at least one thermally conductive element and manufacturing method thereof |
US11356070B2 (en) | 2020-06-01 | 2022-06-07 | Wolfspeed, Inc. | RF amplifiers having shielded transmission line structures |
US11837457B2 (en) * | 2020-09-11 | 2023-12-05 | Wolfspeed, Inc. | Packaging for RF transistor amplifiers |
US11670605B2 (en) | 2020-04-03 | 2023-06-06 | Wolfspeed, Inc. | RF amplifier devices including interconnect structures and methods of manufacturing |
US11990384B2 (en) | 2020-04-17 | 2024-05-21 | Nxp Usa, Inc. | Amplifier modules with power transistor die and peripheral ground connections |
US11990872B2 (en) | 2020-04-17 | 2024-05-21 | Nxp Usa, Inc. | Power amplifier modules including topside cooling interfaces and methods for the fabrication thereof |
KR102328997B1 (ko) * | 2020-04-21 | 2021-11-18 | 삼성전기주식회사 | 방열부를 갖는 전자 소자 모듈 및 그 제조 방법 |
US11908767B2 (en) * | 2021-01-13 | 2024-02-20 | Mediatek Inc. | Semiconductor package structure |
EP4044221A1 (en) * | 2021-02-10 | 2022-08-17 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Heat removal architecture for stack-type component carrier with embedded component |
KR20220164946A (ko) * | 2021-06-07 | 2022-12-14 | 삼성전자주식회사 | 반도체 패키지 |
US20230110957A1 (en) * | 2021-10-13 | 2023-04-13 | Mediatek Inc. | Electronic device with stacked printed circuit boards |
CN118451789A (zh) * | 2021-12-22 | 2024-08-06 | 瑞典爱立信有限公司 | 用于集成电路的热互连 |
JP2024040632A (ja) * | 2022-09-13 | 2024-03-26 | 富士通株式会社 | アンテナ付き半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101090098A (zh) * | 2006-06-16 | 2007-12-19 | 索尼株式会社 | 半导体装置及其制造方法 |
CN101192601A (zh) * | 2006-11-30 | 2008-06-04 | 东芝照明技术株式会社 | 具有半导体发光元件的照明装置 |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5726079A (en) * | 1996-06-19 | 1998-03-10 | International Business Machines Corporation | Thermally enhanced flip chip package and method of forming |
KR100230189B1 (ko) | 1996-10-04 | 1999-11-15 | 마이클 디. 오브라이언 | 볼 그리드 어레이 반도체 패키지 |
JP2914342B2 (ja) | 1997-03-28 | 1999-06-28 | 日本電気株式会社 | 集積回路装置の冷却構造 |
US6653730B2 (en) * | 2000-12-14 | 2003-11-25 | Intel Corporation | Electronic assembly with high capacity thermal interface |
JP2002353398A (ja) * | 2001-05-25 | 2002-12-06 | Nec Kyushu Ltd | 半導体装置 |
JP2003007910A (ja) | 2001-06-19 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 半導体装置 |
KR100495219B1 (ko) | 2003-06-25 | 2005-06-14 | 삼성전기주식회사 | Ic칩 내장형 파워 엠프 모듈 |
JP4254527B2 (ja) * | 2003-12-24 | 2009-04-15 | 株式会社デンソー | 半導体装置 |
US7517787B2 (en) * | 2005-03-22 | 2009-04-14 | Intel Corporation | C4 joint reliability |
JP4534062B2 (ja) * | 2005-04-19 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7545029B2 (en) * | 2006-08-18 | 2009-06-09 | Tessera, Inc. | Stack microelectronic assemblies |
JP4833192B2 (ja) * | 2007-12-27 | 2011-12-07 | 新光電気工業株式会社 | 電子装置 |
US8263437B2 (en) * | 2008-09-05 | 2012-09-11 | STATS ChiPAC, Ltd. | Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit |
US8058714B2 (en) * | 2008-09-25 | 2011-11-15 | Skyworks Solutions, Inc. | Overmolded semiconductor package with an integrated antenna |
US8237252B2 (en) * | 2009-07-22 | 2012-08-07 | Stats Chippac, Ltd. | Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation |
US8278214B2 (en) * | 2009-12-23 | 2012-10-02 | Intel Corporation | Through mold via polymer block package |
KR101711048B1 (ko) * | 2010-10-07 | 2017-03-02 | 삼성전자 주식회사 | 차폐막을 포함하는 반도체 장치 및 제조 방법 |
KR101780423B1 (ko) * | 2011-03-18 | 2017-09-22 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
US8946888B2 (en) * | 2011-09-30 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on packaging structure and methods of making same |
JP5474127B2 (ja) | 2012-05-14 | 2014-04-16 | 株式会社野田スクリーン | 半導体装置 |
US9153542B2 (en) * | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
JP6129177B2 (ja) | 2012-08-03 | 2017-05-17 | パナソニック株式会社 | 電子部品モジュールとその実装体 |
KR20140130920A (ko) * | 2013-05-02 | 2014-11-12 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
JP6314729B2 (ja) | 2014-07-30 | 2018-04-25 | 株式会社ソシオネクスト | 半導体装置及び半導体装置の製造方法 |
KR102117473B1 (ko) | 2015-03-18 | 2020-06-01 | 삼성전기주식회사 | 실장 기판 모듈, 안테나 장치 및 실장 기판 모듈 제조 방법 |
US9461001B1 (en) * | 2015-07-22 | 2016-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same |
US9806040B2 (en) * | 2015-07-29 | 2017-10-31 | STATS ChipPAC Pte. Ltd. | Antenna in embedded wafer-level ball-grid array package |
US9974158B2 (en) * | 2016-08-31 | 2018-05-15 | Qorvo Us, Inc. | Air-cavity package with two heat dissipation interfaces |
US10910329B2 (en) * | 2017-05-23 | 2021-02-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
KR20190050155A (ko) * | 2017-11-02 | 2019-05-10 | 삼성전기주식회사 | 반도체 패키지와 그 제조 방법 |
-
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- 2017-08-16 KR KR1020170103390A patent/KR20190018812A/ko not_active IP Right Cessation
- 2017-12-06 US US15/832,807 patent/US10636721B2/en active Active
-
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- 2018-02-06 CN CN201810115945.6A patent/CN109411423B/zh active Active
-
2020
- 2020-03-19 US US16/823,791 patent/US11437295B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101090098A (zh) * | 2006-06-16 | 2007-12-19 | 索尼株式会社 | 半导体装置及其制造方法 |
CN101192601A (zh) * | 2006-11-30 | 2008-06-04 | 东芝照明技术株式会社 | 具有半导体发光元件的照明装置 |
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US20200219784A1 (en) | 2020-07-09 |
US11437295B2 (en) | 2022-09-06 |
KR20190018812A (ko) | 2019-02-26 |
CN109411423A (zh) | 2019-03-01 |
US10636721B2 (en) | 2020-04-28 |
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