CN109411332B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN109411332B CN109411332B CN201710706018.7A CN201710706018A CN109411332B CN 109411332 B CN109411332 B CN 109411332B CN 201710706018 A CN201710706018 A CN 201710706018A CN 109411332 B CN109411332 B CN 109411332B
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- 238000000034 method Methods 0.000 title claims abstract description 103
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 125
- 230000008569 process Effects 0.000 claims abstract description 69
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 238000009832 plasma treatment Methods 0.000 claims abstract description 26
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 34
- 239000003989 dielectric material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 9
- 230000000149 penetrating effect Effects 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 229920000620 organic polymer Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 63
- 238000012545 processing Methods 0.000 description 18
- 230000000694 effects Effects 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229910020381 SiO1.5 Inorganic materials 0.000 description 1
- 229910020175 SiOH Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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Abstract
A semiconductor device and a method of forming the same, the method comprising: carrying out plasma treatment on the side wall of the photoresist layer, wherein the plasma treatment process also etches the bottom anti-reflection layers at the bottoms of the first opening and the second opening to ensure that the surfaces of the bottom anti-reflection layers are sunken, and the sunken degree of the surface of the bottom anti-reflection layer at the bottom of the second opening is greater than that of the bottom anti-reflection layer at the bottom of the first opening; then etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening, correspondingly forming a third opening and a fourth opening which penetrate through the bottom anti-reflection layers in the bottom anti-reflection layers at the bottoms of the first opening and the second opening, wherein the bottom width of the fourth opening is smaller than that of the third opening; and etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, forming a first groove in the dense region of the layer to be etched, and forming a second groove in the sparse region of the layer to be etched. The performance of the semiconductor device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous progress of semiconductor integrated circuit technology, as semiconductor devices are scaled down to the deep submicron range, high-performance and high-density connections between semiconductor devices need to be realized through an interconnection structure.
Based on the requirement of integrated circuit design, the interconnection structure is provided with a sparse area and a dense area, and the density of the interconnection structure in the dense area is greater than that of the interconnection structure in the sparse area. Usually, the interconnection structure of the dense region and the interconnection structure of the sparse region are formed in the same process.
However, the performance of the semiconductor device formed by the interconnection structure formed by the prior art is poor.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a layer to be etched, wherein the layer to be etched comprises a sparse region and a dense region, the layer to be etched is provided with a bottom anti-reflection layer and a photoresist layer positioned on the surface of the bottom anti-reflection layer, the photoresist layer is provided with a first opening and a second opening which penetrate through the photoresist layer, the first opening is positioned on the dense region, and the second opening is positioned on the sparse region; carrying out plasma treatment on the side wall of the photoresist layer, wherein the plasma treatment process also etches the bottom anti-reflection layers at the bottoms of the first opening and the second opening to ensure that the surfaces of the bottom anti-reflection layers are sunken, and the sunken degree of the surface of the bottom anti-reflection layer at the bottom of the second opening is greater than that of the bottom anti-reflection layer at the bottom of the first opening; after plasma treatment is carried out, etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening, forming a third opening penetrating through the bottom anti-reflection layer in the bottom anti-reflection layer at the bottom of the first opening, forming a fourth opening penetrating through the bottom anti-reflection layer in the bottom anti-reflection layer at the bottom of the second opening, wherein the bottom width of the fourth opening is smaller than the bottom width of the third opening; and etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, forming a first groove in the dense region of the layer to be etched, and forming a second groove in the sparse region of the layer to be etched.
Optionally, the processing gas used in the plasma processing includes a fluorocarbon-based gas, and a molar ratio of the fluorocarbon-based gas to the processing gas is below 3/20.
Optionally, the fluorocarbon-based gas comprises CF4。
Optionally, the molar ratio of the fluorocarbon-based gas to the processing gas is 1/50-3/20.
Optionally, the process gas further comprises H2One or the combination of any of Ar and HBr.
Optionally, the parameters of the plasma processing further include: the plasma power is 20-2000W, and the pressure of the chamber is 3-500 mtorr.
Optionally, after the plasma treatment is performed and before the bottom anti-reflection layer at the bottom of the first opening and the bottom of the second opening are etched, the bottom anti-reflection layer surface at the bottom of the first opening has a first recess, the first recess has a first bottom surface and a first side surface around the first bottom surface, the bottom anti-reflection layer surface at the bottom of the second opening has a second recess, and the second recess has a second bottom surface and a second side surface around the second bottom surface; the second bottom surface is lower than the first bottom surface, and the dimension of the second bottom surface in the direction perpendicular to the second opening side wall is smaller than or equal to the dimension of the first bottom surface in the direction perpendicular to the first opening side wall.
Optionally, after the plasma treatment is performed and before the bottom anti-reflection layer at the bottom of the first opening and the bottom anti-reflection layer at the bottom of the second opening are etched, a first recess is formed in the surface of the bottom anti-reflection layer at the bottom of the first opening, and a second recess is formed in the surface of the bottom anti-reflection layer at the bottom of the second opening; in a section of the first recess, which is perpendicular to the side wall of the first opening, the first recess is provided with a first bottom point and first top points positioned on two sides of the first bottom point, the height from the first top point to the first bottom point is gradually reduced, and a first arc line is arranged from the first top point to the first bottom point; in a section of the second recess perpendicular to the side wall of the second opening, the second recess has a second bottom point and second vertexes located on two sides of the second bottom point, the height from the second vertex to the second bottom point is gradually reduced, a second arc line is arranged from the second vertex to the second bottom point, and the second bottom point is lower than the first bottom point.
Optionally, a flat layer is further arranged between the bottom anti-reflection layer and the layer to be etched; the method for forming the semiconductor device further comprises the following steps: before etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, etching the flat layer at the bottom of the third opening and the flat layer at the bottom of the fourth opening, forming a fifth opening in the flat layer in the dense area, forming a sixth opening in the flat layer in the sparse area, wherein the etching rate of the process for etching the flat layer at the bottom of the third opening and the fourth opening to the flat layer is greater than the etching rate of the bottom anti-reflection layer; and etching the layer to be etched by using the flat layer as a mask to form the first groove and the second groove.
Optionally, the process for etching the flat layer at the bottom of the third opening and the fourth opening includes an anisotropic dry etching process, and the parameters include: the gas employed is H2、N2、CO2And O2Any one or a combination of several of them.
Optionally, the process for etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening includes an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
Optionally, the method further includes: removing the bottom anti-reflection layer and the photoresist layer in the process of etching the bottom flat layers of the third opening and the fourth opening; and removing the flat layer after the first groove and the second groove are formed.
Optionally, the material of the planarization layer is an organic polymer or amorphous carbon.
Optionally, the process of etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening to form the third opening and the fourth opening is an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
Optionally, the bottom anti-reflection layer is made of silicon oxide or silicon-containing oxycarbide.
Optionally, the layer to be etched is made of a low-K dielectric material or an ultra-low-K dielectric material.
The invention also provides a semiconductor device formed by any one of the methods.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device provided by the technical scheme of the invention, the side wall of the photoresist layer is subjected to plasma treatment for improving the line width roughness of the photoresist layer and the edge roughness of the side wall of the photoresist layer. The plasma processing technology also etches the bottom anti-reflection layers at the bottoms of the first opening and the second opening, so that the degree of the depression of the surface of the bottom anti-reflection layer at the bottom of the second opening is greater than that of the bottom anti-reflection layer at the bottom of the first opening; and then in the process of etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening to form a third opening and a fourth opening, the etching rate of the etching process to the edge region of the surface with the concave bottom anti-reflection layer in the sparse region is smaller than that to the middle region, the etching rate of the etching process to the edge region of the surface with the concave bottom anti-reflection layer in the dense region is smaller than that to the middle region, the difference of the etching rate of the etching process to the edge region of the surface with the concave bottom anti-reflection layer in the sparse region relative to that of the middle region is larger, and the difference of the etching rate of the etching process to the edge region of the surface with the concave bottom anti-reflection layer in the dense region relative to that of the middle. Therefore, the width of the bottom of the fourth opening is smaller than that of the third opening, and in the subsequent etching process, the mask blocking effect of the bottom anti-reflection layer in the sparse area is larger than that of the bottom anti-reflection layer in the dense area. And further, the opening of the second groove is prevented from being overlarge relative to the opening of the first groove, and the size consistency of the second groove and the first groove is improved. Thereby improving the performance of the semiconductor device.
Further, a flat layer is arranged between the bottom anti-reflection layer and the layer to be etched; and before etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, etching the flat layer at the bottom of the third opening and the flat layer at the bottom of the fourth opening to form the fifth opening and the sixth opening. In the process of etching the bottom flat layers of the third opening and the fourth opening, the barrier effect of the bottom anti-reflection layer on the side wall of the fourth opening on the etching is larger than the barrier effect of the bottom anti-reflection layer on the side wall of the third opening on the etching, and the sixth opening is prevented from being too large relative to the opening of the fifth opening. And the process of etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening is carried out by taking the flat layer as a mask, so that the opening of the second groove is prevented from being too large relative to the opening of the first groove.
Furthermore, the processing gas adopted by the plasma processing comprises fluorocarbon-based gas, and the fluorocarbon-based gas has certain etching effect on the bottom anti-reflection layer, so that the surface of the bottom anti-reflection layer at the bottom of the second opening and the surface of the bottom anti-reflection layer at the bottom of the first opening are recessed. Because the density of the second openings is less than that of the first openings, the total area of the second openings in the sparse area to be etched is less than that of the first openings in the dense area to be etched, correspondingly, the supply of the etching gas in the sparse area can meet the consumption, or the consumption of the etching gas in the sparse area is more than the supply to cause the reduction of the etching rate is less. The plasma processing process has a large etching degree on the surface of the bottom anti-reflection layer at the bottom of the second opening. Secondly, the molar ratio of the fluorocarbon-based gas occupying the processing gas is below 3/20, and based on the load effect of etching, the consumption of the etching gas in the dense region is larger than the degree of supplying the etching gas to cause the reduction of the etching rate, and the etching degree of the plasma processing process on the surface of the bottom anti-reflection layer at the bottom of the first opening is far smaller than the etching degree on the surface of the bottom anti-reflection layer at the bottom of the second opening. Thereby the concave degree of the bottom anti-reflection layer surface at the bottom of the second opening is larger than that of the bottom anti-reflection layer surface at the bottom of the first opening.
Further, the process gas further comprises H2One or the combination of any of Ar and HBr. Further improving the line width roughness of the photoresist layer and the edge roughness of the sidewall of the photoresist layer.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process;
fig. 4 to 8 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, semiconductor devices formed in the prior art have poor performance.
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1, a layer to be etched 100 is provided, the layer to be etched 100 includes a sparse region Y and a dense region X, the layer to be etched 100 has a planar layer 111, a bottom anti-reflection layer 112 located on the planar layer 111, and a photoresist layer 120 located on a surface of the bottom anti-reflection layer 112, the photoresist layer 120 has a first mask opening 121 and a second mask opening 122 penetrating through the photoresist layer 120, the first mask opening 121 is located on the dense region, and the second mask opening 122 is located on the sparse region Y.
Referring to fig. 2, the sidewalls of the photoresist layer 120 are plasma treated using a gas including H2。
Referring to fig. 3, after the plasma treatment, the bottom anti-reflection layer 112, the flat layer 111 and the layer to be etched 100 are etched along the first mask opening 121 (refer to fig. 2) and the second mask opening 122 (refer to fig. 2) by using an anisotropic etching process, a first trench 131 is formed in the layer to be etched 100 in the dense region X, and a second trench 132 is formed in the layer to be etched 100 in the sparse region Y.
However, the performance of the semiconductor device formed by the method is poor, and researches show that the reason is that:
the plasma treatment of the sidewalls of the photoresist layer 120 includes: the line width roughness of the sidewalls of the photoresist layer 120 and the edge roughness of the sidewalls of the photoresist layer are improved. The etching of the surface of the bottom anti-reflection layer 112 at the bottom of the first mask opening 121 and the second mask opening 122 is less affected by the plasma treatment process. On this basis, the bottom anti-reflection layer 112, the planarization layer 111, and the layer to be etched 100 are etched along the first mask opening 121 (refer to fig. 2) and the second mask opening 122 (refer to fig. 2) using an anisotropic etching process to form the first trench 131 and the second trench 132. Since the density of the second mask openings 122 in the sparse region Y is less than the density of the first mask openings 121 in the dense region X, the consumption of the sparse region etching gas is greater than the consumption of the dense region etching gas which causes the decrease in the etching rate in the process of forming the first trench 131 and the second trench 132, based on the load effect of etching. The anisotropic etching process has a greater etching rate for the layer to be etched 100 along the width direction of the second mask opening 122 than for the layer to be etched 100 along the width direction of the first mask opening 121. Resulting in the width of the second groove 132 being much greater than the width of the first groove 131. The second groove and the first groove have poor dimensional consistency.
In order to solve the above problems, the present invention provides a method of forming a semiconductor device, including: carrying out plasma treatment on the side wall of the photoresist layer, wherein the plasma treatment process also etches the bottom anti-reflection layers at the bottoms of the first opening and the second opening to ensure that the surfaces of the bottom anti-reflection layers are sunken, and the sunken degree of the surface of the bottom anti-reflection layer at the bottom of the second opening is greater than that of the bottom anti-reflection layer at the bottom of the first opening; then etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening, correspondingly forming a third opening and a fourth opening which penetrate through the bottom anti-reflection layers in the bottom anti-reflection layers at the bottoms of the first opening and the second opening, wherein the bottom width of the fourth opening is smaller than that of the third opening; and etching the layer to be etched to form a first groove and a second groove. The performance of the semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 8 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 4, a layer to be etched 200 is provided, the layer to be etched 200 includes a dense region a and a sparse region B, the layer to be etched 200 has a bottom anti-reflection layer 212 and a photoresist layer 220 on the surface of the bottom anti-reflection layer 212, the photoresist layer 220 has a first opening 221 and a second opening 222 penetrating through the photoresist layer 220, the first opening 221 is located on the dense region a, and the second opening 222 is located on the sparse region B.
The layer to be etched 200 is made of a low-K dielectric material (low-K dielectric material has a relative dielectric constant of 2.6 or more and is small)Dielectric materials at 3.9) or ultra-low K dielectric materials (ultra-low K dielectric materials refer to dielectric materials having a relative dielectric constant less than 2.6). When the layer 200 to be etched is made of a low-K dielectric material or an ultra-low-K dielectric material, the layer 200 to be etched is made of SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), hydrogen silsesquioxane (HSQ, (HSiO) or an ultra-low-K dielectric material1.5)n) Or methylsilsesquioxane (MSQ, (CH)3SiO1.5)n). In this embodiment, the layer to be etched 200 is made of an ultra-low K dielectric material, and the ultra-low K dielectric material is SiCOH.
The layer to be etched 200 includes a dense region a and a sparse region B. The density of devices formed on the dense region A is greater than that of devices formed on the sparse region B. Accordingly, the density of the subsequently formed first grooves is greater than the density of the subsequently formed second grooves.
In this embodiment, the first opening 221 and the second opening 222 are the same in size. The density of the first openings 221 is greater than the density of the second openings 222.
The material of the bottom anti-reflection layer 212 is silicon oxide or silicon-containing oxycarbide.
There is also a planarization layer 211 between the bottom anti-reflective layer 212 and the layer to be etched 200. The material of the planarization layer 211 is an organic polymer or amorphous carbon.
Specifically, the step of forming the photoresist layer 220 includes: forming a photoresist material layer on the surface of the bottom anti-reflection layer 212; the photoresist material layer is exposed and developed to form a photoresist layer 220.
The role of the bottom anti-reflective layer 212 includes: in the process of exposing the photoresist material layer, light reflection at the bottom of the photoresist material layer is reduced to reduce shape deviation between the pattern of the first opening 221 and the pattern of the mask used for exposing the photoresist material layer, and to reduce shape deviation between the pattern of the second opening 222 and the pattern of the mask used for exposing the photoresist material layer.
The bottom anti-reflection layer 212 at the bottom of the first opening 221 includes a first middle region and a first edge region around the first middle region, and the bottom anti-reflection layer 212 at the bottom of the second opening 222 includes a second middle region and a second edge region around the second middle region.
Referring to fig. 5, the sidewalls of the photoresist layer 220 are plasma-treated, and the plasma treatment process further etches the bottom anti-reflection layer 212 at the bottoms of the first opening 221 and the second opening 222, so that the surface of the bottom anti-reflection layer 212 is recessed, and the recessed degree of the surface of the bottom anti-reflection layer 212 at the bottom of the second opening 222 is greater than the recessed degree of the surface of the bottom anti-reflection layer 212 at the bottom of the first opening 221.
The etching depth of the plasma treatment to the second middle area is greater than the etching depth to the first middle area and greater than the etching depth to the second edge area, and the etching depth to the second edge area is greater than the etching depth to the first edge area, so that the degree of the recess of the surface of the bottom anti-reflection layer 212 at the bottom of the second opening 222 is greater than the degree of the recess of the surface of the bottom anti-reflection layer 212 at the bottom of the first opening 221.
The bottom anti-reflection layer 212 at the bottom of the first opening 221 has a first recess on its surface, and the bottom anti-reflection layer 212 at the bottom of the second opening 222 has a second recess on its surface.
In this embodiment, in a cross section of the first recess perpendicular to the sidewall of the first opening 221, the first recess has a first bottom point and first top points located at two sides of the first bottom point, a height from the first top point to the first bottom point is gradually reduced, and a first arc line is formed from the first top point to the first bottom point; in a cross section of the second recess perpendicular to the sidewall of the second opening 222, the second recess has a second bottom point and second top points located at two sides of the second bottom point, the height from the second top point to the second bottom point is gradually reduced, the second top point to the second bottom point has a second arc line, and the second bottom point is lower than the first bottom point.
In another embodiment, the first recess has a first bottom surface and a first side around the first bottom surface, and the second recess has a second bottom surface and a second side around the second bottom surface; the second bottom surface is lower than the first bottom surface, and the dimension of the second bottom surface in the direction perpendicular to the second opening side wall is smaller than or equal to the dimension of the first bottom surface in the direction perpendicular to the first opening side wall.
The processing gas adopted by the plasma processing comprises a fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the processing gas is below 3/20. In a particular embodiment, the molar proportion of fluorocarbon-based gas occupying the process gas is below 1/20.
The processing gas used for the plasma processing includes a fluorocarbon-based gas, which has a certain etching effect on the bottom anti-reflection layer 212, so that the bottom anti-reflection layer 212 at the bottom of the second opening 222 and the bottom anti-reflection layer 212 at the bottom of the first opening 221 are recessed. Because the density of the second openings 222 is less than that of the first openings 221, the total area of the second openings 222 in the sparse region B to be etched is less than that of the first openings 221 in the dense region a, and accordingly, the supply of the etching gas in the sparse region B can meet the consumption requirement, or the consumption of the etching gas in the sparse region B is more than the supply to cause the reduction of the etching rate is less. The plasma treatment process etches the bottom anti-reflective layer 212 surface at the bottom of the second opening 222 to a greater extent. Secondly, the molar ratio of the fluorocarbon-based gas occupying the processing gas is below 3/20, and based on the load effect of etching, the consumption of the etching gas in the dense region a is greater than the degree of supplying the etching gas causing the decrease of the etching rate, and the degree of etching of the surface of the bottom anti-reflection layer 212 at the bottom of the first opening 221 by the plasma treatment process is much smaller than the degree of etching of the surface of the bottom anti-reflection layer 212 at the bottom of the second opening 222. Thereby making the degree of the recess of the bottom anti-reflection layer 212 surface at the bottom of the second opening 222 greater than that of the bottom anti-reflection layer 212 surface at the bottom of the first opening 221.
In a specific embodiment, the molar ratio of the fluorocarbon-based gas to the processing gas is 1/50-3/20.
The fluorocarbon-based gas comprises CF4。
The process gas further comprises H2One or the combination of any of Ar and HBr. Further improving the line width roughness of the photoresist layer 220 and the edge of the photoresist layer sidewallAnd (4) roughness.
The parameters of the plasma treatment further include: the plasma power is 20-2000W, and the pressure of the chamber is 3-500 mtorr.
Referring to fig. 6, after the plasma treatment is performed, the bottom anti-reflection layer 212 at the bottom of the first opening 221 and the second opening 222 is etched, a third opening 231 penetrating through the bottom anti-reflection layer 212 is formed in the bottom anti-reflection layer 212 at the bottom of the first opening 221, a fourth opening 232 penetrating through the bottom anti-reflection layer 212 is formed in the bottom anti-reflection layer 212 at the bottom of the second opening 222, and the bottom width of the fourth opening 232 is smaller than the bottom width of the third opening 231.
In the process of etching the bottom anti-reflection layer 212 at the bottoms of the first opening 221 and the second opening 222 to form the third opening 231 and the fourth opening 232, the etching rate of the etching process to the edge region of the surface where the bottom anti-reflection layer 212 in the sparse region B is recessed is less than the etching rate to the middle region, and the etching rate of the etching process to the edge region of the surface where the bottom anti-reflection layer 212 in the dense region a is recessed is less than the etching rate to the middle region. Because the degree of the recess of the bottom anti-reflection layer 212 surface at the bottom of the second opening 222 is greater than the degree of the recess of the bottom anti-reflection layer 212 surface at the bottom of the first opening 221, the difference between the etching rate of the etching process for the surface edge region where the bottom anti-reflection layer 212 is recessed in the sparse region B and the etching rate of the etching process for the surface edge region where the bottom anti-reflection layer 212 is recessed in the dense region a is greater than the etching rate of the etching process for the middle region, and the difference between the etching rate of the etching process for the surface edge. It is possible to make the bottom width of the fourth opening 232 smaller than the bottom width of the third opening 231.
The process of etching the bottom anti-reflection layer 212 at the bottom of the first opening 221 and the second opening 222 to form the third opening 231 and the fourth opening 232 is an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
In the process of etching the bottom anti-reflection layer 212 at the bottom of the first opening 221 and the second opening 222 to form the third opening 231 and the fourth opening 232, the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%, so the rate of etching the bottom anti-reflection layer 212 at the bottom of the first opening 221 and the second opening 222 is greater, and the third opening 231 and the fourth opening 232 can be formed faster.
Secondly, the molar ratio of the fluorocarbon-based gas occupying the etching gas is more than 30%, so that the difference between the concentration of the fluorocarbon-based gas distributed on the surface of the bottom anti-reflection layer 212 at the bottom of the first opening 221 and the concentration of the fluorocarbon-based gas distributed on the surface of the bottom anti-reflection layer 212 at the bottom of the second opening 222 is small. The difference between the bottom width of the fourth opening 232 and the bottom width of the third opening 231 is greatly influenced by the difference in the degree of recess of the surface of the bottom anti-reflection layer 212 at the bottom of the second opening 222 after the plasma treatment with respect to the degree of recess of the surface of the bottom anti-reflection layer 212 at the bottom of the first opening 221.
Then, the layer to be etched 200 at the bottom of the third opening 231 and the layer to be etched 200 at the bottom of the fourth opening 232 are etched, a first trench is formed in the dense region a of the layer to be etched 200, and a second trench is formed in the sparse region B of the layer to be etched 200.
The method for forming the semiconductor device further comprises the following steps: before etching the layer to be etched 200 at the bottom of the third opening 231 and the layer to be etched 200 at the bottom of the fourth opening 232, etching the flat layer 211 at the bottom of the third opening 231 and the flat layer 211 at the bottom of the fourth opening 232, forming a fifth opening in the flat layer 211 in the dense area A, forming a sixth opening in the flat layer 211 in the sparse area B, wherein the etching rate of the flat layer 211 by the process of etching the flat layer 211 at the bottoms of the third opening 231 and the fourth opening 232 is greater than the etching rate of the bottom anti-reflection layer 212; the layer to be etched 200 is etched using the planarization layer 211 as a mask to form a first trench and a second trench.
Referring to fig. 7, the flat layer 211 at the bottom of the third opening 231 and the flat layer 211 at the bottom of the fourth opening 232 are etched, a fifth opening 241 is formed in the flat layer 211 in the dense region a, a sixth opening 242 is formed in the flat layer 211 in the sparse region B, and the etching rate of the flat layer 211 at the bottom of the third opening 231 and the fourth opening 232 is greater than the etching rate of the bottom anti-reflection layer 212.
Since the bottom width of the fourth opening 232 is smaller than the bottom width of the third opening 231, in the process of etching the third opening 231 and the bottom planarization layer 211 of the fourth opening 232, the barrier effect of the bottom anti-reflection layer 212 on the sidewall of the fourth opening 232 on the etching is greater than the barrier effect of the bottom anti-reflection layer 212 on the sidewall of the third opening 231 on the etching, so as to avoid the opening of the sixth opening 242 relative to the fifth opening 241 from being too large.
The process for etching the flat layer 211 at the bottom of the third opening 231 and the fourth opening 232 includes an anisotropic dry etching process, and the parameters include: the gas employed is H2、N2、CO2And O2Any one or a combination of several of them.
In this embodiment, the method further includes: in the process of etching the bottom planarization layer 211 of the third opening 231 and the fourth opening 232, the bottom anti-reflection layer 212 and the photoresist layer 220 are removed.
Referring to fig. 8, the layer to be etched 200 at the bottom of the third opening 231 and the layer to be etched 200 at the bottom of the fourth opening 232 are etched, a first trench 251 is formed in the dense region a of the layer to be etched 200, and a second trench 252 is formed in the sparse region B of the layer to be etched 200.
In this embodiment, the layer to be etched 200 at the bottom of the fifth opening 241 and the sixth opening 242 is etched using the planarization layer 211 as a mask, so as to form the first trench 251 and the second trench 252.
The process for etching the layer to be etched 200 at the bottom of the third opening 231 and the layer to be etched 200 at the bottom of the fourth opening 232 includes an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
After the first groove 251 and the second groove 252 are formed, the planarization layer 211 is removed.
Since the sixth opening 242 is prevented from being excessively large with respect to the opening of the fifth opening 241, the opening of the second groove 252 is prevented from being excessively large with respect to the opening of the first groove 251, and the dimensional uniformity of the second groove 252 and the first groove 251 is improved. Thereby improving the performance of the semiconductor device.
Accordingly, the present embodiment also provides a semiconductor device formed by the above method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor device, comprising:
providing a layer to be etched, wherein the layer to be etched comprises a sparse area and a dense area, the density of devices formed on the dense area is greater than that of devices formed on the sparse area, a bottom anti-reflection layer and a photoresist layer positioned on the surface of the bottom anti-reflection layer are arranged on the layer to be etched, a first opening and a second opening penetrating through the photoresist layer are formed in the photoresist layer, the first opening is positioned on the dense area, and the second opening is positioned on the sparse area;
carrying out plasma treatment on the side wall of the photoresist layer, wherein the plasma treatment process also etches the bottom anti-reflection layers at the bottoms of the first opening and the second opening to ensure that the surfaces of the bottom anti-reflection layers are sunken, and the sunken degree of the surface of the bottom anti-reflection layer at the bottom of the second opening is greater than that of the bottom anti-reflection layer at the bottom of the first opening;
after plasma treatment is carried out, etching the bottom anti-reflection layers at the bottoms of the first opening and the second opening, forming a third opening penetrating through the bottom anti-reflection layer in the bottom anti-reflection layer at the bottom of the first opening, forming a fourth opening penetrating through the bottom anti-reflection layer in the bottom anti-reflection layer at the bottom of the second opening, wherein the bottom width of the fourth opening is smaller than the bottom width of the third opening;
and etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, forming a first groove in the dense region of the layer to be etched, and forming a second groove in the sparse region of the layer to be etched.
2. The method according to claim 1, wherein a process gas used for the plasma treatment comprises a fluorocarbon-based gas, and a molar ratio of the fluorocarbon-based gas to the process gas is 3/20 or less.
3. The method for forming a semiconductor device according to claim 2, wherein the fluorocarbon-based gas comprises CF4。
4. The method for forming a semiconductor device according to claim 2, wherein a molar ratio of the fluorocarbon-based gas to the process gas is 1/50 to 3/20.
5. The method of claim 2, wherein the process gas further comprises H2One or the combination of any of Ar and HBr.
6. The method of claim 2, wherein the parameters of the plasma process further comprise: the plasma power is 20-2000W, and the pressure of the chamber is 3-500 mtorr.
7. The method of claim 1, wherein after the plasma treatment is performed and before the bottom anti-reflection layer at the bottom of the first opening and the second opening is etched, the bottom anti-reflection layer surface at the bottom of the first opening has a first recess having a first bottom surface and a first side around the first bottom surface, the bottom anti-reflection layer surface at the bottom of the second opening has a second recess having a second bottom surface and a second side around the second bottom surface; the second bottom surface is lower than the first bottom surface, and the dimension of the second bottom surface in the direction perpendicular to the second opening side wall is smaller than or equal to the dimension of the first bottom surface in the direction perpendicular to the first opening side wall.
8. The method of claim 1, wherein after the plasma treatment and before etching the bottom anti-reflection layer at the bottom of the first opening and the second opening, the bottom anti-reflection layer at the bottom of the first opening has a first recess on a surface thereof, and the bottom anti-reflection layer at the bottom of the second opening has a second recess on a surface thereof; in a section of the first recess, which is perpendicular to the side wall of the first opening, the first recess is provided with a first bottom point and first top points positioned on two sides of the first bottom point, the height from the first top point to the first bottom point is gradually reduced, and a first arc line is arranged from the first top point to the first bottom point; in a section of the second recess perpendicular to the side wall of the second opening, the second recess has a second bottom point and second vertexes located on two sides of the second bottom point, the height from the second vertex to the second bottom point is gradually reduced, a second arc line is arranged from the second vertex to the second bottom point, and the second bottom point is lower than the first bottom point.
9. The method for forming a semiconductor device according to claim 1, wherein a planarization layer is further provided between the bottom anti-reflection layer and the layer to be etched; the method for forming the semiconductor device further comprises the following steps: before etching the layer to be etched at the bottom of the third opening and the layer to be etched at the bottom of the fourth opening, etching the flat layer at the bottom of the third opening and the flat layer at the bottom of the fourth opening, forming a fifth opening in the flat layer in the dense area, forming a sixth opening in the flat layer in the sparse area, wherein the etching rate of the process for etching the flat layer at the bottom of the third opening and the fourth opening to the flat layer is greater than the etching rate of the bottom anti-reflection layer; and etching the layer to be etched by using the flat layer as a mask to form the first groove and the second groove.
10. The method of claim 9, wherein the process of etching the third opening and the fourth opening bottom planarization layer comprises an anisotropic dry etching process, and the parameters comprise: the gas employed is H2、N2、CO2And O2Any one or a combination of several of them.
11. The method as claimed in claim 9, wherein the etching process comprises an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
12. The method for forming a semiconductor device according to claim 9, further comprising: removing the bottom anti-reflection layer and the photoresist layer in the process of etching the bottom flat layers of the third opening and the fourth opening; and removing the flat layer after the first groove and the second groove are formed.
13. The method of claim 9, wherein a material of the planarization layer is an organic polymer or amorphous carbon.
14. The method as claimed in claim 1, wherein the step of etching the bottom anti-reflection layer at the bottom of the first opening and the second opening to form the third opening and the fourth opening is an anisotropic dry etching process, and the parameters include: the adopted etching gas comprises fluorocarbon-based gas, and the molar ratio of the fluorocarbon-based gas to the etching gas is more than 30%.
15. The method as claimed in claim 1, wherein the material of the bottom anti-reflection layer is silicon oxide or silicon-containing oxycarbide.
16. The method as claimed in claim 1, wherein the layer to be etched is made of a low-K dielectric material or an ultra-low-K dielectric material.
17. A semiconductor device formed according to the method of any one of claims 1 to 16.
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