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CN109390353A - Semiconductor element and preparation method thereof - Google Patents

Semiconductor element and preparation method thereof Download PDF

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Publication number
CN109390353A
CN109390353A CN201710690789.1A CN201710690789A CN109390353A CN 109390353 A CN109390353 A CN 109390353A CN 201710690789 A CN201710690789 A CN 201710690789A CN 109390353 A CN109390353 A CN 109390353A
Authority
CN
China
Prior art keywords
layer
semiconductor element
dielectric layer
semiconductor
passive device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710690789.1A
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Chinese (zh)
Inventor
李文深
智晓愿
陈星星
温晋炀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
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United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN201710690789.1A priority Critical patent/CN109390353A/en
Priority to US15/691,757 priority patent/US20190051666A1/en
Publication of CN109390353A publication Critical patent/CN109390353A/en
Pending legal-status Critical Current

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention discloses a kind of semiconductor element and preparation method thereof.The semiconductor element includes: a substrate, has a leading flank and a dorsal surface, and wherein the substrate includes semi-conductor layer and a buried insulating layer；An at least transistor is set on the semiconductor layer；One interlayer dielectric layer is set to the leading flank, covers an at least transistor；One contact structures run through the interlayer dielectric layer, the semiconductor layer and the buried insulating layer；One metal silicide layer covers an end face of the contact structures on the dorsal surface；And a passive device, on the dorsal surface of the substrate, wherein the contact structures are electrically connected to the passive device.

Description

Semiconductor element and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, more particularly to it is a kind of it is silicon-coated insulated (silicon-on-insulator, SOI) semiconductor element and preparation method thereof.
Background technique
Compared to semiconductor element of the building in silicon base, using it is silicon-coated insulated (silicon-on-insulator, SOI) semiconductor element of technology manufacture can usually show certain performance improvement.In general, soi chip includes partly leading Body element layer (semiconductor device layer), substrate layer (base layer) and such as embedment oxide or BOX The insulating layer of layer, wherein insulating layer is physically separated and electrically isolates semiconductor element layer and substrate layer.Circuit element such as crystal Pipe etc. is fabricated in semiconductor element layer.
In the semiconductor element using SOI technology manufacture, it is sometimes desirable to which at the back side of chip, (back side makes work for processing Skill), further to produce other circuit elements, for example, the passive devices such as inductance or capacitor.Therefore, in need in chip It is middle to form the conductive contact structure (body contact) for being capable of being electrically connected to chip back.However, the prior art is in order to protect Conductive contact structure is made in the process not by the erosion of etchant such as tetramethylammonium hydroxide (TMAH), needs separately protect with insulating liner Electric contact structure is protected and led, the shortcomings that this practice is that conductive contact structure can generate apparent charge inducing effect.
Summary of the invention
The main purpose of the present invention is to provide semiconductor elements of a kind of improvement and preparation method thereof, can solve above-mentioned The deficiencies in the prior art and disadvantage.
In order to achieve the above object, the present invention provides a kind of semiconductor element, include: a substrate has a leading flank and a back Side, wherein substrate includes semi-conductor layer and a buried insulating layer；An at least transistor is set on semiconductor layer；One layer Between dielectric layer, be set to leading flank, covering transistor；One contact structures, through interlayer dielectric layer, semiconductor layer and embedment insulation Layer；One metal silicide layer covers an end face of contact structures on dorsal surface；And a passive device, set on the back side of substrate On face, wherein contact structures are electrically connected to passive device.
An embodiment according to the present invention, contact structures include a conductive liner and a metal layer, and wherein the metal layer is by this Conductive liner surrounds.
An embodiment according to the present invention, wherein conductive liner directly contacts semiconductor layer.
An embodiment according to the present invention, wherein metal silicide layer includes nickle silicide, cobalt silicide or tungsten silicide.
An embodiment according to the present invention, wherein passive device includes an inductance, a capacitor or a resistance.
An embodiment according to the present invention, wherein metal silicide layer directly contacts an engagement pad of passive device.
An embodiment according to the present invention wherein additionally comprises one first dielectric layer and one second dielectric layer on dorsal surface, wherein Engagement pad is set in the first dielectric layer, and passive device is set in the second dielectric layer.
The present invention separately provides a kind of method for making semiconductor element.A silicon-coated insulated chip is provided first, before having one Side and a dorsal surface, wherein silicon-coated insulated chip includes semi-conductor layer, a buried insulating layer and a substrate layer.Then at partly leading An at least transistor is formed on body layer.An interlayer dielectric layer is formed on leading flank, makes its covering transistor.It is subsequently formed one Through the contact hole of interlayer dielectric layer, semiconductor layer and buried insulating layer, wherein the bottom in contact hole manifests portions of substrate layer. A metal silicide layer is formed on the portions of substrate layer that the bottom in contact hole is manifested.Hole will be contacted again with a conductive material It fills up, is thusly-formed a contact structures.A passive device is formed on dorsal surface, wherein contact structures are electrically connected to passive member Part.
For above-mentioned purpose of the invention, feature and advantage can be clearer and more comprehensible, preferred embodiment is cited below particularly, and match Appended attached drawing is closed, is described in detail below.However following preferred embodiment and attached drawing it is only for reference with illustrate to use, not For the present invention is limited person.
Detailed description of the invention
Fig. 1 to Figure 14 shows for a kind of section of the production method of semiconductor element depicted in an embodiment according to the present invention It is intended to, wherein Figure 14 shows semiconductor element cross-section structure of the invention.
Main element symbol description
100 silicon-coated insulated chips (substrate)
100a leading flank
100b dorsal surface
101 semiconductor layers
102 buried insulating layers
103 substrate layers
110 transistors
111 grids
112 gate dielectrics
113 source doping regions
114 drain doping regions
115 clearance walls
121 etching stopping layers
122 interlayer dielectric layers
125,126,127,128 contact hole
The bottom 125a
131 metal layers
132 metal silicide layers
140 conductive materials
141 conductive liners
142 metal layers
145,146,147,148 contact structures
151 barrier oxide layers
160 conductive materials
161 conductive liners
162 metal layers
170 dielectric layer between metal layers
171 passivation layers (protective layer)
180 metal interconnecting structures
200 element wafers
201 temporary bases
301 first dielectric layers
302 second dielectric layers
312 engagement pads
320 passive devices
306 passivation layers (protective layer)
Specific embodiment
Hereinafter, illustrate details with reference to the accompanying drawings, the content in those attached drawings also constitutes the one of specification datail description Part, and be painted with the special case describing mode of the practicable embodiment.Examples below, which has described enough details, makes this The general technology personage in field is implemented.
Certainly, other embodiments can also be adopted, or are made under the premise of not departing from embodiment described in text any Change in structural, logicality and electrical property.Therefore, following detailed description is not considered as limiting, conversely, wherein institute The embodiment for including will be defined by appended claims.
The present invention discloses silicon-coated insulated (silicon-on-insulator, the SOI) semiconductor element of one kind and its production side Method.The soi semiconductor element, for example, it can be used in radio frequency (RF) Element Technology field, but not limited to this.
Fig. 1 to Figure 14 is please referred to, for a kind of production side of semiconductor element depicted in an embodiment according to the present invention The diagrammatic cross-section of method.As shown in Figure 1, providing a silicon-coated insulated chip (or substrate) 100, there is the back of a leading flank 100a and one Side 100b, wherein silicon-coated insulated chip includes semi-conductor layer 101, a buried insulating layer 102 and a substrate layer 103.Embedment Insulating layer 102 is physically separated and electrically isolates semiconductor layer 101 and substrate layer 103.
An embodiment according to the present invention, semiconductor layer 101 may include silicon, such as monocrystalline silicon, and buried insulating layer 102 can be with Including silica, substrate layer 103 may include silicon, but not limited to this.
Then, an at least transistor 110 is formed on semiconductor layer 101.It is to be understood that can be on semiconductor layer 101 Multiple transistors or other electronic components are formed with, are illustrated to simplify, only a single a transistor 110 illustrates in figure.According to this An embodiment is invented, transistor 110 may include a grid 111, a gate dielectric 112 is set to grid 111 and semiconductor layer Between 101, a source doping region 113 and a drain doping region 114.A clearance wall can be formed on the side wall of grid 111 115。
Then, an etching stopping layer 121 is sequentially formed on the semiconductor layer 101 of leading flank 100a and on transistor 110 An and interlayer dielectric layer 122.An embodiment according to the present invention, etching stopping layer 121 can be silicon nitride layer, but not limited to this. An embodiment according to the present invention, interlayer dielectric layer 122 can be silicon dioxide layer, but not limited to this.
As shown in Fig. 2, being subsequently formed one through interlayer dielectric layer 122, etching stopping layer 121, semiconductor layer 101 and embedment The contact hole 125 of insulating layer 102, wherein the bottom 125a in contact hole 125 manifests the substrate layer 103 of part.
As shown in Figures 3 to 5, a metal silicide manufacture craft is then carried out.First in the interlayer dielectric layer of leading flank 100a A metal layer 131 (Fig. 3) is formed on 122 and on the inner surface in contact hole 125, for example, nickel, cobalt or tungsten etc..Then, it is fast to carry out one Speed heat annealing (RTP) manufacture craft forms one on the substrate layer 103 for the part that the bottom 125a in contact hole 125 is manifested Metal silicide layer 132 (Fig. 4).An embodiment according to the present invention, metal silicide layer 132 may include nickle silicide, cobalt silicide or silicon Change tungsten, but not limited to this.Then, unreacted residual metallic layer 131 is removed, the bottom 125a in contact hole 125 leaves silicon Change metal layer 132 (Fig. 5).
As shown in fig. 6, contact hole 125 is filled up with a conductive material 140 again, for example, conductive material 140 may include one Conductive liner 141 and a metal layer 142, wherein being surrounded in contact 125 inner metal layer 142 of hole by conductive liner 141.According to this An embodiment is invented, for example, metal layer 142 is a tungsten metal layer.Conductive liner 141 directly contacts semiconductor layer 101.
As shown in fig. 7, a tungsten metallochemistry mechanical lapping manufacture craft is then carried out, it will be more on interlayer dielectric layer 122 The remaining grinding of conductive material 140 removal, so forms a contact structures 145 in contact hole 125.
As shown in figure 8, after completing aforementioned tungsten metallochemistry mechanical lapping manufacture craft, then in interlayer dielectric layer A barrier oxide layer 151 is formed on 122 and on the surface of contact structures 145.
As shown in figure 9, then with etching side in barrier oxide layer 151, interlayer dielectric layer 122 and etching stopping layer 121 Method forms the contact hole 126,127 and 128 on transistor 110, wherein contact hole 126 is connected to grid 111, contact hole 127 is connected to Source doping region 113, contact hole 128 are connected to drain doping region 114.Hole 126,127 and 128 will be contacted again with a conductive material 160 fill up, for example, conductive material 160 may include a conductive liner 161 and a metal layer 162.One implements according to the present invention Example, for example, metal layer 162 is a tungsten metal layer.
As shown in Figure 10, a tungsten metallochemistry mechanical lapping manufacture craft is then carried out, it will be more on interlayer dielectric layer 122 Remaining conductive material 160 and barrier oxide layer 151 grinding removal, be thusly-formed be electrically connected grid 111, source doping region 113, The contact structures 146,147,148 of drain doping region 114.
As shown in figure 11, metal layer then is formed on interlayer dielectric layer 122 and in contact structures 145,146,147,148 Between dielectric layer (inter-metal dielectric layer) 170 and metal interconnecting structure 180.Wherein metal interlevel is situated between Electric layer 170 may include multilayer dielectric material or insulating layer, and metal interconnecting structure 180 can be respectively formed at the multilayer In dielectric material or insulating layer.Metallization manufacture craft on this leading flank 100a is known skill, therefore its details does not repeat separately. Then, a passivation layer (or protective layer) 171 can be formed on dielectric layer between metal layers 170.At this point, completing leading flank 100a On manufacturing process steps, formed an element wafer 200.
As shown in figure 12, then a temporary base 201 is bonded on the passivation layer 171 on interlayer dielectric layer 122.For side Just illustrate it is subsequent in the manufacturing process steps carried out on dorsal surface, Figure 12 in Figure 11 element wafer 200 above and below invert, Temporary base 201 is in bottom at this time, and substrate layer 103 is in the top.
As shown in figure 13, after the engagement step for completing temporary base 201, then thinning substrate layer 103, until silication gold Belong to layer 132 to be exposed at a time.An embodiment according to the present invention, the practice of thinning substrate layer 103 can use grinding or etching etc. Mode, but not limited to this.An embodiment according to the present invention, substrate layer 103 can manifest embedment insulation by complete grinding removal Layer 102, but not limited to this.
As shown in figure 14, then in one first dielectric layer 301 of formation on the buried insulating layer 102 of dorsal surface 100b.Then, An engagement pad 312 is formed on the first dielectric layer 301, wherein engagement pad 312 directly contacts metal silicide layer 132.According to this hair A bright embodiment, engagement pad 312 can wrap cupric, but not limited to this.Engagement pad 312, which can be, inlays manufacture craft shape using copper At.
Then, one second dielectric layer 302 is formed on the first dielectric layer 301.In addition, separately in second on dorsal surface 100b A passive device 320 is formed in dielectric layer 302, wherein passive device 320 includes an inductance, a capacitor or a resistance.Second is situated between Electric layer 302 may include multilayer dielectric material or insulating layer, and passive device 320 can be layered and be formed in the multilayer dielectric material In material or insulating layer.Passive device manufacture craft on this dorsal surface 100b is known skill, therefore its details does not repeat separately.
An embodiment according to the present invention, contact structures 144 are electrically connected to passive device 320, wherein passive device 320 via Engagement pad 312 and metal silicide layer 132 are electrically connected to contact structures 144.A passivation is finally formed on the second dielectric layer 302 Layer (or protective layer) 306.Finally, temporary base 201 can be removed, that is, complete the method for present invention production semiconductor element.
Semiconductor element of the invention as can be seen from Figure 14 includes: a substrate 100, has a leading flank 100a and one Dorsal surface 100b, wherein substrate 100 includes semi-conductor layer 101 and a buried insulating layer 102；An at least transistor 110, if In on semiconductor layer 101；One interlayer dielectric layer 122 is set to leading flank 100a, covering transistor 110；One contact structures 145, are passed through Wear interlayer dielectric layer 122, semiconductor layer 101 and buried insulating layer 102；One metal silicide layer 132, covers on dorsal surface 100b A firmly end face of contact structures 145；And a passive device 320, on the dorsal surface 100b of substrate 100, wherein contact structures 145 are electrically connected to passive device 320.
An embodiment according to the present invention, contact structures 145 include a conductive liner 141 and a metal layer 142, wherein metal Layer 142 is surrounded by conductive liner 141.
An embodiment according to the present invention, wherein conductive liner 141 directly contacts semiconductor layer 101.
An embodiment according to the present invention, wherein metal silicide layer 132 includes nickle silicide, cobalt silicide or tungsten silicide.
An embodiment according to the present invention, wherein passive device 320 includes an inductance, a capacitor or a resistance.
An embodiment according to the present invention, wherein metal silicide layer 132 directly contacts an engagement pad 312 of passive device 320.
An embodiment according to the present invention wherein additionally comprises one first dielectric layer 301 and one second dielectric on dorsal surface 100b Layer 302, wherein engagement pad 312 is set in the first dielectric layer 301, and passive device 320 is set in the second dielectric layer 302.
The above description is only a preferred embodiment of the present invention, all equivalent changes done according to the claims in the present invention with repair Decorations, should all belong to the scope of the present invention.

Claims (14)

1. a kind of semiconductor element, includes:
Substrate has a leading flank and a dorsal surface, and wherein the substrate includes semiconductor layer and buried insulating layer；
An at least transistor is set on the semiconductor layer；
Interlayer dielectric layer is set to the leading flank, covers an at least transistor；
Contact structures run through the interlayer dielectric layer, the semiconductor layer and the buried insulating layer；
Metal silicide layer covers an end face of the contact structures on the dorsal surface；And
Passive device, on the dorsal surface of the substrate, wherein the contact structures are electrically connected to the passive device.
2. semiconductor element as described in claim 1, wherein the contact structures include conductive liner and metal layer, wherein the gold Belong to layer to be surrounded by the conductive liner.
3. semiconductor element as claimed in claim 2, wherein the conductive liner directly contacts the semiconductor layer.
4. semiconductor element as described in claim 1, wherein the metal silicide layer includes nickle silicide, cobalt silicide or tungsten silicide.
5. semiconductor element as described in claim 1, wherein the passive device includes inductance, capacitor or resistance.
6. semiconductor element as described in claim 1, wherein the metal silicide layer directly contacts a contact of the passive device Pad.
7. semiconductor element as described in claim 1 wherein additionally comprises the first dielectric layer and the second dielectric layer on the dorsal surface, Wherein the engagement pad is set in first dielectric layer, which is set in second dielectric layer.
8. a kind of method for making semiconductor element, includes:
One silicon-coated insulated chip is provided, have a leading flank and a dorsal surface, wherein the silicon-coated insulated chip comprising semiconductor layer, Buried insulating layer and substrate layer；
An at least transistor is formed on the semiconductor layer；
An interlayer dielectric layer is formed on the leading flank, it is made to cover an at least transistor；
A contact hole for running through the interlayer dielectric layer, the semiconductor layer and the buried insulating layer is formed, wherein the bottom in the contact hole Portion manifests the part substrate layer；
A metal silicide layer is formed on the substrate layer of the part that the bottom in the contact hole is manifested；
The contact hole is filled up with a conductive material, is thusly-formed a contact structures；And
A passive device is formed on the dorsal surface, wherein the contact structures are electrically connected to the passive device.
9. the method for production semiconductor element as claimed in claim 8, wherein additionally comprising:
A temporary base is engaged on the interlayer dielectric layer；And
Thinning substrate layer, until the metal silicide layer is exposed at a time.
10. the method for production semiconductor element as claimed in claim 9, wherein additionally comprising:
One first dielectric layer is formed on the dorsal surface；
An engagement pad is formed in first dielectric layer, wherein the engagement pad directly contacts the metal silicide layer；
One second dielectric layer is formed on first dielectric layer；And
A passivation layer is formed on second dielectric layer, wherein the passive device is electrically connected via the engagement pad and the metal silicide layer It is connected to the contact structures.
11. the method for production semiconductor element as claimed in claim 10, wherein the passive device includes inductance, capacitor or electricity Resistance.
12. the method for production semiconductor element as claimed in claim 8, wherein the contact structures include conductive liner and metal Layer, wherein the metal layer is surrounded by the conductive liner.
13. the method for production semiconductor element as claimed in claim 12, wherein the conductive liner directly contacts the semiconductor Layer.
14. the method for production semiconductor element as claimed in claim 8, wherein the metal silicide layer includes nickle silicide, silication Cobalt or tungsten silicide.
CN201710690789.1A 2017-08-14 2017-08-14 Semiconductor element and preparation method thereof Pending CN109390353A (en)

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Application publication date: 20190226