CN109388839B - Clock system performance analysis method and device - Google Patents
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Abstract
The invention provides a clock system performance analysis method and device. The method comprises the following steps: the method comprises the steps of obtaining parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist, adding delay in parameters corresponding to each last-stage inverter in the first simulation netlist to form a second simulation netlist with added delay, wherein the delay is obtained according to ideal delay of inverters on each clock path and fluctuation delay of the inverters, the fluctuation delay of the inverters is caused by on-chip fluctuation, and clock deviation of the clock system to be analyzed is determined according to the second simulation netlist and the parasitic parameters of the interconnection lines.
Description
Technical Field
The present invention relates to computer technology, and in particular, to a method and apparatus for analyzing clock system performance.
Background
In the field of integrated circuit design, clock systems are critical to the proper functioning of integrated circuits. As high performance integrated circuits become larger in size, the complexity increases and the demand for clock system performance (e.g., clock skew) increases.
At present, complete Monte Carlo simulation is performed mainly in a fully customized mode, and clock deviation of a clock system is analyzed.
However, the above analysis method requires a long time and has low efficiency, and factors considered in the simulation process are not comprehensive, so that clock deviation of the clock system cannot be accurately analyzed.
Disclosure of Invention
The invention provides a clock system performance analysis method and device, which are used for solving the technical problems that the time required is long, the efficiency is low and the clock deviation cannot be accurately analyzed when the clock deviation analysis of a clock system is performed at present.
In a first aspect, the present invention provides a method for analyzing performance of a clock system, including:
obtaining parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of all inverters in the clock system;
adding time delay in parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist to form a second simulation netlist with added time delay; the time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path, and the fluctuation time delay of the inverter is caused by on-chip fluctuation;
and determining clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
In the method as described above, the determining the clock bias of the clock system to be analyzed according to the second simulated netlist and the parasitic parameters of the interconnect line includes:
determining a sample of the time delay of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining statistics of clock deviation of the clock system to be analyzed according to the time delay samples.
In the method as shown above, after determining the statistic of the clock bias of the clock system to be analyzed according to the sample of the time delay, the method further includes:
and determining whether the design conservation quantity of the clock system to be analyzed is reasonable or not according to the statistic of the clock deviation.
In the method as shown above, adding a delay to a parameter corresponding to a last-stage inverter of each clock path in the first simulated netlist, and before forming a second simulated netlist after adding the delay, the method further includes:
obtaining the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
acquiring the fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple delay of each inverter caused by the on-chip ripple is subject to normal distribution.
In the method as above, the obtaining the parasitic parameters of the interconnect line of the clock system to be analyzed and the first simulation netlist includes:
obtaining parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and obtaining the first simulation netlist through a circuit simulation tool.
In a second aspect, the present invention provides a clock system performance analysis apparatus, comprising:
the first acquisition module is used for acquiring parasitic parameters of the interconnection line of the clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of all inverters in the clock system;
the adding module is used for adding time delay into parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist to form a second simulation netlist with added time delay; the time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path, and the fluctuation time delay of the inverter is caused by on-chip fluctuation;
and the first determining module is used for determining clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
In the apparatus as shown above, the first determining module is specifically configured to:
determining a sample of the time delay of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining statistics of clock deviation of the clock system to be analyzed according to the time delay samples.
In the apparatus as shown above, the apparatus further comprises:
and the second determining module is used for determining whether the design conservation quantity of the clock system to be analyzed is reasonable or not according to the statistic of the clock deviation.
In the apparatus as shown above, the apparatus further comprises:
the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
the third acquisition module is used for acquiring the fluctuation time delay of each phase inverter caused by on-chip fluctuation through a probability density function; wherein the ripple delay of each inverter caused by the on-chip ripple is subject to normal distribution.
In the apparatus as shown above, the first obtaining module is specifically configured to:
obtaining parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and obtaining the first simulation netlist through a circuit simulation tool.
In a third aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the clock system performance analysis method provided in the first aspect above.
According to the clock system performance analysis method and device, parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist are obtained, the topology structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of each clock path is connected with a clock grid, the clock grid is connected with a load, the first simulation netlist comprises a connection relation of each inverter in the clock system, a delay is added in parameters corresponding to the last stage of each inverter in the first simulation netlist, a second simulation netlist with the delay added is formed, the delay is obtained according to ideal delay of the inverters on each clock path and fluctuation delay of the inverters, the fluctuation delay of the inverters is caused by fluctuation on a sheet, and clock deviation of the clock system to be analyzed is determined according to the parasitic parameters of the second simulation netlist and the interconnection lines.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic flow chart of an embodiment of a method for analyzing clock system performance according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a clock system to be analyzed according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the time delay in the clock system shown in FIG. 2;
fig. 4 is a schematic structural diagram of an embodiment of a clock system performance analysis device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Fig. 1 is a flowchart of an embodiment of a clock system performance analysis method according to an embodiment of the present invention. As shown in fig. 1, the method for analyzing clock system performance provided by the embodiment of the invention includes the following steps:
s101: and obtaining parasitic parameters of interconnection lines of the clock system to be analyzed and a first simulation netlist.
Wherein the topology of the clock system is a grid structure. The clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, and the clock grid is connected with a load. The first simulated netlist includes a connection relationship of inverters in a clock system.
Specifically, fig. 2 is a schematic structural diagram of a clock system to be analyzed in an embodiment of the present invention. It should be noted that, the clock system generally includes a global clock (global clock) system, a local clock (local clock) system, and a local clock (local clock) system. In high performance designs, the local clock system employs a clock mesh (clock mesh) structure because the clock mesh structure can reduce clock skew and attenuate on-chip ripple (on-chip variation) effects on the clock system. The clock system to be analyzed in the embodiment of the invention is a regional clock system with a topological structure of a grid structure.
As shown in fig. 2, the clock system includes a front-end drive module 21, a clock grid 22, and a load 23. The front stage driving module 21 includes a plurality of stages of inverters 211 therein. Illustratively, the inverter 211 in the front-stage drive module 21 is shown as three stages in fig. 2. The plurality of inverters 211 are connected in a tree structure. In the embodiment of the invention, the inverter defining the root node is a first-stage inverter, and the inverter at the tail end is a last-stage inverter. In the front-stage driving module 21, each inverter 211 other than the first-stage inverter is connected to one previous-stage inverter upward and to at least two next-stage inverters downward. One end of the clock grid 22 is connected to each last-stage inverter, and the other end is connected to the load of the clock system. The clock grid 22 is made up of metal connection lines. The load 23 is the destination of the clock system. The front stage driving module 21 is composed of a cascade of several stages of inverters 211. The front stage driving module 21 includes a plurality of clock paths. The clock path in the embodiment of the invention is a path from the inverter of the first stage to the inverter of the last stage through the inverters of the intermediate stages.
Embodiments of the invention may be performed by a computing device having computing capabilities, e.g., a server, personal computer (Personal Computer, PC).
Optionally, in S101, the computing device may obtain the parasitic parameters of the interconnect line through a parasitic parameter extraction tool. The parasitic parameter extraction tool may be starRC. Parasitic parameters of the interconnect line include resistive parameters, capacitive parameters, and inductive parameters. Parasitic parameters of the interconnect line will affect propagation delay and flip time of the clock signal on the interconnect line, and therefore, when analyzing the performance of the clock system, it is necessary to extract the parasitic parameters of the interconnect line. StarRC is a parasitic parameter extraction tool for an integrated circuit layout interconnect, which is a well-established tool, and the specific acquisition process is not described here. The computing device may obtain a first simulated netlist through a circuit simulation tool. The circuit emulation tool may be HSPICE. HSPICE is a general circuit simulation program that performs simulations of circuit performance, such as steady state analysis, transient state analysis, and frequency domain analysis, in integrated circuit designs. Optionally, the first simulated netlist further includes a parasitic parametric model of transistors in each inverter and a load capacitance of the clock system. The HSPICE model of the transistor abstracts the parameter details of the transistor into the interconnection relation of the resistor and the capacitor. The inverter in the front-stage driving module 21 in fig. 2 is composed of a plurality of transistors. Thus, the connection relationship of each inverter in the clock system, the parasitic parametric model of the transistors in each inverter, and the load capacitance of the clock system may be included in the first simulated netlist.
After the parasitic parameters of the interconnection lines of the clock system and the first simulation netlist are obtained, the clock system can be represented by the parasitic parameters of the interconnection lines and the first simulation netlist.
S102: and adding time delay into parameters corresponding to the inverter of the last stage of each clock path in the first simulation netlist to form a second simulation netlist with added time delay.
The time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path. The ripple delay of the inverter is caused by on-chip ripple.
Specifically, in the embodiment of the invention, when clock deviation analysis of a clock system is performed, time delay caused by on-chip fluctuation is considered. The source of on-chip fluctuations includes three aspects: 1. process (process) differences between different wafers and process differences for different areas of the same wafer; 2. noise of the power supply or instability of the power supply; 3. temperature fluctuation: the operating speeds of the transistors are different in different ambient temperatures; temperature differences in different areas of the same chip. On-chip fluctuation can cause the time delay of the device to change, so that the performance of the actually produced clock system is greatly different from the performance obtained by the static time sequence analysis method. Therefore, when the clock system performance analysis is carried out, the accuracy of the clock bias analysis can be improved by considering the time delay caused by on-chip fluctuation.
In the embodiment of the invention, the delay is only added in the parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist. Fig. 3 is a schematic diagram of the time delay in the clock system shown in fig. 2. Each inverter has two delays: ideal delay of the inverter and ripple delay of the inverter caused by on-chip ripple. As shown in a diagram of fig. 3, the delay of the first stage inverter is the ideal delay D 0 With a fluctuation time delay delta 0 The sum, i.e. the delay of the first stage inverter is D 0 +Δ 0 . In other words, the delay of each inverter is the ideal delay D q And the corresponding fluctuation time delay delta q And (2) sum: d (D) q +Δ q 。
The ideal delay of each inverter can be obtained by a static time sequence analysis method. The ripple delay of each inverter can be obtained by two implementations:
the first way is: and obtaining the fluctuation time delay of each inverter caused by on-chip fluctuation in an experimental mode. The quantitative relationship between the ripple time delay and the ideal time delay may be determined experimentally, for example, the ripple time delay may be 30% of the ideal time delay. The second mode is as follows: and acquiring the fluctuation time delay of each inverter caused by the on-chip fluctuation through the probability density function. Wherein the ripple delay of each inverter caused by on-chip ripple obeys normal distribution. Alternatively, the ripple delay may also follow other profiles.
For each last-stage inverter, there will be a plurality of inverters on its corresponding clock path, and added to the first simulated netlist is the sum of the ideal delays of all the inverters on the clock path and the ripple delays corresponding to all the inverters. It should be noted that, all the inverters on the clock paths corresponding to the last-stage inverter include the last-stage inverter itself.
As shown in b diagram in fig. 3, the delay added in the parameters corresponding to the inverter 33 in the first simulated netlist is: the sum of the ideal delay and ripple delay of inverter 30, the ideal delay and ripple delay of inverter 31, and the ideal delay and ripple delay of inverter 33: d (D) 0 +Δ 0 +D 1 +Δ 1 +D 3 +Δ 3 . The delay added to the parameters corresponding to inverter 34 in the first simulated netlist is: the sum of the ideal delay and ripple delay of inverter 30, the ideal delay and ripple delay of inverter 31, and the ideal delay and ripple delay of inverter 34: d (D) 0 +Δ 0 +D 1 +Δ 1 +D 4 +Δ 4 . The delay added in the parameters corresponding to the inverter 35 in the first simulated netlist is: the sum of the ideal time delay and ripple time delay of inverter 30, the ideal time delay and ripple time delay of inverter 32, and the ideal time delay and ripple time delay of inverter 35: d (D) 0 +Δ 0 +D 2 +Δ 2 +D 5 +Δ 5 . The delay added to the parameters corresponding to inverter 36 in the first simulated netlist is: the sum of the ideal time delay and ripple time delay of inverter 30, the ideal time delay and ripple time delay of inverter 32, and the ideal time delay and ripple time delay of inverter 36: d (D) 0 +Δ 0 +D 2 +Δ 2 +D 6 +Δ 6 . Namely, by means of linear superposition, the fluctuation time delay caused by on-chip fluctuation is injected into the parameters corresponding to the inverter of the last stage.
S103: and determining clock deviation of the clock system to be analyzed according to the second simulation netlist and parasitic parameters of the interconnection lines.
Specifically, the computing device may perform monte carlo simulation according to the second simulation netlist added with the fluctuation time delay and the ideal time delay and the parasitic parameters of the interconnection line, that is, assign a value to the random variable according to the distribution form of the random variable, and determine the clock deviation of the clock system to be analyzed, where the process may be: determining a sample of the time delay of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection lines; and determining statistics of clock deviation of the clock system to be analyzed according to the time delay samples.
More specifically, determining the time delay of the clock signal reaching the clock port of the load in the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line; determining statistics of the time delay according to the time delay of the clock signal reaching the clock port of the load; the statistics of the clock skew are determined from the statistics of the delay.
By T i Representing the delay of the clock signal reaching the clock port of load i. T (T) i Is a random variable. After the Monte Carlo simulation is completed, T can be obtained i Is a sample value of (a). By analysis of the sample, T can be obtained i Such as expectations, variances, standard deviations, etc. By T j Representing the delay of the clock signal arriving at the clock port of load j. Similarly, T can be obtained j Is a statistic of (a). Clock deviation S ij ＝T i -T j . I.e. according to T i And T j Is counted to obtain S ij Also, statistics of instantaneous deviations. In addition, the correlation between random variables can be analyzed by statistical methods such as linear regression.
The clock system of the clock grid structure is a multi-drive clock network, and the traditional static time sequence analysis method is not suitable for analyzing the clock deviation of the clock system of the grid structure, and in the existing physical design flow, a simulation method is generally used for analyzing the clock deviation of the clock system of the clock grid structure. When full-custom simulation is performed at present, the whole clock system needs to be simulated, and in order to ensure the sufficiency and completeness of the simulation, designers need to perform millions of simulations, which results in lower efficiency of clock bias analysis of the clock system. In the embodiment of the invention, as the time delay is only added in the parameters of the inverter of the last stage, and the simulation is only needed for the clock grid and the load, the large-scale simulation is not needed for the whole clock system. Therefore, the time required by simulation is shortened, and the simulation efficiency is improved.
Optionally, in the embodiment of the present invention, after determining the statistics of the clock deviation of the clock system to be analyzed according to the samples of the time delay, determining whether the design conservation amount of the clock system to be analyzed is reasonable according to the statistics of the clock deviation is further included. At present, the time delay of a device may be changed due to on-chip fluctuation, so that the performance of a clock system in actual production is greatly different from the performance analyzed by a simulation method, and a sufficient design conservation amount is usually reserved for solving the problem. If the conservation amount is too large, timing closure becomes very difficult; if the amount of conservation is too small, the influence of the fluctuation in the cover sheet cannot be covered, and the yield (yield) becomes low. By analyzing the statistics of the clock skew, the maximum average clock skew of the clock grid and the standard deviation of the clock skew can be ascertained. The standard deviation of the clock bias can be used to determine if there is enough conservative amount set aside for the effects of on-chip fluctuations on the clock system. For example, assuming that the clock skew follows a normal distribution and its standard deviation is 1 picosecond (ps), then the 6 standard deviations have a value of 6ps, and from the statistics of the clock skew, it can be determined that the clock skew is only two parts per billion away from the expected skew by a period of 6 ps. If the design conservation amount is set aside to be 7ps, i.e., the clock skew is considered to be maximally 7ps from the desired skew, then this design conservation amount is explained to be sufficient to cover the effect of the ripple on the cover on the clock system. By the method, whether the design conservation quantity is enough or not can be judged, so that the robustness of a clock system can be ensured, and the design conservation quantity can be reduced.
At present, besides the clock deviation of the clock system can be analyzed by adopting a simulation method, the clock deviation can be estimated by combining the process deviation, and particularly, the clock deviation is determined according to a generalized clock deviation calculation formula, but the generalized clock deviation calculation formula of the method ignores the characteristic of multiple drives of a clock grid, is only suitable for a tree-shaped clock system, and is not suitable for the regional clock system of the grid structure in the embodiment of the invention. In addition, the steps of dividing the transverse and longitudinal banded regions, calibrating the priority, virtually adding a single trunk into the banded regions according to the priority, estimating the total capacitance and the maximum deviation range of the grid, traversing the banded regions and the like can be adopted to estimate the clock deviation of the clock system, but compared with a simulation method, the performance analysis is missing by adopting the scheme, and the influence of on-chip fluctuation on the performance of the clock system is not considered.
According to the clock system performance analysis device provided by the embodiment of the invention, the parasitic parameters of the interconnection lines of the clock system to be analyzed and the first simulation netlist are obtained, wherein the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of each clock path is connected with a clock grid, the clock grid is connected with a load, the first simulation netlist comprises a connection relation of each inverter in the clock system, a delay is added in the parameters corresponding to the last stage of each inverter in the first simulation netlist, a second simulation netlist with the added delay is formed, the delay is obtained according to the ideal delay of the inverters on each clock path and the fluctuation delay of the inverters, the fluctuation delay of the inverters is caused by the fluctuation on a piece, and the clock deviation of the clock system to be analyzed is determined according to the parasitic parameters of the second simulation netlist and the interconnection lines, on-piece fluctuation delay is considered, the accuracy of clock deviation analysis of the clock system is improved, on the one hand, on the other hand, the clock deviation of the clock system to be analyzed is improved, the ideal time delay is only needs to be added in the first simulation netlist and the corresponding parameters of the inverters, and the clock deviation of the clock system is not required to be analyzed.
Fig. 4 is a schematic structural diagram of an embodiment of a clock system performance analysis device according to an embodiment of the present invention. As shown in fig. 4, the clock system performance analysis device provided by the embodiment of the invention includes: a first acquisition module 41, an addition module 42 and a first determination module 43.
The first obtaining module 41 is configured to obtain parasitic parameters of an interconnect line of the clock system to be analyzed and a first simulation netlist.
Wherein the topology of the clock system is a grid structure. The clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, and the clock grid is connected with a load. The first simulated netlist includes a connection relationship of inverters in a clock system.
Optionally, parasitic parametric models of transistors in each inverter and load capacitances of the clock system may also be included in the first simulated netlist.
Optionally, the first obtaining module 41 is specifically configured to: and obtaining parasitic parameters of the interconnection line through a parasitic parameter extraction tool, and obtaining a first simulation netlist through a circuit simulation tool. The parasitic parameter extraction tool may be specifically starRC and the circuit simulation tool may be specifically HSPICE.
And the adding module 42 is configured to add a delay to the parameters corresponding to the last-stage inverter of each clock path in the first simulated netlist, so as to form a second simulated netlist after adding the delay.
The time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path, and the fluctuation time delay of the inverter is caused by on-chip fluctuation.
The first determining module 43 is configured to determine a clock bias of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnect line.
Optionally, the first determining module 43 is specifically configured to: and determining a time delay sample of the clock system to be analyzed according to the second simulation netlist and parasitic parameters of the interconnection lines, and determining statistics of clock deviation of the clock system to be analyzed according to the time delay sample.
Further, the apparatus further comprises: and the second determining module is used for determining whether the design conservation quantity of the clock system to be analyzed is reasonable or not according to the statistic of the clock deviation.
Further, the apparatus further comprises: and the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by on-chip fluctuation in an experimental mode. Or the third acquisition module is used for acquiring the fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function, wherein the fluctuation time delay of each inverter caused by on-chip fluctuation is subjected to normal distribution.
The clock system performance analysis device provided by the embodiment of the invention is used for obtaining parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist by arranging a first obtaining module, wherein the topology structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, the first simulation netlist comprises a connection relation of each inverter in the clock system, an adding module is used for adding time delay into parameters corresponding to the last stage of inverter of each clock path in the first simulation netlist, a second simulation netlist after adding time delay is formed, wherein the time delay is obtained according to ideal time delay of the inverters on each clock path and fluctuation time delay of the inverters, the fluctuation time delay of the inverters is caused by on-chip fluctuation, and a first determining module is used for determining clock deviation of the clock system to be analyzed according to the parasitic parameters of the second simulation netlist and the interconnection lines, on one hand, the accuracy of the clock system to be analyzed is realized, on the aspect that when the clock system performance analysis is considered, the time delay of the clock system is improved, on-chip accuracy of the clock system is improved, on the clock system on the premise that the clock delay is not needed to be analyzed, and on the clock system time delay is increased, on the ideal time delay of the clock delay of the pair of the ideal inverter is only needs to be added to be analyzed, and the clock delay of the clock system on the clock delay is shortened, on the stage of the clock delay is not needed, and the ideal time delay is compared.
Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon. The program, when executed by a processor, implements the steps of the clock system performance analysis method provided in the embodiment shown in fig. 1.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (11)
1. A method of analyzing clock system performance, comprising:
obtaining parasitic parameters of interconnection lines of a clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of all inverters in the clock system;
adding time delay in parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist to form a second simulation netlist with added time delay; the time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path, and the fluctuation time delay of the inverter is caused by on-chip fluctuation;
and determining clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
2. The method of claim 1, wherein the determining the clock bias of the clock system to be analyzed based on the second simulated netlist and the parasitic parameters of the interconnect line comprises:
determining a sample of the time delay of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining statistics of clock deviation of the clock system to be analyzed according to the time delay samples.
3. The method of claim 2, wherein after the determining statistics of clock bias of the clock system to be analyzed from the time-lapse samples, the method further comprises:
and determining whether the design conservation quantity of the clock system to be analyzed is reasonable or not according to the statistic of the clock deviation.
4. A method according to any one of claim 1 to 3, wherein,
adding time delay in parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist, and before forming a second simulation netlist with added time delay, the method further comprises:
obtaining the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
acquiring the fluctuation time delay of each inverter caused by on-chip fluctuation through a probability density function; wherein the ripple delay of each inverter caused by the on-chip ripple is subject to normal distribution.
5. A method according to any one of claims 1-3, wherein said obtaining parasitic parameters of the interconnect lines of the clock system to be analyzed and the first simulated netlist comprises:
obtaining parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and obtaining the first simulation netlist through a circuit simulation tool.
6. A clock system performance analysis apparatus, comprising:
the first acquisition module is used for acquiring parasitic parameters of the interconnection line of the clock system to be analyzed and a first simulation netlist; the topological structure of the clock system is a grid structure, the clock system comprises a plurality of clock paths, each clock path is formed by cascading a plurality of stages of inverters, the last stage of inverter of each clock path is connected with a clock grid, the clock grid is connected with a load, and the first simulation netlist comprises the connection relation of all inverters in the clock system;
the adding module is used for adding time delay into parameters corresponding to the last-stage inverter of each clock path in the first simulation netlist to form a second simulation netlist with added time delay; the time delay is obtained according to ideal time delay of the inverter and fluctuation time delay of the inverter on each clock path, and the fluctuation time delay of the inverter is caused by on-chip fluctuation;
and the first determining module is used for determining clock deviation of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line.
7. The apparatus of claim 6, wherein the first determining module is specifically configured to:
determining a sample of the time delay of the clock system to be analyzed according to the second simulation netlist and the parasitic parameters of the interconnection line;
and determining statistics of clock deviation of the clock system to be analyzed according to the time delay samples.
8. The apparatus of claim 7, wherein the apparatus further comprises:
and the second determining module is used for determining whether the design conservation quantity of the clock system to be analyzed is reasonable or not according to the statistic of the clock deviation.
9. The apparatus according to any one of claims 6-8, further comprising:
the second acquisition module is used for acquiring the fluctuation time delay of the inverter caused by the on-chip fluctuation in an experimental mode; or,
the third acquisition module is used for acquiring the fluctuation time delay of each phase inverter caused by on-chip fluctuation through a probability density function; wherein the ripple delay of each inverter caused by the on-chip ripple is subject to normal distribution.
10. The apparatus according to any one of claims 6-8, wherein the first acquisition module is specifically configured to:
obtaining parasitic parameters of the interconnection line through a parasitic parameter extraction tool;
and obtaining the first simulation netlist through a circuit simulation tool.
11. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, carries out the method steps of any of claims 1-5.
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| TWI774381B (en) * | 2021-05-18 | 2022-08-11 | 瑞昱半導體股份有限公司 | Circuit simulation method and circuit simulation system |
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