CN109360185B - A layout test pattern extraction method, device, equipment and medium - Google Patents

Abstract

The invention discloses a layout test pattern extraction method, a device, equipment and a medium, wherein the method comprises the following steps: searching a plurality of target areas on a target layout, and setting sampling points at each target area; slicing the target layout according to sampling points, and extracting a plurality of slice graphs; dividing each slice graph into grids, and determining a description matrix of each slice graph according to the divided grids; and scanning the description matrix of each slice image by adopting a preset unit characteristic image group, determining the characteristic vector of each slice image, and extracting a test image according to the characteristic vector. The technical problem that the time consumption of calculation is too long in the layout test pattern extraction method in the prior art is solved. The effects of reducing the amount of calculation and saving the calculation time are achieved.

Description

A layout test pattern extraction method, device, equipment and medium

technical field

The present invention relates to the field of semiconductors, in particular to a layout test pattern extraction method, device, equipment and medium.

Background technique

In integrated circuit manufacturing, photolithography, as the only patterning process, has become an important technology to promote the development of integrated circuit manufacturing. Photolithography technology uses the principle of photochemical reaction to transfer the pattern prepared on the mask to the substrate, so as to perform selective etching and deposition to form the device.

Photolithography usually uses optical exposure to generate patterns. Therefore, interference diffraction, or optical proximity effect, occurs between adjacent patterns on the mask, resulting in differences between the imaging pattern on the wafer surface and the mask pattern. With the reduction of integrated circuit process nodes, the difference between the imaging pattern and the mask pattern is getting larger and larger, and it is necessary to introduce resolution enhancement technologies, such as optical proximity correction (Optical Proximity Correction, OPC), light source mask co-optimization ( Source Mask Optimization, SMO) and other methods make the imaging pattern and the design pattern as similar as possible by modifying the mask pattern or adjusting the shape of the light source.

Both SMO and OPC calculations require a test pattern as input. The selection of test graphics is very important, it is directly related to whether the collected experimental data is valid and whether it can cover all the features of the graphics in the design layout. Only the test pattern that matches the layout pattern can get a suitable light source through SMO or fully calibrate to get an accurate OPC model.

At present, the automatic generation method of the test pattern is to extract the typical pattern as the test pattern by adopting the method based on spectrum analysis by using an Electronic Design Automation (Electronic Design Automation, EDA) tool. However, with the trend of complexity of the layout, the calculation of spectral changes takes too long.

SUMMARY OF THE INVENTION

By providing a layout test pattern extracting method, device, equipment and medium, the present invention improves the technical problem of long calculation time in the layout test pattern extraction method in the prior art.

First, in order to solve the above-mentioned technical problems, the embodiments of the present invention provide the following technical solutions:

A layout test pattern extraction method, comprising:

Searching out a plurality of target areas that satisfy the preset layout rules on the target layout, and setting sampling points at each of the target areas;

According to the sampling points, the target layout is sliced, and a plurality of slice graphics are extracted, and each of the slice graphics includes at least one of the sampling points;

Each of the sliced graphics is divided into grids, and a description matrix of each of the sliced graphics is determined according to the divided grid, and the description matrix can characterize the graphics layout characteristics of the corresponding sliced graphics;

Scan the description matrix of each slice pattern by using a preset unit feature pattern group, determine the feature vector of each slice pattern, and extract the test from the plurality of slice patterns according to the feature vector graph, wherein the feature vector represents the correlation between the corresponding slice graph and the unit feature graph group.

Optionally, the target area that satisfies the preset layout rule includes any one or more of the following combinations: the area from the end point of the line to the end point of the line, the area from the end point of the line to the line, the area from the end point of the line to the inflection point, the area from the inflection point to the inflection point. Areas of lines, inflection point to inflection point, or areas where lines overlap.

Optionally, the searching for a plurality of target areas that meet the preset layout rules on the target layout includes: determining the search size according to the key size and graphics period of the target layout; Within the search size, there is an area of graphics that satisfies a preset layout rule as the target area.

Optionally, the setting the sampling point at each of the target areas includes: taking the sampling point as the center of a graph that satisfies a preset layout rule.

Optionally, slicing the target layout according to the sampling points, and extracting multiple slice graphics, including: taking each sampling point as a center, slicing the target layout, and extracting multiple slices A graph, wherein the center of each slice graph is the sampling point, and the side length is 3 times the graph period of the target layout.

Optionally, dividing each of the slicing graphics into a grid shape includes: using a line that coincides with each edge of the polygon in each of the slicing graphics as a tangent, dividing each of the slicing graphics into a grid. are divided into grids.

Optionally, determining the description matrix of each of the sliced graphics according to the divided grid includes: determining, according to the divided grid, a Boolean matrix, an area matrix and a distance matrix of each of the sliced graphics, wherein, The Boolean matrix is determined according to the graphics in the divided grids, and represents the graphic shape of the corresponding sliced graphics; the area matrix is determined according to the area of the divided grids; the distance matrix is determined according to the divided grids according to the location. The distance from the center of the slice pattern is determined.

Optionally, using a preset unit feature pattern group to scan the description matrix of each of the slice patterns, and determining a feature vector of each of the slice patterns, includes: Each unit feature pattern scans the Boolean matrix of each slice pattern to determine the eigenvalue of each slice pattern relative to each unit feature pattern; according to each slice pattern relative to each The eigenvalues of the cell feature patterns, and the feature vectors for each of the slice patterns are generated.

Optionally, before extracting the test pattern from the plurality of slice patterns according to the feature vector, the method further includes: normalizing the feature vector of each slice pattern.

Optionally, the extracting the test pattern from the plurality of slice patterns according to the feature vector includes: grouping the plurality of slice patterns according to the feature vector of each of the slice patterns; A representative slicing graph is extracted from each group of slicing graphs after grouping, and the determined representative slicing graph is used as the test graph. In a second aspect, a layout test pattern extraction device is provided, including:

The sampling point setting module is used to search for a plurality of target areas that satisfy the preset layout rules on the target layout, and set sampling points at each of the target areas;

a slice pattern extraction module, configured to slice the target layout according to the sampling points, and extract a plurality of slice patterns, each of which includes at least one of the sampling points;

A grid dividing module is used to divide each of the sliced graphics into a grid shape, and determine a description matrix of each of the sliced graphics according to the divided grids, and the description matrix can represent the corresponding slices Graphical layout characteristics of graphics;

The extraction module is configured to scan the description matrix of each of the sliced graphics by using a preset unit feature graphics group, determine the feature vector of each of the sliced graphics, and select a feature vector from the plurality of slices according to the feature vector. A test pattern is extracted from the pattern, wherein the feature vector represents the correlation between the corresponding slice pattern and the unit feature pattern group. In a third aspect, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the method of any one of the first aspect when the processor executes the program A step of.

In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, implements the steps of any one of the methods in the first aspect. One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

In the layout test pattern extraction method, device, device and medium provided by the embodiments of the present application, sampling points are set according to preset layout rules, sliced patterns are extracted according to the sampling points, and only slice patterns with sampling points are generated. Describing matrices and performing calculations such as unit feature graph group scanning, it is not necessary to perform calculation and analysis on each area of the target layout, which reduces the amount of calculation and saves calculation time.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without any creative effort.

1 is a flowchart of a method for extracting a layout test pattern in an embodiment of the application;

2 is an example diagram of a target area that satisfies a preset layout rule in an embodiment of the present application;

3 is a schematic diagram 1 of a grid division method in an embodiment of the present application;

FIG. 4 is a second schematic diagram of a grid division method in an embodiment of the present application;

5 is a schematic diagram of describing a matrix in an embodiment of the present application;

6 is a schematic diagram of a unit feature pattern group in an embodiment of the present application;

7 is a structural diagram of a layout test pattern extraction device in an embodiment of the application;

FIG. 8 is a structural diagram of an electronic device in an embodiment of the present application.

Detailed ways

By providing a layout test pattern extraction method, device, device, and medium, the embodiments of the present application improve the technical problem of excessive computation time in the layout test pattern extraction method in the prior art. The effect of reducing the amount of computation and saving computation time is achieved.

In order to solve the above-mentioned technical problems, the general idea of the technical solutions provided by the embodiments of the present application is as follows:

Searching out a plurality of target areas that satisfy the preset layout rules on the target layout, and setting sampling points at each of the target areas;

According to the sampling points, the target layout is sliced, and a plurality of slice graphics are extracted, and each of the slice graphics includes at least one of the sampling points;

Each of the sliced graphics is divided into grids, and a description matrix of each of the sliced graphics is determined according to the divided grid, and the description matrix can characterize the graphics layout characteristics of the corresponding sliced graphics;

Scan the description matrix of each slice pattern by using a preset unit feature pattern group, determine the feature vector of each slice pattern, and extract the typical slice pattern from the plurality of slice patterns according to the feature vector. The graph is used as a test graph, wherein the feature vector represents the correlation between the corresponding slice graph and the unit feature graph group. The feature vector can quantitatively characterize the similarity between the slice patterns.

By setting the sampling points according to the preset layout rules, and extracting the slice graphics according to the sampling points, only the slice graphics with sampling points are calculated to generate the description matrix and scan the unit feature graphics group, without the need for the target layout. Calculation analysis is performed in each area of the system, which reduces the amount of calculation and saves calculation time.

In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with specific implementations. The limitations of the technical solutions of the application, in the case of no conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

Example 1

In this embodiment, a layout test pattern extraction method is provided, as shown in FIG. 1 , including:

Step S101, searching for a plurality of target areas that meet the preset layout rules on the target layout, and setting sampling points at each of the target areas;

Step S102, slicing the target layout according to the sampling points, and extracting a plurality of slice graphics, each of which includes at least one sampling point;

Step S103, dividing each of the slice graphics into a grid shape, and determining a description matrix of each of the slice graphics according to the divided grid, and the description matrix can represent the graphic layout of the corresponding slice graphics. feature;

Step S104, scan the description matrix of each of the sliced graphics using a preset unit feature pattern group, determine the feature vector of each of the sliced graphics, and select the sliced graphics from the plurality of sliced graphics according to the feature vector. A test pattern is extracted, wherein the feature vector represents the correlation between the corresponding slice pattern and the unit feature pattern group. The feature vector can quantitatively characterize the similarity between the slice patterns. Below, the method provided by this embodiment is described in detail with reference to FIGS. 1 to 5:

First, step S101 is performed, and a plurality of target areas satisfying the preset layout rules are searched on the target layout, and sampling points are set at each of the target areas.

The target layout is the initial design layout of the chip that needs to be corrected by lithography. Searches on the target layout can be performed by EDA tools. In the specific implementation process, the design rule check (design rule check, DRC) function in the EDA software can be used for implementation.

In the specific implementation process, in order to improve the accuracy of searching the target area, the search size can be determined according to the key size (ie the minimum feature size) and the pattern period (ie the minimum line period Pitch) of the target layout; On the target layout, within the search size, there is an area of graphics that satisfies a preset layout rule as the target area. Specifically, it is necessary to set the characteristic parameters of structures such as endpoints, lines, and inflection points according to the key dimensions and graphic cycle data on the layout, and describe these characteristic parameters as sentences used by the EDA software, so as to realize the search for special structures and then set sampling points.

Specifically, the critical dimension and pattern cycle are determined by the process size selected by the chip, that is, the critical dimension of the M1 layer layout of the 32nm process is usually 50nm, the pattern cycle is 100nm, and the key dimension of the M1 layer layout of the 28nm process is usually 45nm, and the pattern The cycle is 90nm, which are parameters that can be obtained after selecting the manufacturing process of the chip. An area size can be determined as the search size based on the critical size and pattern period. Then it is stipulated that if there is a graphic that satisfies the preset layout rule in the area size, the area where the graphic is located is the target area. It should be noted that the search size is usually proportional to the key size of the layout pattern and the pattern period.

For example, assuming that the preset layout rule is an inflection point-to-inflection point structure, and the search size is 200nm, first find all the inflection points in the layout, take these inflection points as the center, if there is another inflection point in the square area with a side length of 200nm Inflection point, the area where the structure is located is determined as the target area.

In this embodiment of the present application, the target area that satisfies the preset layout rule includes any one or a combination of the following: an end-to-end structure, an end-to-line structure, an inflection point-to-line structure, and a protruding structure, An inflection point-to-inflection point structure, or a structure in which lines overlap. Figure 2 shows an example of a target area that satisfies the preset layout rules.

Of course, the preset layout rule may also be a specific line width or spacing, etc., which is not limited here.

After the target area is determined, there are many ways to set the sampling point. Here are two examples:

In the first type, the center of the graphic that satisfies the preset layout rule is used as the sampling point.

The second is to set sampling points according to preset rules. For example, the preset sampling point that satisfies the preset layout rule of line endpoint to line endpoint is the midpoint of the two endpoints, and the preset sampling point that satisfies the preset layout rule from endpoint to line The sampling point of is the projection point of the endpoint on the line, and the preset sampling point that satisfies the rules of overlapping layout of lines is the midpoint of the overlapping area, which is not limited here, and will not be listed one by one.

Of course, in the specific implementation process, the methods for setting sampling points are not limited to the above two, which are not limited here.

Specifically, because most of the layouts are repeating line structures or blank areas without graphics, there are only areas from line endpoints to line endpoints, line endpoints to line regions, line endpoints to inflection points, and inflection points to the line. Areas, inflection points to inflection points, or areas where lines overlap, etc., the topology of the graph will change significantly. Therefore, compared with the traditional comprehensive window slicing, the targeted setting of sampling points in these areas can Significantly reduces the number of sample points without losing graphical information on the layout.

Then, step S102 is performed, and the target layout is sliced according to the sampling points, and a plurality of slice graphics are extracted, and each of the slice graphics includes at least one of the sampling points.

In this embodiment of the present application, the target layout can be sliced with each sampling point as the center, and a plurality of sliced graphics can be extracted, wherein the center of each sliced graphics is the sampling point, and the side length is 3 times the graphics period of the target layout.

For example, assuming that 300 sampling points are set for the search on the target layout, take each sampling point as the center and 3 times the graphics period as the side length to extract a square slice pattern, and extract 300 slice patterns.

Of course, in the specific implementation process, the slice graphics can also be extracted by rectangles with other aspect ratios, or the slice graphics can be extracted by rectangles, circles or other polygons; Any preset value is not limited here. When there are some sampling points that are very close to each other and exist on the same slice image, no processing is required, or only one slice image including the same sampling points can be retained.

Of course, in the specific implementation process, the slice image may also be extracted with the sampling point as the endpoint instead of the sampling point as the midpoint, which is not limited herein.

Next, step S103 is performed, each of the sliced graphics is divided into grids, and a description matrix of each of the sliced graphics is determined according to the divided grids, and the description matrix can represent the corresponding slices Graphical layout characteristics of the graph.

In a specific implementation process, tangent lines in two mutually perpendicular directions may be set at preset intervals to divide a uniform grid shape. In order to further reduce the amount of calculation and save the calculation time, the embodiment of the present application sets:

Taking the line that coincides with the sides of the polygons in the slicing graph as the tangent, that is, taking the straight lines obtained by extending the sides of the polygons in the slicing graph to both sides as the tangent, each of the slicing graphs is divided into grid-like. That is, when pixelizing the sliced graph, the tangent is set based on the edge of each polygon to divide the grid, and the entire sliced graph is cut into a grid shape. The resulting pixel matrix is smaller, which can also represent the shape characteristics of the sliced graph. The amount of computation is reduced.

For example, when the slicing graph shown in FIG. 3 is divided into a grid, as shown in FIG. 4 , the sides of the polygons in the slicing graph are extended at both ends as tangents 301 , so that the slicing graph of FIG. 3 is divided into FIG. 4 The grid is divided into 18 grid points. Generally speaking, the graphics in the design layout do not have a fixed size, so the size of each grid point in the cut grid is different.

Then, a description matrix of each of the sliced graphics is determined according to the divided grids, and the description matrix specifically includes a Boolean matrix, an area matrix and a distance matrix of the sliced graphics, wherein the Boolean matrix is based on the divided grids. The graphs in are determined and represent the graph shapes of the corresponding slice graphs; the area matrix is determined according to the area of each divided grid; the distance matrix is determined according to the distance between the divided grids and the center of the slicing graph. The Boolean matrix contains the graphics structure information in the sliced graphics, the area matrix can express the area size of each part in the sliced graphics, and the distance matrix can express the position information of each part of the graphics in the sliced area.

Specifically, the generation rule of the Boolean matrix is, according to the number of grid points and their arrangement rules, when a single grid point contains graphics (dark areas in the image), set the value at the corresponding position of the matrix to is 1. When there is no graphic in the grid point (white area in the image), the value at the corresponding position of the matrix is set to 0.

For example, the Boolean matrix corresponding to the grid-like slice graph in Fig. 4 is shown in Fig. 5. In the grid generated by the slice graph, there are 6 rows in the x (horizontal) direction and 3 columns in the y (vertical) direction. Generate a 6×3 Boolean matrix corresponding to the size of the grid, and set the value at the corresponding position of the matrix to 1 when a single grid point contains graphics, and set the corresponding position of the matrix to 1 when there is no graphic in the grid point. The value at 0 is set to 0, and the Boolean matrix shown in Figure 5 is set.

The generation rule of the area matrix is to generate a matrix according to the area size of each grid point in the grid obtained by slicing the graph according to the number of grid points and their arrangement rules.

For example, the area matrix corresponding to the grid-like slicing graph in Fig. 4 is shown in Fig. 5. In the grid generated by the slicing graph, there are 6 rows in the x (horizontal) direction and 3 columns in the y (vertical) direction. A 6×3 area matrix is generated corresponding to the size of the grid, and the area value of each single grid point is filled in the corresponding position of the area matrix, and the area matrix shown in Figure 5 is set. For example, the length of the first grid point in the first row of the grid is 175 nm and the width is 100 nm, so the value at the corresponding position of the matrix is set to the area value of this grid point, that is, 17500. And so on for other values in the matrix.

The generation rule of the distance matrix is to generate a matrix according to the distance between each grid point and the center of the slicing graph in the grid obtained by slicing the graph according to the number of grid points and their arrangement rules.

For example, the area matrix corresponding to the grid-like slicing graph in Fig. 4 is shown in Fig. 5. In the grid generated by the slicing graph, there are 6 rows in the x (horizontal) direction and 3 columns in the y (vertical) direction. A 6×3 distance matrix is generated corresponding to the size of the grid, and the distance between each single grid point and the center of the sliced graph is filled in the corresponding position of the distance matrix, and the distance matrix shown in Figure 5 is set. For example, the offset of the center point of the first grid point in the first row of the grid from the center of the slice pattern in the x direction is 137.5 nm, and the offset in the y direction is 175 nm. Therefore, the value at the corresponding position of the matrix is set to the distance value of the grid point from the center of the sliced graph, that is, 223. And so on for other values in the matrix.

Then, step S104 is performed, and the description matrix of each sliced pattern is scanned by using a preset unit characteristic pattern group, the characteristic vector of each sliced pattern is determined, and according to the characteristic vector A test pattern is extracted from the slice pattern, wherein the feature vector represents the correlation between the corresponding slice pattern and the unit feature pattern group.

In the embodiment of the present application, the unit feature graph group can be as shown in FIG. 6 , which is a second-order feature graph generated according to the high-order local autocorrelation theory. The adjacent area (that is, the area where the layout graphic exists) needs to be considered for the feature pattern, and the white block indicates the area that the feature does not need to consider. Of course, the unit feature pattern group can also be set by the staff according to experience, which is not limited here.

Specifically, first scan the Boolean matrix of each slice pattern with each unit characteristic pattern in the unit characteristic pattern group, and determine the characteristics of each slice pattern relative to each unit characteristic pattern value; and then generate a feature vector of each of the sliced graphics according to the characteristic value of each of the sliced graphics relative to the characteristic graphics of each unit.

For, scanning the Boolean matrix of each of the slice patterns with each unit feature pattern, and determining the eigenvalues of each of the slice patterns relative to the feature patterns of each unit are as follows:

Use a single unit feature graph to scan in the Boolean matrix in a windowed manner. When the center position of the unit feature graph and the adjacent area are both scanned as 1 in the Boolean matrix of the slice graph, it means that the slice graph has the unit feature. The topological structure feature represented by the graph, the feature value of the slice graph relative to the feature graph of the unit should be added with the product of the area weight and the distance weight of the corresponding grid position. The unit feature graph will continuously scan and operate in the Boolean matrix of the slice graph in a step-by-step manner. Whenever the Boolean value of the center position and the adjacent area in the Boolean matrix is 1, the slice graph is relative to the unit feature graph. The eigenvalues of are added to the product of the area at the corresponding location and the distance weight. This process can be expressed in mathematical expressions as:

Among them, f(area) is the formula for calculating the area weight from the area value, g(distance) is the formula for calculating the distance weight from the distance value, v _i represents the feature value of the slice graph relative to the i-th unit feature graph, and x represents the Each pixel in the boolean matrix of the sliced graph, r represents the offset of the adjacent position to be considered around x in the unit feature graph, bit(x) indicates whether there is a graph at the x position (if not, bit(x) is 0. If there is, it is 1), f(area _x ) and g(distance _x ) represent the area weight and distance weight calculation formula of the graph at the x position, respectively, where cd represents the key dimension in the layout graph.

Of course, in the specific calculation of eigenvalues, the area weight and distance weight can be replaced by other calculation functions, as long as the area weight is positively correlated with the grid area, and the distance weight is negatively correlated with the distance between the grid and the center of the slice graph.

For example, the cell feature pattern 20 in FIG. 6 is scanned in the Boolean matrix of FIG. 5 in a windowed manner. When the values at the center of the feature and its upper and left positions are all 1, it indicates that the slice pattern has cells. The topological structure features represented by the feature graph 20 (the second grid in the first row, the first grid in the second row, and the second grid in the second row in the Boolean matrix of FIG. 5 are being scanned with the unit feature graph 20, that is, the three grids have The topological structure feature represented by the unit feature graph 20 ), then the slice graph in FIG. 4 needs to add the product of the area weight and the distance weight of the first row and the second grid with respect to the feature value of the unit feature graph 20 , the second row first The product of the area weight and distance weight of the grid, and the product of the area weight and distance weight of the second grid in the second row. The unit feature pattern 20 continuously scans and operates in the Boolean matrix of the slice pattern in a step-by-step manner. Whenever the Boolean values at the three positions in the Boolean matrix that match the unit feature pattern 20 are all 1, the feature value will be added. The product of the area weight and the distance weight at the corresponding location on .

Arrange each slice pattern in a preset order relative to the feature values of each unit feature pattern to form a feature vector V of each slice pattern. For example, assuming that the eigenvalues of slice graph A relative to each unit feature graph in FIG. 6 are a0, a1, a2...a24 in sequence, then the eigenvectors of slice graph A are V=(a0, a1, a2... a24).

Further, considering that the test pattern extraction method is mainly used for design layout preprocessing before lithography process optimization, and considering the symmetry of the lithography light source, the unit feature patterns symmetrical about the x-axis and the y-axis are equivalent, so The unit characteristic pattern of Fig. 5 (3, 4) (7, 8) (9, 10, 11, 12) (13, 14, 15, 16) (17, 18, 19, 20) (21, 22, 23, 24) represent the same feature respectively, and the eigenvalues obtained by its operation will be added together as the eigenvalues of the same topology feature. For example, assuming that the eigenvalues of slice graph A relative to each unit feature graph in FIG. 5 are a0, a1, a2...a24 in sequence, then the feature vector of slice graph A is V=(a0, a1, a2, a3 +a4, a5, a6, a7+a8, a9+a10+a11+a12, a13+a14+a15+a16, a17+a18+a19+a20, a21+a22+a23+a24).

The above-mentioned eigenvectors can represent the topological features of the corresponding slice graphs, and the difference of the topological structures between different slicing graphs can be expressed as the distance of their eigenvectors in the feature space. Because the number and area of different topological structures in the layout graph are very different, the difference in the extracted eigenvalues is also very large, even reaching several orders of magnitude. In order to facilitate data processing and reduce the difficulty of data processing, this embodiment The eigenvalues in the eigenvectors are also normalized, and after normalization, the weights of the eigenvalues in the eigenvectors are balanced. The calculation formula for linear normalization is:

Among them, vi is the _ith eigenvalue in the feature vector before normalization, _vmax is the maximum value of the ith feature in the feature vectors of all slice graphics, and v _min is the eigenvector of all slice graphics. The minimum value of the ith feature.

Of course, other normalization methods, such as standard deviation normalization methods, can also be used.

Further, the method for extracting a test pattern from the plurality of slice patterns according to the feature vector is: firstly group the plurality of slice patterns according to the feature vector of each of the slice patterns; A representative slice pattern is extracted from each subsequent group of slice patterns, and the determined representative slice pattern is used as the test pattern.

Specifically, a plurality of slice graphs whose distances of feature vectors in the feature space are less than a preset distance may be used as a group for grouping, or a hierarchical clustering algorithm or the like may be used for grouping, which is not limited here.

In the specific implementation process, the slice pattern whose feature vector is at the center of the feature space in each group of slice patterns may be determined as the representative slice pattern of the group, and the representative slice patterns determined in each group are used as test patterns. Of course, one can also be randomly selected from each group of slicing patterns as the representative slicing pattern of the group, and the representative slicing patterns determined in each group are used as test patterns. There is no restriction here.

Specifically, in the actual design layout, a considerable number of areas have repeated line structures or no graphic structures. The test pattern extraction method of this embodiment only slices the areas where the graphic structure changes. Compared with the traditional Compared with the method of all slicing of the design layout, the number of sliced graphics to be analyzed is greatly reduced, and the graphics information in the design layout will not be lost.

Further, when pixelizing the sliced graphics, the grid is divided based on the edge extension lines of the polygons to generate the matrix, while the traditional method takes the minimum structure size of the graphics as the pixel size. Compared with this, the pixel description matrix generated in this embodiment is smaller, which reduces the computational complexity of feature extraction.

Moreover, compared with the traditional high-order local autocorrelation feature description method, this embodiment improves the typical pattern extraction problem for lithography process optimization, because the light source in the lithography process is a The feature graph whose axis is symmetrical with the Y axis is an equivalent structure for this problem, so this embodiment combines these features to reduce the complexity of feature description.

Based on the same inventive concept, the present application also provides a device corresponding to the method in Embodiment 1, and details are described in Embodiment 2 for details.

Embodiment 2

In this embodiment, as shown in FIG. 7, a layout test pattern extraction device is provided, including:

A sampling point setting module 701, configured to search for a plurality of target areas that satisfy the preset layout rules on the target layout, and set sampling points at each of the target areas;

A slice pattern extraction module 702, configured to slice the target layout according to the sampling points, and extract a plurality of slice patterns, each of which includes at least one of the sampling points;

The grid dividing module 703 is configured to divide each of the slice graphics into a grid shape, and determine a description matrix of each of the slice graphics according to the divided grid, and the description matrix can represent the corresponding Graphical layout features of sliced graphics;

The extraction module 704 is configured to scan the description matrix of each of the sliced graphs by using a preset unit feature graph group, determine a feature vector of each of the sliced graphs, and select a feature vector from the plurality of slices according to the eigenvectors. A test pattern is extracted from the slice pattern, wherein the feature vector represents the correlation between the corresponding slice pattern and the unit feature pattern group.

Since the device introduced in the second embodiment of the present invention is the device used to implement the method in the first embodiment of the present invention, based on the method introduced in the first embodiment of the present invention, those skilled in the art can understand the specific structure and deformation of the device. , so it is not repeated here. All devices used in the method of Embodiment 1 of the present invention belong to the scope of protection of the present invention.

Based on the same inventive concept, this embodiment of the present invention also provides an electronic device embodiment corresponding to the method in Embodiment 1, see Embodiment 3.

Embodiment 3

This embodiment provides an electronic device, as shown in FIG. 8 , including a memory 810, a processor 820, and a computer program 811 stored in the memory 810 and running on the processor 820. When the processor 820 executes the computer program 811, Any of the implementations in the first embodiment can be implemented.

Since the electronic device introduced in this embodiment is the device used to implement the method in the first embodiment of the present application, based on the method introduced in the first embodiment of the present application, those skilled in the art can understand the specific details of the electronic device in this embodiment. Therefore, how the electronic device implements the methods in the embodiments of the present application will not be described in detail here. As long as the devices used by those skilled in the art to implement the methods in the embodiments of the present application fall within the scope of the intended protection of the present application.

Based on the same inventive concept, the present application provides a storage medium corresponding to the first embodiment. For details, refer to the fourth embodiment.

Embodiment 4 This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, any one of the implementation manners of Embodiment 1 can be implemented.

The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

By setting the sampling points according to the preset layout rules, and extracting the slice graphics according to the sampling points, only the slice graphics with sampling points are calculated to generate the description matrix and scan the unit feature graphics group, without the need for the target layout. Calculation analysis is performed in each area of the system, which reduces the amount of calculation and saves calculation time. Further, when pixelizing the sliced graphics, the grid is divided based on the edge extension lines of the polygons to generate the matrix, while the traditional method takes the minimum structure size of the graphics as the pixel size. Compared with this, the pixel description matrix generated in this embodiment is smaller, which reduces the computational complexity of feature extraction. Moreover, compared with the traditional high-order local autocorrelation feature description method, this embodiment improves the typical pattern extraction problem for lithography process optimization, because the light source in the lithography process is a The feature graph whose axis is symmetrical with the Y axis is an equivalent structure for this problem, so this embodiment combines these features to reduce the complexity of feature description.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (11)

1. a layout test pattern extraction method, is characterized in that, comprises: Searching out a plurality of target areas that satisfy the preset layout rules on the target layout, and setting sampling points at each of the target areas; According to the sampling points, the target layout is sliced, and a plurality of slice graphics are extracted, and each of the slice graphics includes at least one of the sampling points; Each of the sliced graphics is divided into grids, and a description matrix of each of the sliced graphics is determined according to the divided grid, and the description matrix can characterize the graphics layout characteristics of the corresponding sliced graphics; Scan the description matrix of each slice pattern by using a preset unit feature pattern group, determine the feature vector of each slice pattern, and extract the test from the plurality of slice patterns according to the feature vector A graph, wherein the feature vector represents the correlation between the corresponding slice graph and the unit feature graph group; The target area that satisfies the preset layout rules includes any one or a combination of the following: the area from the end point of the line to the end point of the line, the area from the end point of the line to the line, the area from the end point of the line to the inflection point, the area from the inflection point to the line, The area from inflection point to inflection point, the area where lines overlap, the area of specific line width, the area of specific spacing; The determining a description matrix of each of the sliced graphics according to the divided grid includes: determining a Boolean matrix, an area matrix and a distance matrix of each of the sliced graphics according to the divided grid, wherein the Boolean matrix Determined according to the graphics in the divided grids, representing the graphic shape of the corresponding sliced graphics; the area matrix is determined according to the areas of the divided grids; the distance matrix is determined according to the distances between the divided grids from the center of the sliced graphics distance is determined. 2. The method according to claim 1, wherein the searching for a plurality of target areas on the target layout that satisfies the preset layout rules, comprising: Determine the search size according to the key size and pattern period of the target layout; On the target layout, within the search size, there is an area of graphics that satisfies a preset layout rule as the target area. 3. The method of claim 1, wherein the setting sampling points at each of the target areas comprises: The center of the graph that satisfies the preset layout rule is taken as the sampling point. 4. The method according to claim 1, wherein, according to the sampling points, the target layout is sliced to extract a plurality of slice graphics, comprising: Taking each sampling point as the center, the target layout is sliced, and a plurality of sliced graphics are extracted, wherein the center of each sliced graphics is the sampling point, and the side length is the period of the graphics of the target layout. 3 times. 5. The method of claim 1, wherein the dividing each of the slice graphics into a grid shape comprises: Each of the slicing graphs is divided into a grid shape by taking the lines coincident with the respective sides of the polygons in each slicing graph as tangent lines. 6. The method according to claim 1, wherein the described description matrix of each of the sliced graphics is scanned by a preset unit characteristic graphics group, and the feature vector of each of the sliced graphics is determined, include: Scanning the Boolean matrix of each of the slice graphics with each unit characteristic figure in the unit characteristic figure group, and determining the eigenvalue of each of the slice figures relative to the each unit characteristic figure; A feature vector of each of the slice patterns is generated according to the feature values of each of the slice patterns relative to the feature patterns of each unit. 7. The method of claim 1, wherein before extracting a test pattern from the plurality of slice patterns according to the feature vector, the method further comprises: The feature vector of each of the sliced graphics is normalized. 8. The method of claim 1, wherein the extracting a test pattern from the plurality of slice patterns according to the feature vector comprises: grouping the plurality of slice graphics according to the feature vector of each of the slice graphics; A representative slice pattern is extracted from each group of slice patterns after grouping, and the determined representative slice pattern is used as the test pattern. 9. A layout test pattern extraction device, characterized in that, comprising: The sampling point setting module is used to search for a plurality of target areas that satisfy the preset layout rules on the target layout, and set sampling points at each of the target areas; a slice pattern extraction module, configured to slice the target layout according to the sampling points, and extract a plurality of slice patterns, each of which includes at least one of the sampling points; A grid dividing module is used to divide each of the sliced graphics into a grid shape, and determine a description matrix of each of the sliced graphics according to the divided grids, and the description matrix can represent the corresponding slices Graphical layout characteristics of graphics; The extraction module is configured to scan the description matrix of each of the sliced graphics by using a preset unit feature graphics group, determine the feature vector of each of the sliced graphics, and select a feature vector from the plurality of slices according to the feature vector. A test pattern is extracted from the pattern, wherein the feature vector represents the correlation between the corresponding slice pattern and the unit feature pattern group; Wherein, the target area that satisfies the preset layout rule includes any one or a combination of the following: the area from the end point of the line to the end point of the line, the area from the end point of the line to the line, the area from the end point of the line to the inflection point, the area from the inflection point to the line Area, inflection point to inflection point area, area where lines overlap, area with specific line width, area with specific spacing; Wherein, determining the description matrix of each of the slice graphics according to the divided grid includes: determining a Boolean matrix, an area matrix and a distance matrix of each of the slice graphics according to the divided grid, wherein the The Boolean matrix is determined according to the graphics in each divided grid, and represents the graphic shape of the corresponding sliced graphics; the area matrix is determined according to the area of each divided grid; the distance matrix is determined according to the distance of each divided grid from the slice The distance from the center of the graph is determined. 10. An electronic device, comprising a memory, a processor and a computer program stored on the memory and running on the processor, when the processor executes the program, the method of any one of claims 1-8 is implemented. step. 11. A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any one of claims 1-8.

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