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CN109346572B - Manufacturing method of light emitting diode epitaxial wafer and light emitting diode epitaxial wafer - Google Patents

Manufacturing method of light emitting diode epitaxial wafer and light emitting diode epitaxial wafer Download PDF

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CN109346572B
CN109346572B CN201810961474.0A CN201810961474A CN109346572B CN 109346572 B CN109346572 B CN 109346572B CN 201810961474 A CN201810961474 A CN 201810961474A CN 109346572 B CN109346572 B CN 109346572B
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type semiconductor
semiconductor layer
type
layer
groove
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CN109346572A (en
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郭炳磊
王群
葛永晖
吕蒙普
胡加辉
李鹏
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

The invention discloses a manufacturing method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate; sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate, wherein the N-type semiconductor layer is N-type doped nitride; forming a groove extending to the N-type semiconductor on the P-type semiconductor layer; and carrying out electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the surface of the N-type semiconductor layer in the groove is used for arranging an N-type electrode. According to the invention, through carrying out electron irradiation on the surface of the N-type semiconductor layer provided with the N-type electrode, nitrogen vacancies in the N-type semiconductor layer are increased, the incorporation of an N-type dopant is promoted, the incorporation effectiveness of a doping element is improved, the high impurity state caused by heavy doping is changed, the mobility of a carrier is improved, and the light efficiency of the whole light-emitting diode is improved.

Description

Manufacturing method of light emitting diode epitaxial wafer and light emitting diode epitaxial wafer
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. Gallium nitride (GaN) has good thermal conductivity, and also has excellent characteristics of high temperature resistance, acid and alkali resistance, high hardness and the like, so that gallium nitride (GaN) based LEDs are receiving more and more attention and research.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are sequentially stacked on the substrate. The P-type semiconductor layer is used for providing holes for carrying out compound luminescence, the N-type semiconductor layer is used for providing electrons for carrying out compound luminescence, the active layer is used for carrying out radiation compound luminescence of the electrons and the holes, and the substrate is used for providing a growth surface for the epitaxial material.
The chip is a core component of the LED, and comprises an epitaxial wafer and an electrode arranged on the epitaxial wafer. In a chip process, a groove extending to an N-type semiconductor layer is usually formed in a P-type semiconductor layer, and an N-type electrode is disposed on the N-type semiconductor layer in the groove. In addition, a P-type electrode is disposed on the P-type semiconductor layer.
In order to form good ohmic contact with the electrode, the N-type semiconductor layer is heavily doped, and an ultrathin potential barrier is obtained through the heavy doping. The ultra-thin barrier has no blocking capability for the carriers, and the carriers can freely pass through the barrier to form a large tunneling current, so that ohmic contact is obtained (no obvious additional blocking is generated, and the voltage drop generated by the current on the contact layer is smaller than that generated on the device per se).
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the substrate is made of sapphire, the N-type semiconductor layer and the like, gallium nitride is usually selected, the sapphire and the gallium nitride are heterogeneous materials, the lattice constant difference is large, and large lattice mismatch exists between the sapphire and the gallium nitride. Stress and defects generated by lattice mismatch are more introduced into gallium nitride and are continuously accumulated in the epitaxial growth process, so that larger crystal defects exist in the N-type semiconductor layer. And the N-type semiconductor layer is heavily doped, and excessive impurity defects can be introduced in the heavily doped process, so that the defect concentration in the N-type semiconductor layer is high. The high concentration of defects can restrict the migration of carriers, and influence the light efficiency of the whole light emitting diode.
Disclosure of Invention
The embodiment of the invention provides a manufacturing method of a light-emitting diode epitaxial wafer and the light-emitting diode epitaxial wafer, which can solve the problem that the high-concentration defect in an N-type semiconductor layer in the prior art can restrict the migration of carriers and influence the light efficiency of the whole light-emitting diode. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a method for manufacturing an epitaxial wafer of a light emitting diode, where the method includes:
providing a substrate;
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate, wherein the N-type semiconductor layer is N-type doped nitride;
forming a groove extending to the N-type semiconductor on the P-type semiconductor layer;
and carrying out electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the surface of the N-type semiconductor layer in the groove is used for arranging an N-type electrode.
Optionally, the electron irradiation has a radiation dose of 1016/cm2～1022/cm2。
Optionally, the performing electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove includes:
and irradiating the surface of the N-type semiconductor layer in the groove by using an electron beam provided by a transmission electron microscope as a light source.
Preferably, the diameter of the electron beam is 8to 30 μm.
Optionally, the manufacturing method further includes:
and after the surface of the N-type semiconductor layer in the groove is subjected to electron irradiation, annealing treatment is carried out on the N-type semiconductor layer in the groove.
In a possible implementation manner of the embodiment of the present invention, the manufacturing method further includes:
and carrying out electron irradiation on the surface of the P-type semiconductor layer to increase nitrogen vacancies in the P-type semiconductor layer, wherein the P-type semiconductor layer is P-type doped nitride, and the surface of the P-type semiconductor layer is used for arranging a P-type electrode.
Optionally, the manufacturing method further includes:
and after the surface of the P-type semiconductor layer is subjected to electron irradiation, annealing treatment is carried out on the P-type semiconductor layer.
In another possible implementation manner of the embodiment of the present invention, the manufacturing method further includes:
growing a contact layer on the P-type semiconductor layer, wherein the contact layer is P-type doped nitride, and the surface of the contact layer is used for arranging a P-type electrode;
and performing electron irradiation on the surface of the contact layer to increase nitrogen vacancies in the contact layer.
Optionally, the manufacturing method further includes:
and after the surface of the contact layer is subjected to electron irradiation, annealing the contact layer.
On the other hand, the embodiment of the invention provides a light emitting diode epitaxial wafer, which comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate, a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, an N-type electrode is arranged on the surface of the N-type semiconductor layer in the groove, and the surface of the N-type semiconductor layer in the groove is subjected to electron irradiation treatment.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the surface of the N-type semiconductor layer provided with the N-type electrode is subjected to electron irradiation, the microstructure of the crystal of the N-type semiconductor layer is changed, the form and the number of defects in the N-type semiconductor layer are influenced, more nitrogen vacancies are generated under the condition of not changing the proportion of nitrogen elements, the nitrogen vacancies in the N-type semiconductor layer are increased, the incorporation of an N-type dopant is promoted, the incorporation effectiveness of doping elements is improved, the high impurity state caused by heavy doping is changed, the mobility of carriers is improved, the electrical contact between the N-type electrode and the N-type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the whole light emitting diode is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a light emitting diode epitaxial wafer obtained after step 101 of the manufacturing method provided by the embodiment of the invention is executed;
fig. 3 is a schematic structural diagram of an led epitaxial wafer obtained after step 102 of the manufacturing method according to the embodiment of the present invention is executed;
fig. 4 is a schematic structural diagram of a light emitting diode epitaxial wafer obtained after the step 103 of the manufacturing method provided by the embodiment of the invention is executed;
fig. 5 is a schematic structural diagram of an led epitaxial wafer during the step 104 of the manufacturing method according to the embodiment of the present invention;
fig. 6 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a manufacturing method of a light-emitting diode epitaxial wafer. Fig. 1 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 1, the manufacturing method includes:
step 101: a substrate is provided.
Fig. 2 is a schematic structural diagram of a light emitting diode epitaxial wafer obtained after step 101 of the manufacturing method according to the embodiment of the present invention is executed. Wherein 10 denotes a substrate.
Specifically, the material of the substrate may be sapphire (aluminum oxide is a main material), such as sapphire having a crystal orientation of [0001 ].
Specifically, the step 101 may include:
controlling the temperature to be 1000-1200 ℃ (preferably 1100 ℃), and annealing the substrate for 6-10 minutes (preferably 8 minutes) in a hydrogen atmosphere;
the substrate is subjected to a nitridation process.
The surface of the substrate is cleaned by adopting the steps, so that the phenomenon that impurities are doped into the epitaxial wafer to influence the overall crystal quality is avoided, and the luminous efficiency of the LED is reduced.
Step 102: an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate, wherein the N-type semiconductor layer is N-type doped nitride.
Fig. 3 is a schematic structural diagram of a light emitting diode epitaxial wafer obtained after the step 102 of the manufacturing method according to the embodiment of the present invention is executed. Wherein 20 denotes an N-type semiconductor layer, 30 denotes an active layer, and 40 denotes a P-type semiconductor layer. Referring to fig. 3, an N-type semiconductor layer 20, an active layer 30, and a P-type semiconductor layer 40 are sequentially stacked on a substrate 10.
Specifically, the material of the N-type semiconductor layer may employ N-type doped (e.g., silicon) gallium nitride (GaN). The active layer may include a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the quantum well material may be indium gallium nitride (InGaN), such as InxGa1-xN, x is more than 0 and less than 1; the material of the quantum barrier can adopt gallium nitride. The P-type semiconductor layer may be made of P-type doped (e.g., magnesium) gallium nitride.
Further, the thickness of the N-type semiconductor layer may be 1 μm to 5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer may be 1018cm-3～1019cm-3Preferably 5 x 1018cm-3. The number of quantum wells is the same as that of quantum barriers, and the number of quantum barriers can be 3-15 (preferably 9); the thickness of the quantum well may be 2.5nm to 3.5nm (preferably 3nm), and the thickness of the quantum barrier may be 9nm to 20nm (preferably 15 nm). The thickness of the P-type semiconductor layer can be 100nm to 800nm, preferably 450 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer may be 1018cm-3～1019cm-3Preferably 5 x 1018cm-3。
Specifically, this step 102 may include:
a first step of growing an N-type semiconductor layer on a substrate at a temperature of 1000 ℃ to 1200 ℃ (preferably 1100 ℃) and a pressure of 100torr to 500torr (preferably 300 torr);
secondly, growing an active layer on the N-type semiconductor layer; the growth temperature of the quantum well is 720 ℃ to 829 ℃ (preferably 770 ℃), and the growth pressure of the quantum well is 100torr to 500torr (preferably 300 torr); the growth temperature of the quantum barrier is 850 ℃ -959 ℃ (preferably 900 ℃), and the growth pressure of the quantum barrier is 100 torr-500 torr (preferably 300 torr);
and thirdly, controlling the temperature to be 850-1080 ℃ (preferably 960 ℃) and the pressure to be 100-300 torr (preferably 200torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the first step, the manufacturing method may further include:
a buffer layer is grown on a substrate.
The buffer layer is utilized to relieve stress and defects generated by lattice mismatch between the substrate material and the gallium nitride, and provides nucleation centers for epitaxial growth of the gallium nitride material.
Accordingly, an N-type semiconductor layer is grown on the buffer layer.
Specifically, the material of the buffer layer may employ gallium nitride (GaN).
Further, the thickness of the buffer layer may be 15nm to 35nm, preferably 25 nm.
Specifically, growing a buffer layer on a substrate may include:
controlling the temperature to be 400-600 ℃ (preferably 500 ℃), and the pressure to be 400-600 torr (preferably 500torr), and growing a buffer layer on the substrate;
the buffer layer is subjected to in-situ annealing treatment while controlling the temperature to 1000 ℃ to 1200 ℃ (preferably 1100 ℃), the pressure to 400Torr to 600Torr (preferably 500Torr), and the duration to 5 minutes to 10 minutes (preferably 8 minutes).
Preferably, after growing the buffer layer on the substrate, the manufacturing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Stress and defects generated by lattice mismatch between the substrate material and the gallium nitride are further relieved, and a growth surface with good crystal quality is provided for the main body structure of the epitaxial wafer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on the patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer in this embodiment.
Further, the thickness of the undoped gallium nitride layer may be 1 μm to 5 μm, preferably 3 μm.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 100torr to 500torr (preferably 300 torr).
Optionally, before the second step, the manufacturing method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Stress generated by lattice mismatch between sapphire and gallium nitride is released by the stress release layer, so that the crystal quality of the active layer is improved, electrons and holes can radiate and emit light in the active layer in a composite manner, the internal quantum efficiency of the LED is improved, and the luminous efficiency of the LED is improved.
Accordingly, an active layer is grown on the stress relieving layer.
Specifically, the material of the stress release layer can be gallium indium aluminum nitride (AlInGaN), so that the stress generated by lattice mismatch of sapphire and gallium nitride can be effectively released, the crystal quality of an epitaxial wafer is improved, and the luminous efficiency of the LED is improved.
Preferably, the molar content of the aluminum component in the stress release layer may be less than or equal to 0.2, and the molar content of the indium component in the stress release layer may be less than or equal to 0.05, so as to avoid causing adverse effects.
Further, the thickness of the stress release layer may be 50nm to 500nm, preferably 250 nm.
Specifically, growing the stress relief layer on the N-type semiconductor layer may include:
the temperature is controlled to be 800 ℃ to 1100 ℃ (preferably 950 ℃) and the pressure is controlled to be 100torr to 500torr (preferably 300torr), and the stress release layer is grown on the N-type semiconductor layer.
Optionally, before the third step, the manufacturing method may further include:
an electron blocking layer is grown on the active layer.
The electron blocking layer is used for preventing electrons from jumping into the P-type semiconductor layer to be non-radiatively combined with holes, and the luminous efficiency of the LED is reduced.
Specifically, the electron blocking layer may be made of P-type doped aluminum gallium nitride (AlGaN) such as AlyGa1-yN，0.1＜y＜0.5。
Further, the thickness of the electron blocking layer may be 50nm to 150nm, preferably 100 nm.
Specifically, growing an electron blocking layer on the active layer may include:
the temperature is controlled to be 850 ℃ to 1080 ℃ (preferably 960 ℃), the pressure is controlled to be 200torr to 500torr (preferably 350torr), and the electron blocking layer is grown on the active layer.
Preferably, before growing the electron blocking layer on the active layer, the manufacturing method may further include:
a low temperature P-type layer is grown on the active layer.
The low-temperature P-type layer is used for preventing indium atoms in the active layer from being separated out due to the high growth temperature of the electron blocking layer and influencing the light emitting efficiency of the light emitting diode.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, the material of the low-temperature P-type layer may be the same as that of the P-type semiconductor layer. In this embodiment, the material of the low temperature P-type layer may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low-temperature P-type layer may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after step 102, the manufacturing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, the contact layer may be made of P-type doped (e.g., mg) indium gallium nitride (ingan) or gallium nitride (gan).
Further, the thickness of the contact layer may be 5nm to 300nm, preferably 150 nm; the doping concentration of the P-type dopant in the contact layer may be 1021/cm3～1022/cm3Preferably 5 x 1021cm-3。
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the above step, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature, thereby ending the epitaxial growth process.
The control of temperature and pressure refers to controlling the temperature and pressure in a reaction chamber for growing epitaxial wafers, such as the temperature and pressure in a Metal Organic Chemical Vapor Deposition (MOCVD) equipment with the model of VeecoK465i C4. During implementation, high-purity hydrogen or high-purity nitrogen or mixed gas of hydrogen and nitrogen is used as carrier gas, high-purity ammonia gas is used as a nitrogen source, trimethyl gallium or triethyl gallium is used as a gallium source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as an N-type dopant, and dicyclopentadienyl magnesium is used as a P-type dopant.
Step 103: and a groove extending to the N-type semiconductor is formed on the P-type semiconductor layer.
Fig. 4 is a schematic structural diagram of a light emitting diode epitaxial wafer obtained after the step 103 of the manufacturing method according to the embodiment of the present invention is executed. Wherein 100 denotes a groove. Referring to fig. 4, the groove 100 extends from the P-type semiconductor layer 40 to the N-type semiconductor layer 20.
Specifically, the step 103 may include:
forming photoresist with a set pattern on the P-type semiconductor layer by adopting a photoetching technology, wherein the photoresist with the set pattern is arranged on a region except the region where the groove is located;
forming a groove extending to the N-type semiconductor layer on the P-type semiconductor layer by adopting a dry etching technology;
and removing the photoresist.
In the specific implementation, when the photoresist with the set pattern is formed on the P-type semiconductor layer by adopting the photoetching technology, a layer of photoresist is firstly paved on the P-type semiconductor layer, then the photoresist is exposed through a mask with a certain pattern, and finally the exposed photoresist is soaked in a developing solution, so that the photoresist with the set pattern can be obtained.
It is easy to know that if a contact layer is grown on the P-type semiconductor layer, the groove extends from the contact layer to the N-type semiconductor layer.
Step 104: and carrying out electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the surface of the N-type semiconductor layer in the groove is used for arranging an N-type electrode.
In this embodiment, Electron irradiation (English: Electron irradiation) is used to irradiate the material with high-energy Electron beams, which causes the crystal atoms to shift, and improves the material performance.
Fig. 5 is a schematic structural diagram of an led epitaxial wafer during the step 104 of the manufacturing method according to the embodiment of the present invention. Referring to fig. 5, electron irradiation (indicated by arrows in fig. 5) acts on the N-type semiconductor layer within the groove 100.
According to the embodiment of the invention, the electron irradiation is carried out on the surface of the N-type semiconductor layer provided with the N-type electrode, the microstructure of the N-type semiconductor layer crystal is changed, the form and the number of defects in the N-type semiconductor layer are influenced, more nitrogen vacancies are generated under the condition of not changing the proportion of nitrogen elements, the nitrogen vacancies in the N-type semiconductor layer are increased, the incorporation of an N-type dopant is promoted, the incorporation effectiveness of a doping element is improved, the high impurity state caused by heavy doping is changed, the mobility of carriers is improved, the electrical contact between the N-type electrode and the N-type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the whole light emitting diode is improved.
Alternatively, the radiation dose of electron irradiation may be 1016/cm2～1022/cm2Preferably 1019/cm2。
If the radiation dose of the electron irradiation is less than 1016/cm2If the radiation dose of electron irradiation is too small, nitrogen vacancies in the N-type semiconductor layer cannot be effectively increased, and the light efficiency improvement effect of the light emitting diode is not obvious; if the radiation dose of the electron irradiation is more than 1022/cm2The radiation dose of the electric radiation is too much, which may affect the main structure of the N-type semiconductor layer crystal, and may reduce the light efficiency of the light emitting diode.
Wherein the radiation dose is the total number of electrons radiated per unit area of the electron irradiation surface.
Alternatively, the temperature of the environment in which the N-type semiconductor layer is exposed when the electrons are irradiated may be 20 to 150 ℃, preferably 85 ℃.
Alternatively, the pressure of the environment in which the N-type semiconductor layer is exposed when the electrons are irradiated may be 5Torr to 50Torr, for example, 28 Torr.
Optionally, this step 104 may include:
an Electron beam provided by a Transmission Electron Microscope (TEM) is used as a light source to irradiate the surface of the N-type semiconductor layer in the groove.
The existing equipment is directly adopted for electron irradiation, and the realization is simpler and more convenient.
In particular, the transmission electron microscope may include an electron gun, a condenser, a sample chamber, an objective lens, an intermediate mirror, a transmission mirror, and the like. The electron gun (electronic gun) is used for emitting electrons and comprises a cathode, a gate and an anode.
The cathode is the source of the free electrons. In a TEM, a heating filament (filament) is usually used as a cathode, and the material of the filament may be tungsten or lanthanum hexaboride. When a heating current of several amperes flows through the filament, the filament starts to emit free electrons based on a field electron emission or thermionic emission mechanism. Within a certain range, the quantity of free electrons emitted by the filament is in direct proportion to the intensity of the heating current.
The anode is a metal cylinder with a hollow center. The anode is below the cathode. When tens or hundreds of kilovolts of accelerating voltage is applied to the anode, strong attraction effect is generated on the free electrons emitted by the heated cathode, the disordered state is changed into ordered directional motion, and the free electrons are accelerated to a certain motion speed to form a beam which is emitted to the target surface of the anode. The electron beam moving on the axis emits the electron beam out of the electron gun through the circular hole in the center of the anode to become the light source for irradiating the sample.
The grid is located between the cathode and the anode, near the top of the filament. The grid is a metal object shaped like a cap, and a small hole is arranged in the center of the grid for electron beams to pass through. A negative voltage (for a cathode) of 0-1000V is added on the grid electrode, and the negative voltage (called as grid bias) can enable the electron beam to generate the action of converging towards a central axis and has a certain regulation and inhibition effect on the emission quantity of free electrons on the filament.
When the transmission electron microscope works, under the action of the filament power supply, current flows through the filament cathode, so that the filament generates heat. When the filament generates heat to over 2500 ℃, the filament generates free electrons, and the generated free electrons escape from the surface of the filament. Meanwhile, the accelerating voltage enables the surface of the anode to gather dense positive charges, and a strong positive electric field is formed. Under the action of this positive field, free electrons fly out of the electron gun. In addition, the magnitude of the electron beam flux can be controlled by adjusting the magnitude of the grid bias voltage.
In practical applications, an electron beam provided by a TEM of 200 kilo electron volts (keV) may be used as a light source. Further, the power supply of the TEM may employ a high voltage source of up to 10-30 kilovolts. The radiation dose of electron irradiation is 10 by controlling the heating current of the cathode in the TEM, the accelerating voltage of the anode in the TEM, the grid bias voltage of the grid in the TEM and the duration of the electron irradiation16/cm2～1022/cm2。
Preferably, the diameter of the electron beam may be 8 μm to 30 μm, preferably 19 μm.
If the diameter of the electron beam is smaller than 8 μm, the electron beam may be too concentrated due to too small diameter of the electron beam, and thus the main structure of the N-type semiconductor layer is damaged, and the light emitting efficiency of the LED is affected; if the diameter of the electron beam is greater than 30 μm, the electron beam may be too dispersed due to too large diameter of the electron beam, so that nitrogen vacancies in the N-type semiconductor layer cannot be effectively increased, and the light efficiency improvement effect of the light emitting diode is not significant.
Optionally, after step 104, the manufacturing method may further include:
and annealing the N-type semiconductor layer in the groove.
And eliminating partial defects and impurity states through annealing treatment.
Optionally, the temperature of the annealing treatment can be 700-900 ℃, and the realization effect is better.
Optionally, the contact layer may be in a nitrogen atmosphere during the annealing process, so as to achieve a better effect.
Preferably, the vacuum degree of the nitrogen atmosphere may be 10-8Torr～10-6Torr, the realization effect is better.
Optionally, the duration of the annealing treatment can be 15min to 50min, so that the realization effect is good.
In an implementation manner of this embodiment, when the surface of the P-type semiconductor layer is used for disposing the P-type electrode, the manufacturing method may further include:
and performing electron irradiation on the surface of the P-type semiconductor layer to increase nitrogen vacancies in the P-type semiconductor layer, wherein the P-type semiconductor layer is P-type doped nitride.
The electron irradiation is carried out on the surface of the P type semiconductor layer, the microstructure of the crystal of the P type semiconductor layer is changed, the form and the number of defects in the P type semiconductor layer are influenced, more nitrogen vacancies are generated under the condition of not changing the proportion of nitrogen elements, the nitrogen vacancies in the P type semiconductor layer are increased, the incorporation of a P type dopant is promoted, the incorporation effectiveness of doping elements is improved, the high impurity state caused by heavy doping is changed, the mobility of carriers is improved, the electrical contact between a P type electrode and the P type semiconductor layer is improved, the series resistance is reduced, and the light efficiency of the whole light emitting diode is improved.
In practical application, the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove can be subjected to electron irradiation simultaneously, so that the process steps are saved, the realization is convenient, and the realization cost is reduced. The surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove may be subjected to electron irradiation, for example, after the P-type semiconductor layer is grown, the surface of the P-type semiconductor layer is subjected to electron irradiation, and then the groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, and the surface of the N-type semiconductor layer in the groove is subjected to electron irradiation.
Specifically, the parameters for electron irradiation on the surface of the P-type semiconductor layer may be the same as those for electron irradiation on the surface of the N-type semiconductor layer in the groove, for example, the radiation dose of electron irradiation is 1016/cm2～1022/cm2。
Optionally, in the foregoing implementation, the manufacturing method may further include:
after the surface of the P-type semiconductor layer is subjected to electron irradiation, annealing treatment is performed on the P-type semiconductor layer.
Specifically, the parameters of annealing the P-type semiconductor layer may be the same as those of annealing the N-type semiconductor layer in the groove, for example, the temperature of annealing is 700 to 900 ℃.
In another implementation manner of this embodiment, when the surface of the contact layer is used for disposing the P-type electrode, the manufacturing method may further include:
and (3) carrying out electron irradiation on the surface of the contact layer to increase nitrogen vacancies in the contact layer.
Through carrying out electron irradiation to the surface of contact layer, change the microstructure of contact layer crystal, influence the form and the quantity of defect in the contact layer, produce more nitrogen vacancy under the condition that does not change the nitrogen element proportion, increase the nitrogen vacancy in the contact layer, promote incorporating into of P type dopant, improve the validity that doping element incorporated into, change the high impurity state because the heavy doping leads to, improve the mobility of carrier, improve the electricity contact of electrode and contact layer, reduce series resistance, improve whole emitting diode's light efficiency.
In practical application, the surface of the contact layer and the surface of the N-type semiconductor layer in the groove can be subjected to electron irradiation simultaneously, so that the process steps are saved, the realization is convenient, and the realization cost is reduced. The surface of the contact layer and the surface of the N-type semiconductor layer in the groove may also be subjected to electron irradiation, for example, after the contact layer is grown, the surface of the contact layer is subjected to electron irradiation, and then the groove extending to the N-type semiconductor layer is formed in the contact layer, and the surface of the N-type semiconductor layer in the groove is subjected to electron irradiation.
Specifically, the parameters for electron irradiation on the surface of the contact layer may be the same as those for electron irradiation on the surface of the N-type semiconductor layer in the groove, for example, the radiation dose of electron irradiation is 1016/cm2～1022/cm2。
Optionally, in the foregoing implementation, the manufacturing method may further include:
after the surface of the contact layer is subjected to electron irradiation, the contact layer is subjected to annealing treatment.
Specifically, the parameters of annealing the contact layer may be the same as those of annealing the N-type semiconductor layer in the groove, for example, the temperature of annealing is 700 to 900 ℃.
One specific implementation of the preparation method shown in fig. 1 may include:
step 201: controlling the temperature at 1100 deg.C and the pressure at 300torr, and growing an N-type semiconductor layer with a thickness of 3 μm on the substrate, wherein the doping concentration of N-type dopant in the N-type semiconductor layer is 5 × 1018cm-3。
Step 202: growing an active layer on the N-type semiconductor layer; the active layer comprises 9 quantum wells and 9 quantum barriers which are alternately grown; the thickness of the quantum well is 3nm, the growth temperature of the quantum well is 770 ℃, and the growth pressure of the quantum well is 300 torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900 ℃, and the growth pressure of the quantum barrier is 300 torr.
Step 203: controlling the temperature to 960 deg.C and the pressure to 200torr, growing a P-type semiconductor layer with a thickness of 450nm on the active layer, wherein the doping concentration of the P-type dopant in the P-type semiconductor layer is 5 × 1018cm-3。
Step 204: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Step 205: performing electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the radiation dose of the electron irradiation is 1016/cm2。
Compared with the mode that the N-type semiconductor layer in the groove is not subjected to electron irradiation, the light efficiency of the chip is improved by 3% -5%.
Another specific implementation of the preparation method shown in fig. 1 may include:
step 301: growing the film with a thickness of 3 μm on a substrate at a controlled temperature of 1100 deg.C and a pressure of 300torrAn N-type semiconductor layer with an N-type dopant doping concentration of 5 × 1018cm-3。
Step 302: growing an active layer on the N-type semiconductor layer; the active layer comprises 9 quantum wells and 9 quantum barriers which are alternately grown; the thickness of the quantum well is 3nm, the growth temperature of the quantum well is 770 ℃, and the growth pressure of the quantum well is 300 torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900 ℃, and the growth pressure of the quantum barrier is 300 torr.
Step 303: controlling the temperature to 960 deg.C and the pressure to 200torr, growing a P-type semiconductor layer with a thickness of 450nm on the active layer, wherein the doping concentration of the P-type dopant in the P-type semiconductor layer is 5 × 1018cm-3。
Step 304: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Step 305: performing electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the radiation dose of the electron irradiation is 1019/cm2。
Compared with the mode that the N-type semiconductor layer in the groove is not subjected to electron irradiation, the light efficiency of the chip is improved by 5% -7%.
Still another specific implementation of the preparation method shown in fig. 1 may include:
step 401: controlling the temperature at 1100 deg.C and the pressure at 300torr, and growing an N-type semiconductor layer with a thickness of 3 μm on the substrate, wherein the doping concentration of N-type dopant in the N-type semiconductor layer is 5 × 1018cm-3。
Step 402: growing an active layer on the N-type semiconductor layer; the active layer comprises 9 quantum wells and 9 quantum barriers which are alternately grown; the thickness of the quantum well is 3nm, the growth temperature of the quantum well is 770 ℃, and the growth pressure of the quantum well is 300 torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900 ℃, and the growth pressure of the quantum barrier is 300 torr.
Step 403: controlling the temperature to 960 deg.C and the pressure to 200torr, and growing a P-type semiconductor layer with a thickness of 450nm on the active layerDoping concentration of medium P type dopant is 5 x 1018cm-3。
Step 404: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Step 405: performing electron irradiation on the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove, wherein the radiation dose of the electron irradiation is 1022/cm2。
Compared with the mode that the N-type semiconductor layer in the groove is not subjected to electron irradiation, the light efficiency of the chip is improved by 2% -3%.
Still another specific implementation of the preparation method shown in fig. 1 may include:
step 501: controlling the temperature at 1100 deg.C and the pressure at 300torr, and growing an N-type semiconductor layer with a thickness of 3 μm on the substrate, wherein the doping concentration of N-type dopant in the N-type semiconductor layer is 5 × 1018cm-3。
Step 502: growing an active layer on the N-type semiconductor layer; the active layer comprises 9 quantum wells and 9 quantum barriers which are alternately grown; the thickness of the quantum well is 3nm, the growth temperature of the quantum well is 770 ℃, and the growth pressure of the quantum well is 300 torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900 ℃, and the growth pressure of the quantum barrier is 300 torr.
Step 503: controlling the temperature to 960 deg.C and the pressure to 200torr, growing a P-type semiconductor layer with a thickness of 450nm on the active layer, wherein the doping concentration of the P-type dopant in the P-type semiconductor layer is 5 × 1018cm-3。
Step 504: and a groove extending to the N-type semiconductor layer is formed on the P-type semiconductor layer.
Step 505: performing electron irradiation on the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the P-type semiconductor layer and the N-type semiconductor layer in the groove, wherein the radiation dose of the electron irradiation is 1019/cm2。
Compared with the mode that the P-type semiconductor layer and the N-type semiconductor layer in the groove are not subjected to electron irradiation, the light efficiency of the chip is improved by 5% -7%.
One specific implementation of the preparation method shown in fig. 1 may include:
step 601: controlling the temperature at 1100 deg.C and the pressure at 300torr, and growing an N-type semiconductor layer with a thickness of 3 μm on the substrate, wherein the doping concentration of N-type dopant in the N-type semiconductor layer is 5 × 1018cm-3。
Step 602: growing an active layer on the N-type semiconductor layer; the active layer comprises 9 quantum wells and 9 quantum barriers which are alternately grown; the thickness of the quantum well is 3nm, the growth temperature of the quantum well is 770 ℃, and the growth pressure of the quantum well is 300 torr; the thickness of the quantum barrier is 15nm, the growth temperature of the quantum barrier is 900 ℃, and the growth pressure of the quantum barrier is 300 torr.
Step 603: controlling the temperature to 960 deg.C and the pressure to 200torr, growing a P-type semiconductor layer with a thickness of 450nm on the active layer, wherein the doping concentration of the P-type dopant in the P-type semiconductor layer is 5 × 1018cm-3。
Step 604: and controlling the temperature to 950 ℃ and the pressure to 200torr, and growing a contact layer with the thickness of 150nm on the P-type semiconductor layer.
Step 605: and a groove extending to the N-type semiconductor layer is formed on the contact layer.
Step 606: performing electron irradiation on the surfaces of the contact layer and the N-type semiconductor layer in the groove to increase nitrogen vacancies in the contact layer and the N-type semiconductor layer in the groove, wherein the radiation dose of the electron irradiation is 1019/cm2。
Compared with the mode that the N-type semiconductor layer in the contact layer and the groove is not subjected to electron irradiation, the light efficiency of the chip is improved by 8% -10%.
The embodiment of the invention provides a light emitting diode epitaxial wafer which is suitable for being manufactured by adopting the manufacturing method shown in FIG. 1. Fig. 6 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 6, the light emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, an active layer 30, and a P-type semiconductor layer 40, and the N-type semiconductor layer 20, the active layer 30, and the P-type semiconductor layer 40 are sequentially stacked on the substrate 10. The P-type semiconductor layer 40 is provided with a groove 100 extending to the N-type semiconductor layer 20, and the surface of the N-type semiconductor layer 20 in the groove 100 is used for arranging an N-type electrode.
In the present embodiment, the surface of the N-type semiconductor layer 20 in the groove 100 is the surface subjected to the electron irradiation treatment.
Alternatively, as shown in fig. 6, the light emitting diode epitaxial wafer may further include a buffer layer 51, and the buffer layer 51 is disposed between the substrate 10 and the N-type semiconductor layer 20.
Preferably, as shown in fig. 6, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 52, and the undoped gallium nitride layer 52 is disposed between the buffer layer 51 and the N-type semiconductor layer 20.
Optionally, as shown in fig. 6, the light emitting diode epitaxial wafer may further include a stress relief layer 60, and the stress relief layer 60 is disposed between the N-type semiconductor layer 20 and the active layer 30.
Optionally, as shown in fig. 6, the light emitting diode epitaxial wafer may further include an electron blocking layer 71, and the electron blocking layer 71 is disposed between the active layer 30 and the P-type semiconductor layer 40.
Preferably, as shown in fig. 6, the light emitting diode epitaxial wafer may further include a low temperature P-type layer 72, and the low temperature P-type layer 72 is disposed between the active layer 30 and the electron blocking layer 71.
Optionally, as shown in fig. 6, the light emitting diode epitaxial wafer may further include a contact layer 80, and the contact layer 80 is disposed on the P-type semiconductor layer 40.
In one implementation of the embodiment, when the surface of the contact layer is used for disposing the P-type electrode, the surface of the contact layer may be a surface subjected to electron irradiation treatment.
In another implementation manner of the present embodiment, when the surface of the P-type semiconductor layer is used to provide a P-type electrode, the surface of the P-type semiconductor layer 40 may be a surface subjected to electron irradiation treatment.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (4)

1. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate, wherein the N-type semiconductor layer is N-type doped nitride, and the P-type semiconductor layer is P-type doped nitride;
forming a groove extending to the N-type semiconductor on the P-type semiconductor layer;
simultaneously carrying out electron irradiation on the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the P-type semiconductor layer and the N-type semiconductor layer in the groove, wherein the surface of the N-type semiconductor layer in the groove is used for arranging an N-type electrode, the P-type semiconductor layer is used for arranging a P-type electrode, and the radiation dose of the electron irradiation is 1016/cm2～1022/cm2The doping concentration of the P type dopant in the P type semiconductor layer and the doping concentration of the N type dopant in the N type semiconductor layer are 1018cm-3～1019cm-3；
And annealing the P-type semiconductor layer and the N-type semiconductor layer in the groove.
2. The method for manufacturing according to claim 1, wherein the step of irradiating electrons to the surface of the N-type semiconductor layer in the groove to increase nitrogen vacancies in the N-type semiconductor layer in the groove comprises:
and irradiating the surface of the N-type semiconductor layer in the groove by using an electron beam provided by a transmission electron microscope as a light source.
3. The method of claim 2, wherein the diameter of the electron beam is 8 μm to 30 μm.
4. Hair-like hairThe light-emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate, the N-type semiconductor layer is N-type doped nitride, the P-type semiconductor layer is P-type doped nitride, a groove extending to the N-type semiconductor layer is formed in the P-type semiconductor layer, an N-type electrode is arranged on the surface of the N-type semiconductor layer in the groove, the P-type semiconductor layer is used for arranging a P-type electrode, the light-emitting diode epitaxial wafer is characterized in that the surface of the P-type semiconductor layer and the surface of the N-type semiconductor layer in the groove are surfaces subjected to electron irradiation and annealing treatment, and the radiation dose of the electron irradiation is 1016/cm2～1022/cm2The doping concentration of the P type dopant in the P type semiconductor layer and the doping concentration of the N type dopant in the N type semiconductor layer are 1018cm-3～1019cm-3。
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