CN109346523A - Trench-gate field effect transistors and its manufacturing method with super-junction structures - Google Patents
Trench-gate field effect transistors and its manufacturing method with super-junction structures Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 26
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007773 growth pattern Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- XCKKIKBIPZJUET-VYKNHSEDSA-N morphine hydrochloride Chemical compound Cl.O([C@H]1[C@H](C=C[C@H]23)O)C4=C5[C@@]12CCN(C)[C@@H]3CC5=CC=C4O XCKKIKBIPZJUET-VYKNHSEDSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a kind of trench-gate field effect transistors and its manufacturing method with super-junction structures, belong to technical field of semiconductors.Trench-gate field effect transistors with super-junction structures of the invention, it is with silica deep trouth, and there is P-type layer and N-type extension around the deep trouth, to compared with existing super-junction structure MOSFET, its conducting resistance is smaller, simultaneously because grid and the contact area of drain electrode are smaller, and there is silica deep trench isolation, so gate leakage capacitance is smaller, switching speed is faster, and then further improve device overall performance, and of the invention its structure of the trench-gate field effect transistors with super-junction structures is simple, it is easy to generate manufacturing method, production and application cost also relative moderate.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to field effect transistor technical field, in particular to a kind of tool
There are the trench-gate field effect transistors and its manufacturing method of super-junction structures.
Background technique
Quick hair with the rapid development of electronic information technology, especially as fashional consumption electronics and portable product
Exhibition, the demand of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) constant power device is increasing, and MOSFET is main
It is divided into horizontal and vertical two kinds, the clear superiority of (Silicon-on-insulator) MOSFET lateral is its preferable integration, can be easier to be integrated into existing
On the technique platform of technology, but due to the drift region surface spreading of its pressure resistance, its maximum deficiency, the face of occupancy are shown
Larger, the area representative cost of product, the higher device of pressure resistance, disadvantage is more obvious, and vertical nMOSFET avoids this well and asks
Topic, therefore, the discrete device of super-pressure is still based on longitudinal direction.
However, conducting resistance is presented 2.5 power indexes relative to breakdown voltage and increases with the continuous increase of applied voltage
Greatly, conducting resistance size just determines to bear the size of current capacity, and then determines the area of device, so that cost is influenced,
In the case where not changing substrate material, the appearance of superjunction changes this relationship, and the breakdown voltage and conducting resistance of superjunction are almost
It is linear, therefore superjunction advantage is clearly, the concept that charge balance is utilized in superjunction can accomplish EPI more highly concentrated
Degree, effectively reduces conducting resistance, but how to further decrease conducting resistance, improves switching speed, and then promote device performance,
As this field urgent problem to be solved.
Summary of the invention
The purpose of the present invention is overcome it is above-mentioned in the prior art the shortcomings that, provide it is a kind of there is silica deep trouth, and
There is P-type layer and N-type extension around the deep trouth, while further decreasing conducting resistance, switching speed is improved, so as to mention
Rise the trench-gate field effect transistors and its manufacturing method with super-junction structures of device overall performance.
In order to achieve the above purpose, the manufacturer of the trench-gate field effect transistors with super-junction structures of the invention
Method, comprising the following steps:
(1) deep trouth is etched in the N- epitaxial layer of the substrate as drain electrode；
(2) P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth inner wall；
(3) silica is filled in the deep trouth；
(4) in the deep trouth and the top etching grid groove of N- epitaxial layer, gate oxidation is carried out, and fills polysilicon,
Form grid；
(5) source electrode is formed in top device.
In the manufacturing method of the trench-gate field effect transistors with super-junction structures, the step (1) is specifically wrapped
Include following steps:
(11) N- epitaxial layer is grown on the N+ substrate as drain electrode；
(12) in the top mask film covering of the N- epitaxial layer；
(13) deep trouth is etched in the N- epitaxial layer.
In the manufacturing method of the trench-gate field effect transistors with super-junction structures, the step (2) is specifically wrapped
Include following steps:
(21) vertically, first time P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth bottom；
(22) angled, second of P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth side wall；
(23) exposure mask is removed.
In the manufacturing method of the trench-gate field effect transistors with super-junction structures, the step (5) is specifically wrapped
Include following steps:
(51) P- is carried out on the top of the N- epitaxial layer to inject to form P- body area；
(52) at the top in the P- body area, N+ injection is carried out along the gate trench, forms the area N+, and adjacent
P+ injection is carried out between the area N+ of two devices；
(53) last part technology is utilized, source electrode is formed.
The present invention also provides using made of above-mentioned manufacturing method with the trench-gate field effect transistors of super-junction structures,
Comprising:
Substrate, as drain electrode；
N- epitaxial layer is located at the substrate；
Silica deep trouth is formed in the N- epitaxial layer；
Gate trench is formed at the top of the silica deep trouth and the N- epitaxial layer；
Source electrode is formed in top device.
In the trench-gate field effect transistors with super-junction structures, the silica of the silica deep trouth is filled out
Fill has P- layers between deep trouth inner wall.
The trench-gate field effect transistors with super-junction structures further include:
P- body area is formed in the top of the N- epitaxial layer；
The area N+ is formed in the top in the P- body area along the gate trench；
The area P+ is formed between the area N+ of two neighboring device.
Using the trench-gate field effect transistors and its manufacturing method with super-junction structures of the invention, the transistor
With silica deep trouth, and there is P-type layer and N-type extension around the deep trouth, thus with existing super-junction structure MOSFET phase
Than conducting resistance is smaller, simultaneously because grid and the contact area of drain electrode are smaller, and has silica deep trench isolation, institute
Smaller with gate leakage capacitance, switching speed faster, and then further improves device overall performance, and of the invention has super junction
Its structure of the trench-gate field effect transistors of structure is simple, and it is easy to generate manufacturing method, production and application cost also relative moderate.
Detailed description of the invention
Fig. 1 is the conventional Super junction composition in the prior art with the P column formed by EPI growth pattern.
Fig. 2 is the conventional Super junction composition that another kind has the P column formed by EPI growth pattern in the prior art
Fig. 3 is the step process of the manufacturing method of the trench-gate field effect transistors with super-junction structures of the invention
Figure.
Fig. 4 is the schematic diagram of deep etching step in the manufacturing method of the present invention.
Fig. 5 is the schematic diagram of P-type first time injection step in the manufacturing method of the present invention.
Fig. 6 is the schematic diagram of second of injection step of P-type in the manufacturing method of the present invention.
Fig. 7 is the schematic diagram of filling silica step in groove in the manufacturing method of the present invention.
Fig. 8 is gate trench etching, the schematic diagram of gate oxidation and polysilicon filling step in the manufacturing method of the present invention.
Fig. 9 is the schematic diagram of P-body injection step in the manufacturing method of the present invention.
Figure 10 is the schematic diagram of N+ and P+ injection step in the manufacturing method of the present invention.
Figure 11 is the signal of the trench-gate field effect transistors with super-junction structures manufactured using method of the invention
Figure.
Specific embodiment
In order to be more clearly understood that technology contents of the invention, spy lifts following embodiment and is described in detail.
Refering to Figure 1, being the manufacturing method of the trench-gate field effect transistors with super-junction structures of the invention
Step flow chart.
In one embodiment, the manufacturing method of the trench-gate field effect transistors with super-junction structures, such as Fig. 3
It is shown, comprising the following steps:
(1) deep trouth is etched in the N- epitaxial layer of the substrate as drain electrode；
(2) P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth inner wall；
(3) silica is filled in the deep trouth；
(4) in the deep trouth and the top etching grid groove of N- epitaxial layer, gate oxidation is carried out, and fills polysilicon,
Form grid；
(5) source electrode is formed in top device.
In a preferred embodiment, the step (1) specifically includes the following steps:
(11) N- epitaxial layer is grown on the N+ substrate as drain electrode；
(12) in the top mask film covering of the N- epitaxial layer；
(13) deep trouth is etched in the N- epitaxial layer.
In another preferred embodiment, the step (2) specifically includes the following steps:
(21) vertically, first time P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth bottom；
(22) angled, second of P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth side wall；
(23) exposure mask is removed.
In preferred embodiment, the step (5) specifically includes the following steps:
(51) P- is carried out on the top of the N- epitaxial layer to inject to form P- body area；
(52) at the top in the P- body area, N+ injection is carried out along the gate trench, forms the area N+, and adjacent
P+ injection is carried out between the area N+ of two devices；
(53) last part technology is utilized, source electrode is formed.
The present invention also provides utilize the trench-gate field effect transistors made of above-mentioned manufacturing method with super-junction structures.
In one embodiment, the trench-gate field effect transistors with super-junction structures, comprising:
Substrate, as drain electrode；
N- epitaxial layer is located at the substrate；
Silica deep trouth is formed in the N- epitaxial layer；
Gate trench is formed at the top of the silica deep trouth and the N- epitaxial layer；
Source electrode is formed in top device.
In a preferred embodiment, the silica-filled of the silica deep trouth has between deep trouth inner wall
P- layers.
In preferred embodiment, the trench-gate field effect transistors with super-junction structures further include:
P- body area is formed in the top of the N- epitaxial layer；
The area N+ is formed in the top in the P- body area along the gate trench；
The area P+ is formed between the area N+ of two neighboring device.
In an application of the invention, the main production of the trench-gate field effect transistors with super-junction structures of the invention
Step includes:
1, as shown in figure 4, deep etching；
2, as shown in figure 5, P-type injects for the first time；
3, as shown in fig. 6, second of P-type is injected；
4, as shown in fig. 7, filling silica in groove；
5, as shown in figure 8, gate trench etches, gate oxidation and polysilicon filling；
6, as shown in figure 9, P-body injects；
7, as shown in Figure 10, N+ and P+ injection；
8, backend process forms final structure as shown in figure 11.
The structure of inventive silica deep trouth combination P embracing layer is epitaxially formed charge balance with N-type to realize preferably
Performance.Specifically, the present invention is compared with conventional planar grid structure shown in FIG. 1, because without the presence of JFET resistance,
Conducting resistance is smaller；Compared with traditional trench gate structure shown in Fig. 2, since grid and the contact area of drain electrode are smaller, and
And have silica deep trench isolation, so gate leakage capacitance is smaller, switching speed is faster.
Using the trench-gate field effect transistors and its manufacturing method with super-junction structures of the invention, the transistor
With silica deep trouth, and there is P-type layer and N-type extension around the deep trouth, thus with existing super-junction structure MOSFET phase
Than conducting resistance is smaller, simultaneously because grid and the contact area of drain electrode are smaller, and has silica deep trench isolation, institute
Smaller with gate leakage capacitance, switching speed faster, and then further improves device overall performance, and of the invention has super junction
Its structure of the trench-gate field effect transistors of structure is simple, and it is easy to generate manufacturing method, production and application cost also relative moderate.
In this description, the present invention is described with reference to its specific embodiment.But it is clear that can still make
Various modifications and alterations are without departing from the spirit and scope of the invention.Therefore, the description and the appended drawings should be considered as illustrative
And not restrictive.
Claims (8)
1. a kind of manufacturing method of the trench-gate field effect transistors with super-junction structures, which is characterized in that this method includes
Following steps:
(1) deep trouth is etched in the N- epitaxial layer of the substrate as drain electrode；
(2) P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth inner wall；
(3) silica is filled in the deep trouth；
(4) in the deep trouth and the top etching grid groove of N- epitaxial layer, gate oxidation is carried out, and fills polysilicon, is formed
Grid；
(5) source electrode is formed in top device.
2. the manufacturing method of the trench-gate field effect transistors according to claim 1 with super-junction structures, feature
Be, the step (1) specifically includes the following steps:
(11) N- epitaxial layer is grown on the N+ substrate as drain electrode；
(12) in the top mask film covering of the N- epitaxial layer；
(13) deep trouth is etched in the N- epitaxial layer.
3. the manufacturing method of the trench-gate field effect transistors according to claim 1 with super-junction structures, feature
Be, the step (2) specifically includes the following steps:
(21) vertically, first time P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth bottom；
(22) angled, second of P- injection is carried out in the deep trouth, and P- layers are formed on deep trouth side wall；
(23) exposure mask is removed.
4. the manufacturing method of the trench-gate field effect transistors according to claim 1 with super-junction structures, feature
Be, the step (5) specifically includes the following steps:
(51) P- is carried out on the top of the N- epitaxial layer to inject to form P- body area；
(52) at the top in the P- body area, N+ injection is carried out along the gate trench, forms the area N+, and two neighboring
P+ injection is carried out between the area N+ of device；
(53) last part technology is utilized, source electrode is formed.
5. a kind of trench-gate field effect transistors with super-junction structures, which is characterized in that appoint using in Claims 1-4 4
Manufacturing method described in one is made.
6. the trench-gate field effect transistors according to claim 5 with super-junction structures characterized by comprising
Substrate, as drain electrode；
N- epitaxial layer is located at the substrate；
Silica deep trouth is formed in the N- epitaxial layer；
Gate trench is formed at the top of the silica deep trouth and the N- epitaxial layer；
Source electrode is formed in top device.
7. the trench-gate field effect transistors according to claim 6 with super-junction structures, which is characterized in that described
The silica-filled of silica deep trouth has P- layers between deep trouth inner wall.
8. the trench-gate field effect transistors according to claim 6 with super-junction structures, which is characterized in that also wrap
It includes:
P- body area is formed in the top of the N- epitaxial layer；
The area N+ is formed in the top in the P- body area along the gate trench；
The area P+ is formed between the area N+ of two neighboring device.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110127601A1 (en) * | 2009-12-02 | 2011-06-02 | Suku Kim | Semiconductor Devices and Methods for Making the Same |
| CN103035720A (en) * | 2012-09-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device and manufacturing method thereof |
| CN103594348A (en) * | 2012-08-17 | 2014-02-19 | 茂达电子股份有限公司 | Method for manufacturing semiconductor element with low miller capacitance |
| US20140099762A1 (en) * | 2011-12-16 | 2014-04-10 | Anpec Electronics Corporation | Manufacturing method of trench type power transistor device with super junction |
| CN107919398A (en) * | 2017-12-13 | 2018-04-17 | 深圳市晶特智造科技有限公司 | Half superjunction devices and its manufacture method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110127601A1 (en) * | 2009-12-02 | 2011-06-02 | Suku Kim | Semiconductor Devices and Methods for Making the Same |
| US20140099762A1 (en) * | 2011-12-16 | 2014-04-10 | Anpec Electronics Corporation | Manufacturing method of trench type power transistor device with super junction |
| CN103594348A (en) * | 2012-08-17 | 2014-02-19 | 茂达电子股份有限公司 | Method for manufacturing semiconductor element with low miller capacitance |
| CN103035720A (en) * | 2012-09-05 | 2013-04-10 | 上海华虹Nec电子有限公司 | Super junction device and manufacturing method thereof |
| CN107919398A (en) * | 2017-12-13 | 2018-04-17 | 深圳市晶特智造科技有限公司 | Half superjunction devices and its manufacture method |
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Effective date of registration: 20191119 Address after: 510700 Room 303, building 1, No. 23, Jinzhong Road, Huangpu District, Guangzhou City, Guangdong Province Applicant after: GUANGZHOU ANHAI SEMICONDUCTOR CO.,LTD. Address before: Room 302, room 88, 7, Guiping Road, Xuhui District, Shanghai Applicant before: Zhang Shuai Applicant before: Huang Xin |
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Effective date of registration: 20191204 Address after: Floor 12, building a1-3, Hanyu Jingu, no.7000, jingshidong Road, Jinan area, China (Shandong) pilot Free Trade Zone, Jinan City, Shandong Province, 250102 Applicant after: Jinan Anhai Semiconductor Co.,Ltd. Address before: 510700 Room 303, building 1, No. 23, Jinzhong Road, Huangpu District, Guangzhou City, Guangdong Province Applicant before: GUANGZHOU ANHAI SEMICONDUCTOR CO.,LTD. |
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Application publication date: 20190215 |