CN109302194B - Mbus host receiving circuit - Google Patents
Mbus host receiving circuit Download PDFInfo
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- CN109302194B CN109302194B CN201811443843.3A CN201811443843A CN109302194B CN 109302194 B CN109302194 B CN 109302194B CN 201811443843 A CN201811443843 A CN 201811443843A CN 109302194 B CN109302194 B CN 109302194B
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- operational amplifier
- resistor
- input end
- power supply
- mbus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40228—Modbus
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
Abstract
The application discloses an Mbus host receiving circuit, which comprises a sampling resistor, an operational amplifier and a comparator, wherein the sampling resistor is connected with the operational amplifier; one end of the sampling resistor is connected with the input end, and the other end of the sampling resistor is grounded; the driving power supply of the operational amplifier is 7.5-9.6V, and the driving power supply amplifies the signal of the input end by 3-4 times and outputs the signal; the driving power supply of the comparator is the same as the driving power supply of the operational amplifier; the positive input end of the comparator is connected with the output end of the operational amplifier after the resistor I, the negative input end of the comparator is connected with the output end of the operational amplifier after the resistor II, and the output end of the comparator is connected with the signal receiving end of the singlechip. According to the Mbus host receiving circuit, the single-channel load capacity is improved from 100mA to 200mA to 1600mA to 1700mA in the prior art, and a single channel can drive a larger number of acquisition substations, so that the use requirement in the current market is satisfied; and the load capacity is improved, and meanwhile, zero-distortion transmission data can be transmitted to the receiving port of the singlechip.
Description
Technical Field
The application relates to the technical field of instrument bus Mbus, in particular to an Mbus host receiving circuit with large load capacity.
Background
The meter bus (MeterBus Mbus) is a master-slave configuration field bus, and the Mbus is mainly characterized by using two nonpolar transmission lines to simultaneously supply power and transmit serial data, and each substation (confirmed with different IDs and unique identification ID) is connected in parallel to the Mbus bus. When Mbus is used in the energy consumption intelligent management system of various meters or related devices, related data or signals can be collected and transmitted to the concentrator and then transmitted to the master station through the corresponding interface. The wiring and connection of the intelligent energy consumption management system of residential communities, offices and the like can be greatly simplified by utilizing Mbus, and the intelligent energy consumption management system has the characteristics of simple structure, low manufacturing cost and high reliability; the energy consumption intelligent management system consists of terminal data or signal acquisition substation, an Mbus transceiver circuit, an Mbus bus, a master station, an Mbus converter and the like.
The Mbus host receiving circuit is used for receiving the data of each acquisition substation and transmitting the data to the signal receiving end of the singlechip. At present, the load of the receiving circuit of most of the existing Mbus hosts can only reach 100 mA-200 mA (namely, the carrying capacity is 100 mA-200 mA), and very few manufacturers can reach 300 mA. However, the number of meters in the centralized meter reading site is often very large, in order to meet the load capacity in practical application requirements, in the prior art, a plurality of Mbus channels are added on each host, and a plurality of Mbus collector hosts are installed in each cell. Multiple Mbus channels require multiple Mbus buses to be wired in parallel, so that the workload of wiring is increased; on the other hand, installing multiple sets of Mbus collector hosts can add significant cost.
Disclosure of Invention
The technical problem to be solved by the application is to provide an Mbus host receiving circuit, wherein the single-path load capacity of the receiving circuit is improved from 100 mA-200 mA to 1600 mA-1700 mA in the prior art, and the single-path can drive more acquisition substations, so that the receiving circuit is enough to meet the use requirements in the current market.
In order to solve the technical problems, the application provides an Mbus host receiving circuit, which comprises a sampling resistor R, an operational amplifier U1 and a comparator U2;
one end of the sampling resistor R is connected with the input end Mbus, and the other end of the sampling resistor R is grounded;
the driving power supply of the operational amplifier U1 is 7.5-9.6V, and the driving power supply amplifies signals of Mbus at the input end by 3-4 times and outputs the signals;
the driving power supply of the comparator U2 is the same as that of the operational amplifier U1;
the forward input end of the comparator U2 is connected with the first resistor R1 and then is connected with the output end of the operational amplifier U1, the reverse input end of the comparator U2 is connected with the second resistor R2 and then is connected with the output end of the operational amplifier U1, and the output end of the comparator U2 is connected with the receiving port RXD of the singlechip.
In a preferred embodiment of the present application, the present application further includes a filter circuit, where the filter circuit includes a capacitor one C1, a capacitor two C2, a resistor three R3 and a resistor four R4; the capacitor C1 and the resistor tri-R3 are connected in series between a driving power supply of the operational amplifier U1 and the ground, and a node A between the capacitor C1 and the resistor tri-R3 is connected with the reverse input end of the comparator U2; the second capacitor C2 and the fourth resistor R4 are connected in series between the driving power supply of the operational amplifier U1 and the ground, and the node B between the second capacitor C2 and the fourth resistor R4 is connected with the positive input end of the comparator U2; the resistance of the resistor three R3 is smaller than that of the resistor four R4, and the capacitance of the capacitor one C1 is smaller than that of the capacitor two C2.
In a preferred embodiment of the present application, the positive input terminal of the operational amplifier U1 is connected to the input terminal Mbus, the negative input terminal thereof is connected to the output terminal thereof after being connected to the resistor five R5, and the negative input terminal thereof is connected to the ground after being connected to the resistor six R6.
In a preferred embodiment of the present application, the positive input terminal of the operational amplifier U1 is further connected to a resistor seven R7 and then connected to a driving power supply of the operational amplifier U1.
In a preferred embodiment of the present application, the circuit further includes a diode D1, wherein the anode of the diode D1 is connected to the resistor a and the resistor b, and the cathode of the diode D1 is connected to the output terminal of the operational amplifier U1.
In a preferred embodiment of the present application, the present application further includes an isolation optocoupler GD, wherein an output end of the isolation optocoupler GD is connected to a receiving port RXD of the singlechip, an input end of the isolation optocoupler GD is connected to an output end of the comparator U2, and a driving end of the isolation optocoupler GD is connected to a driving power supply of the operational amplifier U1.
In a preferred embodiment of the present application, the driving power of the operational amplifier U1 is 9.0V, which amplifies the signal of Mbus at the input terminal by 3.7 times and outputs the amplified signal.
In a preferred embodiment of the present application, the present application further includes a clamping diode D3, where an anode of the clamping diode D3 is connected to the positive input terminal of the operational amplifier U1, and a cathode of the clamping diode D is connected to the driving power supply of the operational amplifier U1.
In a preferred embodiment of the present application, the present application further includes a filter capacitor C3, where one end of the filter capacitor C3 is connected to the positive input end of the operational amplifier U1, and the other end is grounded.
The application has the beneficial effects that:
compared with the Mbus receiving circuit in the prior art, the single-channel load capacity of the Mbus host receiving circuit is improved by 8-10 times, and a single channel can drive a plurality of acquisition substations, so that the use requirement in the current market is satisfied.
In the prior art, the single-path load capacity of the Mbus receiving circuit is 100 mA-200 mA.
The application relates to an Mbus host receiving circuit, which is characterized in that an output signal of a collecting substation is sampled by a sampling resistor and then enters an operational amplifier to amplify for 3-4 times and then is output, the output signal of the operational amplifier is isolated by a resistor I and a resistor II to obtain two paths of alternating current signals, the two paths of alternating current signals enter a comparator, the comparator shapes the input signals into digital square wave signals and inputs the digital square wave signals to a receiving port of a singlechip, a driving power supply of the operational amplifier is controlled to be 7.5-9.6V, and the amplification factor of the operational amplifier is controlled, so that the single-path load capacity of the Mbus host receiving circuit is improved to 1600 mA-1700 mA; meanwhile, the load capacity is improved, and meanwhile, zero-distortion data can be transmitted to the receiving port of the singlechip.
Drawings
Fig. 1 is a circuit schematic of an Mbus host receiving circuit in a preferred embodiment of the application.
Detailed Description
The present application will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the application and practice it.
Examples
As shown in fig. 1, the embodiment discloses an Mbus host receiving circuit, which includes a sampling resistor R, an operational amplifier U1, a comparator U2, an isolation optocoupler GD, a diode D1, a clamping diode D3, and a filter capacitor C3.
One end of the sampling resistor R is connected with the input end Mbus, and the other end of the sampling resistor R is grounded;
the operational amplifierThe positive input end of the amplifier U1 is connected with the input end Mbus, the negative input end of the amplifier U1 is connected with the output end of the amplifier after being connected with the resistor five R5, the negative input end of the amplifier U1 is also connected with the resistor six R6 and then grounded, and the amplification factor of the operational amplifier U1 is as follows
The output end of the operational amplifier U1 is connected with the cathode of the diode D1, the positive input end of the comparator U2 is connected with the resistor R1 and then is connected with the anode of the diode D1, the reverse input end of the comparator U2 is connected with the resistor R2 and then is connected with the anode of the diode D1, the output end of the comparator U1 is connected with the input end of the isolation optocoupler GD, and the output end of the isolation optocoupler GD is connected with the receiving port RXD of the singlechip. The driving end of the isolation optocoupler GD is connected to the driving power supply of the operational amplifier U1, and the driving power supply of the comparator U2 is the same as the driving power supply of the operational amplifier U1.
The design of the diode D1 ensures that the voltage value of the input end of the comparator U2 is always higher than that of the operational amplifier U1, otherwise, the receiving circuit is disconnected.
Above, the output signal of gathering substation inserts input Mbus, and the signal is after sampling by sampling resistor R gets into operational amplifier and amplifies the output, and operational amplifier's output signal isolates two way alternating current signal through resistance one R1 and resistance two R2 and gets into comparator U2, and comparator U2 is the digital square wave signal with the input signal shaping, and the receiving port of singlechip is input to after isolating opto-coupler GD isolation to the digital square wave signal, realizes Mbus receiving circuit and singlechip's communication, will gather the output signal of substation to the singlechip.
In the technical scheme of the embodiment, the amplification factor of the operational amplifier U1 is 3-4 by matching the resistance values of the resistor five R5 and the resistor six R6. In order to meet the requirement of improving the load capacity and zero-distortion transmission data, in the preferred technical scheme of the embodiment, the amplification factor of the operational amplifier U1 is preferably 3.7 times. Meanwhile, the driving power supply of the operational amplifier U1 is controlled to be 7.5-9.6V. In the technical scheme of the embodiment, the optimal model of the operational amplifier U1 is LM358, and the attribute of the LM358 determines the maximum output voltage V max The method comprises the following steps: v (V) max =vcc-1.5. In the preferred technical solution of this embodiment, in order to meet the requirement of lifting the load capacity and zero-distortion data transmission, the driving power supply of the operational amplifier U1 is controlled to be 9V so that the maximum output voltage V thereof max 7.5V.
Above, the maximum load capacity of the receiving circuit of the Mbus host of the present application is:the optimal matching resistance of the sampling resistor R is 1.2 Ω, so as to determine that in the preferred technical scheme of this embodiment, the maximum load capacity of the receiving circuit of the Mbus host is +.>
In the above, only one embodiment of the present application is shown, and in other embodiments, any one of the amplification factor of the operational amplifier U1, the driving power supply size of the operational amplifier U1, and the resistance value of the sampling resistor R may be changed to adjust the load carrying capacity of the Mbus host receiving circuit to 1600mA to 1700mA.
In addition, according to the requirements of Mbus hardware specifications, the dynamic current of a sending logic 0 of Mbus substation equipment is 0mA, the dynamic current of a sending logic 1 is between 10mA and 20mA, the static current consumed by each Mbus substation equipment on an Mbus bus is about 1mA (the static currents of equipment of all factories are different), according to the receiving circuit designed above, the voltage drop of the dynamic current on a sampling resistor R is between 0V and (12 mV and 24 mV), the output voltage is between 0V and (44.4 mV and 88.8 mV) after the dynamic current is amplified by an operational amplifier U1, the voltage change is enough for a comparator U2 to perform error-free identification, so that a correct square wave signal is generated, the communication between the receiving circuit and a singlechip is completed, and the output signal of a collecting substation (or the Mbus substation equipment) is transmitted to the singlechip.
As a further improvement of the present application, the receiving circuit further includes a filter circuit, where the filter circuit includes a capacitor one C1, a capacitor two C2, a resistor three R3 and a resistor four R4; the capacitor C1 and the resistor tri-R3 are connected in series between the driving power supply of the operational amplifier U1 and the ground, and the node A between the capacitor C1 and the resistor tri-R3 is connected with the reverse input end of the comparator U2; the second capacitor C2 and the fourth resistor R4 are connected in series between the driving power supply of the operational amplifier U1 and the ground, and the node B between the second capacitor C2 and the fourth resistor R4 is connected with the positive input end of the comparator U2; the resistance of the resistor three R3 is smaller than that of the resistor four R4, and the capacitance of the capacitor one C1 is smaller than that of the capacitor two C2. After the signal is amplified by the operational amplifier U1, two paths of signals are isolated by the resistor I and the resistor II, wherein one path of signal filters an alternating current component through a large capacitor (a capacitor II C2) and a large resistor (a resistor IV R4) to become a smooth direct current signal; the high-level interference signals are filtered by one path of signals through a small capacitor (capacitor C1) and a small resistor (resistor three R3), the wave path of signals are input into a comparator U2 for comparison, direct current components are thoroughly removed, only alternating current signals are left, and the comparator U2 shapes the alternating current signals into digital square wave signals, so that the interference signals on a signal transmission link are reduced, and zero distortion of signal transmission is ensured.
In the practical use process of the receiving circuit, the load of the back end belt is possibly more or less, and the number of the load required by the receiving circuit in the prior art can be estimated in advance, so that the receiving circuit is designed independently corresponding to the loads in different number ranges. In order to overcome this technical problem, the host receiving circuit of the present application designs a resistor seven R7, and the positive input terminal of the operational amplifier U1 is connected to the resistor seven R7 and then to the driving power supply of the operational amplifier U1. The voltage value of the forward input end of the operational amplifier U1 is pulled through the resistor seven R7, so that the receiving circuit can work normally in the range of load capacity regardless of a plurality of loads.
The positive electrode of the clamping diode D3 is connected with the positive input end of the operational amplifier U1, and the negative electrode of the clamping diode D is connected with the driving power supply of the operational amplifier U1; one end of the filter capacitor C3 is connected with the positive input end of the operational amplifier U1, and the other end of the filter capacitor C is grounded. The clamp diode D3 clamps the voltage at the positive input terminal of the operational amplifier U1, and the filter capacitor C3 filters the signal entering the receiving circuit.
The above-described embodiments are merely preferred embodiments for fully explaining the present application, and the scope of the present application is not limited thereto. Equivalent substitutions and modifications will occur to those skilled in the art based on the present application, and are intended to be within the scope of the present application. The protection scope of the application is subject to the claims.
Claims (8)
1. An Mbus host receiving circuit, characterized in that: the circuit comprises a sampling resistor (R), an operational amplifier (U1) and a comparator (U2);
one end of the sampling resistor (R) is connected with an input end (Mbus), and the other end of the sampling resistor (R) is grounded;
the driving power supply of the operational amplifier (U1) is 7.5-9.6V, and the driving power supply amplifies a signal (Mbus) at the input end by 3-4 times and outputs the amplified signal;
the driving power supply of the comparator (U2) is the same as the driving power supply of the operational amplifier (U1);
the forward input end of the comparator (U2) is connected with the output end of the operational amplifier (U1) after being connected with the resistor I (R1), the reverse input end of the comparator is connected with the output end of the operational amplifier (U1) after being connected with the resistor II (R2), and the output end of the comparator is connected with the signal receiving end (RXD) of the singlechip;
the filter circuit comprises a first capacitor (C1), a second capacitor (C2), a third resistor (R3) and a fourth resistor (R4); the capacitor I (C1) and the resistor III (R3) are connected in series between a driving power supply of the operational amplifier (U1) and the ground, and a node A between the capacitor I (C1) and the resistor III (R3) is connected with the reverse input end of the comparator (U2); the second capacitor (C2) and the fourth resistor (R4) are connected in series between a driving power supply of the operational amplifier (U1) and the ground, and a node B between the second capacitor (C2) and the fourth resistor (R4) is connected with a positive input end of the comparator (U2); the resistance of the resistor three (R3) is smaller than that of the resistor four (R4), and the capacitance of the capacitor one (C1) is smaller than that of the capacitor two (C2).
2. The Mbus host receiving circuit of claim 1, wherein: the positive input end of the operational amplifier (U1) is connected with the input end (Mbus), the negative input end of the operational amplifier is connected with the output end of the operational amplifier after being connected with the resistor five (R5), and the negative input end of the operational amplifier is also connected with the resistor six (R6) and then grounded.
3. The Mbus host receiving circuit of claim 2, wherein: the positive input end of the operational amplifier (U1) is also connected with a resistor seven (R7) and then connected to a driving power supply of the operational amplifier (U1).
4. The Mbus host receiving circuit of claim 1, wherein: the circuit also comprises a diode I (D1), wherein the anode of the diode I (D1) is connected with a resistor I and a resistor II, and the cathode of the diode I is connected with the output end of the operational amplifier (U1).
5. The Mbus host receiving circuit of claim 1, wherein: the device further comprises an isolation optocoupler (GD), wherein the output end of the isolation optocoupler (GD) is connected with a signal receiving end (RXD) of the singlechip, the input end of the isolation optocoupler is connected with the output end of the comparator (U2), and the driving end of the isolation optocoupler is connected with a driving power supply of the operational amplifier (U1).
6. The Mbus host receiving circuit of claim 1, wherein: the driving power supply of the operational amplifier (U1) is 9.0V, and the driving power supply amplifies the signal (Mbus) of the input end by 3.7 times and outputs the amplified signal.
7. The Mbus host receiving circuit of claim 1, wherein: the power supply circuit further comprises a clamping diode (D3), wherein the positive electrode of the clamping diode (D3) is connected with the positive input end of the operational amplifier (U1), and the negative electrode of the clamping diode is connected with the driving power supply of the operational amplifier (U1).
8. The Mbus host receiving circuit of claim 7, wherein: the filter circuit further comprises a filter capacitor (C3), one end of the filter capacitor (C3) is connected with the positive input end of the operational amplifier (U1), and the other end of the filter capacitor is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811443843.3A CN109302194B (en) | 2018-11-29 | 2018-11-29 | Mbus host receiving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811443843.3A CN109302194B (en) | 2018-11-29 | 2018-11-29 | Mbus host receiving circuit |
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| CN109302194A CN109302194A (en) | 2019-02-01 |
| CN109302194B true CN109302194B (en) | 2023-10-20 |
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| CN201811443843.3A Active CN109302194B (en) | 2018-11-29 | 2018-11-29 | Mbus host receiving circuit |
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| CN112333070B (en) * | 2020-11-06 | 2022-03-15 | 江阴市立信智能设备有限公司 | Implementation method of MBUS master station in MBUS gateway |
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| CN109302194A (en) | 2019-02-01 |
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