CN109300972A - FINFET device and forming method thereof - Google Patents
FINFET device and forming method thereof Download PDFInfo
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- CN109300972A CN109300972A CN201710606730.XA CN201710606730A CN109300972A CN 109300972 A CN109300972 A CN 109300972A CN 201710606730 A CN201710606730 A CN 201710606730A CN 109300972 A CN109300972 A CN 109300972A
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- 239000010410 layer Substances 0.000 claims description 174
- 239000000463 material Substances 0.000 claims description 50
- 239000011229 interlayer Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 11
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 description 27
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- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 230000009969 flowable effect Effects 0.000 description 4
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical group F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A kind of FINFET device and forming method thereof, the device is formed with the first groove and the second groove in the upper surface of isolation structure, first groove, the second groove are distributed in the two sides of gate structure along the extending direction of fin, external wall is covered on the side wall of gate structure, portion outboard wall extends to the side surface of the first groove and the side surface of the second groove along the thickness direction of semiconductor substrate.So, the bottom end that the grid in gate structure is located at the part on isolation structure is limited within external wall, without extend on two neighboring fin source, between drain electrode, because of the problem of being shorted without source, drain electrode and grid.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of FINFET device and forming method thereof.
Background technique
With the continuous diminution of cmos device size, the challenge from manufacture and design aspect has promoted three dimensional design such as fin
The development of gate fin-fet (FINFET).Relative to existing planar transistor, FINFET is for 20nm and following technique
The advanced semiconductor device of node, can effectively control device it is scaled caused by be difficult to the short channel overcome effect
It answers, the density of transistor array formed on a substrate can also be effectively improved, meanwhile, the grid of FINFET is set around fin
It sets, therefore electrostatic can be controlled from three faces, thus with the performance in terms of Electrostatic Control more outstanding.
Fig. 1 is a kind of projection view of the existing FINFET device along fin height direction (i.e. X-direction in Fig. 2), and Fig. 2 is
The sectional view of FINFET device shown in Fig. 1, wherein Fig. 2 a is sectional view of the Fig. 1 along the direction AA, and Fig. 2 b is Fig. 1 along the direction BB
Sectional view, Fig. 2 c are sectional view of the Fig. 1 along the direction CC.In conjunction with shown in Fig. 1 to Fig. 2, a kind of existing FINFET device includes partly leading
Body substrate 1, has several spaced fins 10 positioned at surface, be isolated between two neighboring fin 10 structure 2 every
It opens, the upper surface S1 of isolation structure 2 is lower than the upper surface S2 of fin 10.Gate structure 3 across fin 10 and isolation structure 2, and
Grid 31 including gate dielectric layer 30 and on gate dielectric layer 30.Two sides in fin 10 positioned at gate structure 3 are respectively equipped with
Source electrode 4 and drain electrode 5.Interlayer dielectric layer 6 covers fin 10, isolation structure 2, source electrode 4 and drain electrode 5, and surrounds gate structure 3.It needs
Illustrate, in order to show fin in Fig. 1, interlayer dielectric layer is not shown in Fig. 1.
However, finding through detection, usually there is the portion that grid 31 is located on isolation structure 2 in above-mentioned existing FINFET device
The problem of bottom end divided and source electrode 4, drain electrode 5 are shorted.
Summary of the invention
The technical problem to be solved in the present invention: usually there is the portion that grid is located on isolation structure in existing FINFET device
The problem of bottom end divided and source electrode, drain electrode are shorted.
To solve the above-mentioned problems, An embodiment provides a kind of FINFET devices comprising: semiconductor
Substrate has several spaced fins positioned at surface, and the two neighboring fin is isolated structure and separates, the isolation
The upper surface of structure is lower than the upper surface of the fin；Across the gate structure of the fin and isolation structure, the grid knot
Structure includes gate dielectric layer and the grid on the gate dielectric layer；First groove of the upper surface of the isolation structure is set
With the second groove, first groove, the second groove are distributed in the two sides of the gate structure along the extending direction of the fin；
The external wall being covered on the gate structure sidewall, the part external wall extend along the thickness direction of the semiconductor substrate
To the side surface of first groove and the side surface of the second groove；Source electrode and drain electrode in the fin, the source electrode,
Drain electrode is distributed in the two sides of the gate structure.
Optionally, the material of the external wall is silicon nitride.
Optionally, the external wall along the thickness direction of the semiconductor substrate extend to first groove bottom wall,
The bottom wall of second groove.
Optionally, the source electrode, drain electrode include the groove being arranged in the fin and the epitaxial layer for filling the groove.
Optionally, the groove is sigma type.
Optionally, the semiconductor substrate include be used to form core devices core device region and be used to form input it is defeated
The input and output device area of device out；
The core devices include the fin, the isolation structure, the gate structure, first groove, described
Second groove, the external wall, the source electrode and the drain electrode；
The input and output device includes the fin, the isolation structure, the gate structure, the external wall, institute
State source electrode and the drain electrode.
Optionally, the material of the isolation structure is the silica formed using FCVD technique.
Optionally, the gate dielectric layer is high-K gate dielectric layer, and the grid is metal gates.
Optionally, the semiconductor substrate is body silicon substrate, and the lower end of the fin is surrounded by the isolation structure.
In addition, the present invention also provides a kind of forming methods of FINFET device comprising:
There is provided semiconductor substrate, the semiconductor substrate have positioned at surface several spaced fins, adjacent two
A fin is isolated structure and separates, and the upper surface of the isolation structure is lower than the upper surface of the fin；It is developed across institute
The gate structure of fin and isolation structure is stated, the gate structure includes gate dielectric layer and the grid on the gate dielectric layer
Pole；The first groove and the second groove are formed in the upper surface of the isolation structure, first groove, the second groove are along the fin
The extending direction of piece is distributed in the quasi- region two sides for forming the gate structure；It is formed around the region of the gate structure quasi-
External wall is formed, the part external wall extends to the side surface of first groove along the thickness direction of the semiconductor substrate
With the side surface of the second groove；The source electrode and drain electrode being located in the fin is formed, the source electrode, drain electrode, which are distributed in, to be intended forming institute
State the region two sides of gate structure.
Optionally, the forming method of the gate structure includes:
Before forming first groove and the second groove, pseudo- grid knot is formed in the quasi- region for forming the gate structure
Structure, dummy gate structure include pseudo- gate dielectric layer and the dummy grid on the pseudo- gate dielectric layer, and the puppet gate dielectric layer is extremely
The fin is covered less, and the dummy grid covers the fin and isolation structure；
It is formed after first groove and the second groove, forms the external wall in the side wall of dummy gate structure；
It is formed after the external wall, the source electrode, the leakage is respectively formed in the fin of dummy gate structure two sides
Pole；
It is formed after the source electrode and drain electrode, is formed and cover the fin, isolation structure, the first groove, the second groove, source
Pole and drain electrode, and the interlayer dielectric layer of dummy gate structure is surrounded, the upper surface of the interlayer dielectric layer and the dummy grid
Upper surface flushes；
Dummy gate structure is removed, to form gate trench in the interlayer dielectric layer；
The gate structure is formed in the gate trench.
Optionally, the material of the pseudo- gate dielectric layer is thermal oxidation silicon.
Optionally, the material of the isolation structure is the silica formed using FCVD technique.
Optionally, the material of the external wall is silicon nitride.
Optionally, the external wall along the thickness direction of the semiconductor substrate extend to first groove bottom wall,
The bottom wall of second groove.
Optionally, the source electrode, drain electrode include the groove being arranged in the fin and the epitaxial layer for filling the groove.
Optionally, the groove is sigma type.
Optionally, the semiconductor substrate include be used to form core devices core device region and be used to form input it is defeated
The input and output device area of device out；
The core devices include the fin, the isolation structure, the gate structure, first groove, described
Second groove, the external wall, the source electrode and the drain electrode；
The input and output device includes the fin, the isolation structure, the gate structure, the source electrode and institute
State drain electrode.
Optionally, the gate dielectric layer is high-K gate dielectric layer, and the grid is metal gates.
Optionally, the semiconductor substrate is body silicon substrate, and the lower end of the fin is surrounded by the isolation structure.
In the inventive solutions, the upper surface of the isolation structure is formed with the first groove and the second groove, institute
State the first groove, the second groove is distributed in the two sides of gate structure along the extending direction of the fin, on the side wall of gate structure
It is covered with external wall, the part external wall extends to the side table of first groove along the thickness direction of the semiconductor substrate
The side surface in face and the second groove.So, the grid in gate structure is located at the bottom end quilt of the part on isolation structure
Be limited within external wall, without extend on two neighboring fin source, between drain electrode, because without source, drain electrode
The problem of being shorted with grid.
When gate structure is using the formation of rear grid technique, when removing the pseudo- gate dielectric layer in pseudo- grid structure, even if isolation
The upper surface that structure is exposed to the gate trench is formed with over etching slot, and external wall can also prevent isolation structure to be exposed to grid
Upper surface in the groove of pole is in the direction of extension by overetch, so that over etching slot is limited within external wall, such one
To come, the bottom end that the grid in gate trench is located at the part on isolation structure can also be limited within external wall, without
The source on two neighboring fin is extended to, between drain electrode, because of the problem of being shorted without source, drain electrode and grid.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention, side
Face and its advantage will become apparent.
Detailed description of the invention
Attached drawing forms part of this specification, and which depict exemplary embodiment of the present invention, and together with specification
Principle for explaining the present invention together, in the accompanying drawings:
Fig. 1 is a kind of projection view of the existing FINFET device along fin height direction, does not illustrate interlayer dielectric layer in figure；
Fig. 2 is the sectional view of FINFET device shown in Fig. 1, wherein Fig. 2 a is sectional view of the Fig. 1 along the direction AA, and Fig. 2 b is
For Fig. 1 along the sectional view in the direction BB, Fig. 2 c is sectional view of the Fig. 1 along the direction CC；
Fig. 3 is the production flow diagram of FINFET device in one embodiment of the present of invention；
Fig. 4 be in one embodiment of the present of invention FINFET device along the projection view in fin height direction；
Fig. 5 to Figure 17 is diagrammatic cross-section of the FINFET device in each production phase in one embodiment of the present of invention,
Wherein, Fig. 5 a to Figure 17 a is sectional view of the device shown in Fig. 4 in each production phase along the direction AA, and Fig. 5 b to Figure 17 b is Fig. 4
For shown device in each production phase along the sectional view in the direction BB, Fig. 5 c to Figure 17 c is device shown in Fig. 4 in each production phase
Sectional view along the direction CC.
Specific embodiment
As previously mentioned, usually there is the bottom end and source for the part that grid is located on isolation structure in existing FINFET device
The problem of pole, drain electrode are shorted.It has been investigated that the reason of causing the above problem are as follows:
It continues to refer to figure 1 to shown in Fig. 2, FINFET is formed using rear grid technique (gate last).That is, first in semiconductor
The position for intending being formed gate structure 3 on substrate 1 forms pseudo- grid structure, and dummy gate structure includes the pseudo- grid on fin 10
Dielectric layer and the dummy grid on pseudo- gate dielectric layer and isolation structure 2, the dummy grid is across fin 10 and adjacent two fin
Isolation structure 2 between piece 10；Then, the two sides that pseudo- grid structure is located in fin 10 are respectively formed source electrode 4 and drain electrode 5；It connects
, covering fin 10, isolation structure 2, source electrode 4 and drain electrode 5 are formed, and surround the interlayer dielectric layer 6 of dummy gate structure, then
Dummy gate structure is removed, to form gate trench G in interlayer dielectric layer 6；Finally, forming grid in the gate trench G
Dielectric layer 30 and the grid 31 on gate dielectric layer 30.
After removing the dummy grid, when then removing the pseudo- gate dielectric layer on fin 10, isolation structure 2 is exposed to
Upper surface in gate trench G is exposed in etching environment.Since the material of isolation structure 2 is to utilize FCVD (Flowable
Chemical Vapor Deposition, mobility chemical vapor deposition) technique formed silica, quality is more loose,
So that the upper surface that isolation structure 2 is exposed to the gate trench G is easily etched, and formed in the upper surface of isolation structure 2
Etching groove 20, over etching slot 20 are connected to gate trench G, and protrude from gate trench G at the both ends of the extending direction Y of fin 10
(the over etching slot 20 and the T-shaped groove of gate trench G that are connected to).
So, the gate structure 3 in the gate trench G also extends to the over etching groove 20 on isolation structure 2
Interior, bottom end (enclosing region by dotted line in Fig. 1 in the both ends of the bottom end) edge that grid 31 is located at the part on isolation structure 2 is prolonged
Direction Y is stretched to project between the both ends of adjacent two fin 10.And the source electrode 4, drain electrode 5 on fin 10 are intended on fin 10 using first
Formed source electrode 4, drain 5 position formed groove the method for epitaxial layer is formed in groove again, when growing the epitaxial layer, this is outer
Prolong layer often to outgrowth, so that the epitaxial layer of source electrode 4, drain electrode 5 exceeds except the groove, and is located at isolation junction with grid 31
The bottom end of part on structure 2 is shorted.
In order to solve this problem, the invention proposes a kind of improved plans, are formed in the upper surface of isolation structure
First groove and the second groove, first groove, the second groove are distributed in gate structure along the extending direction of the fin
Two sides are covered with external wall on the side wall of gate structure, and the part external wall prolongs along the thickness direction of the semiconductor substrate
Extend to the side surface of first groove and the side surface of the second groove.So, the grid in gate structure is located at isolation
The bottom end of part on structure is limited within external wall, without extend on two neighboring fin source, drain it
Between, because of the problem of being shorted without source, drain electrode and grid.
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For limitation of the scope of the invention.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the present invention and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
The forming method of FINFET device
Fig. 3 is the production flow diagram of FINFET device in one embodiment of the present of invention, and Fig. 4 is an implementation of the invention
For FINFET device along the projection view in fin height direction, Fig. 5 to Figure 17 is FINFET in one embodiment of the present of invention in example
Diagrammatic cross-section of the device in each production phase, wherein Fig. 5 a to Figure 17 a is device shown in Fig. 4 on each production phase edge
The sectional view in the direction AA, Fig. 5 b to Figure 17 b are sectional view of the device shown in Fig. 4 in each production phase along the direction BB, and Fig. 5 c is extremely
Figure 17 c is sectional view of the device shown in Fig. 4 in each production phase along the direction CC.It is provided by the present invention in order to clear explanation
Important feature in FINFET device, Fig. 4 do not show interlayer dielectric layer.Below with reference to Fig. 3 to Figure 17 to the present embodiment
The production method of FINFET device is described in detail.
Firstly, executing the step S1 in Fig. 3 with reference to Fig. 4 and Fig. 5, semiconductor substrate 1 is provided, semiconductor substrate 1 has position
Several spaced fins 10 in surface, two neighboring fin 10 are isolated structure 11 and separate, the upper table of isolation structure 11
Face S1 is lower than the upper surface S2 of fin 10.
In the present embodiment, semiconductor substrate 1 be body silicon substrate, material can for monocrystalline substrate, multicrystalline silicon substrate,
Amorphous silicon substrate, germanium silicon substrate, carbon silicon substrate etc..It, can be in the table of the body silicon substrate by being performed etching to the body silicon substrate
Face forms several spaced fins 10.
In the present embodiment, the forming method of isolation structure 11 includes: to be formed after fin 10, on semiconductor substrate 1
Insulation material layer is formed, the surface of the insulation material layer is higher than the upper surface S2 of fin 10；Then, which is carried out
Planarization process, to remove the part that the insulation material layer is higher than fin 10；Then, which is performed etching, is made
It obtains fin 10 and protrudes from the insulation material layer, to form isolation structure 11.
Further, in the present embodiment, the material of isolation structure 11 is to utilize FCVD (Flowable Chemical
Vapor Deposition, mobility chemical vapor deposition) silica that is formed of technique, why using FCVD technique be because
It can form the higher isolation structure 11 of quality, will not generate gap.Certainly, in other embodiments, isolation structure 11 can also
To be formed using traditional chemical vapor deposition process, atom layer deposition process etc..
It should be noted that in the alternative of the present embodiment, semiconductor substrate 1 or silicon-on-insulator substrate
(SOI) comprising silicon base, insulating layer, the top layer silicon stacked gradually, if by the way that the top layer silicon is patterned and can be formed
Spaced fin 10 is done, the insulating layer is as the isolation structure 11 that two neighboring fin 10 is isolated.
Further, in the present embodiment, semiconductor substrate 1 includes the input and output device for being used to form input and output device
Part area I (i.e. the area IO) and the core device region II (i.e. the area Core) for being used to form core devices, wherein the core devices are used for
Realize the main function of integrated circuit, the input and output device is used to provide corresponding input signal for core devices or will
The corresponding signal of core devices exports.It is to disconnect signal in Fig. 4, between input and output device area I and core device region II.
In the present embodiment, input and output device area I and core device region II are each formed with FINFET, and input and output device
The FINFET in part area I and the FINFET of core device region II synchronize formed.For the sake of summary, in following each step, remove
It non-specifically points out, otherwise each step is both implemented in input and output device area I, also implements in core device region II.With following steps
For rapid S2, the pseudo- grid structure of formation, which refers to, on a semiconductor substrate implements shape in input and output device area I, core device region II
The step of at pseudo- grid structure.
Then, with reference to Fig. 4 and Fig. 6, the step S2 in Fig. 3 is executed, intends forming grid (Fig. 4 acceptance of the bid on semiconductor substrate 1
The position being denoted as 5) forms pseudo- grid structure 2, and specifically, pseudo- grid structure 2 is across fin 10 and isolation structure 11.In the figure with puppet
For isolation structure 11 of the grid structure 2 between two adjacent fins 10 and the two neighboring fin 10.In practical applications,
Pseudo- grid structure 2 can isolation structure 11 between three or more adjacent fins 10 and fin 10 simultaneously.
Pseudo- grid structure 2 includes pseudo- gate dielectric layer 20 and the dummy grid 21 on the pseudo- gate dielectric layer 20.Wherein, described
Pseudo- gate dielectric layer 20 at least covers fin 10, and the dummy grid 21 covers the isolation structure between fin 10 and adjacent two fin 10
11.Pseudo- grid structure 2 plays the role of as grid occupy-place, and at least dummy grid 21 can be removed in subsequent process steps.
In the present embodiment, pseudo- grid structure 2 further includes the hard mask layer 22 on dummy grid 21, and effect will be rear
It is described in detail in continuous step S9.The material of hard mask layer 22 can select silicon nitride, silicon oxynitride etc..
In the present embodiment, the material of pseudo- gate dielectric layer 20 is silica, and its method for using thermal oxide is formed, because
This, pseudo- gate dielectric layer 20 only covers fin 10, and does not cover isolation structure 11.Certainly, in other embodiments, pseudo- gate medium
Layer 20 can also be formed using other techniques, such as chemical vapor deposition, atomic layer deposition, in this case, pseudo- gate medium
Layer 20 can cover fin 10 and isolation structure 11 simultaneously.In addition, pseudo- gate dielectric layer 20 can also select other low-K materials or height
K material.
In the present embodiment, the material of dummy grid 21 is polysilicon, is removed easily in the subsequent process, and cost
It is low.
In the present embodiment, the forming method of pseudo- grid structure 2 includes: to form puppet on fin 10 using the method for thermal oxide
Gate dielectric layer 20；Form the pseudo- gate material layer for covering pseudo- gate dielectric layer 20 and isolation structure 11；The shape in the pseudo- gate material layer
At hardmask material and the graphical photoresist layer on the hardmask material；With the graphical photoresist layer
The hardmask material is performed etching for exposure mask, to be formed for defining the shape of pseudo- grid structure 2 and the hard exposure mask of position
Layer 22；Remove the graphical photoresist layer；It is that exposure mask performs etching the pseudo- gate material layer with hard mask layer 22, to be formed
Dummy grid 21.
Then, with continued reference to Fig. 4 and Fig. 6, the step S3 in Fig. 3 is executed, forms inside wall around pseudo- grid structure 2
23。
The effect of inside wall 23 includes: that can carry out ion implanting to be covered with the pseudo- grid structure 2 of inside wall 23 as exposure mask,
To form lightly-doped source drain region (not shown) in the fin 10 of pseudo- 2 two sides of grid structure, and the lightly-doped source drain region is in fin 10
Extending direction (i.e. the horizontal direction of Fig. 6 a and Fig. 6 b) on will not be excessively close apart from pseudo- grid structure 2.
Inside wall 23 can be single layer side wall or multilayer side wall, and inside wall 23 is by taking single layer side wall as an example in the figure.Inside wall
23 material can be silica, silicon nitride, silicon oxynitride etc..
In the present embodiment, the forming method of inside wall 23 include: to be formed covering isolation structure 11, pseudo- gate dielectric layer 20,
The inside wall material layer of the side wall of dummy grid 21, the side wall of hard mask layer 22 and roof；The inside wall material layer carve,
To form inside wall 23.
Then, with reference to Fig. 7, the step S4 in Fig. 3 is executed, forms the sacrificial of covering inside wall 23 around pseudo- grid structure 2
Domestic animal side wall 24.
The effect for sacrificing side wall 24 will be described in detail in subsequent step S5, and it can be removed in the next steps.?
In the present embodiment, the material for sacrificing side wall 24 is amorphous carbon, is easy to remove, and to semiconductor substrate 1 in removal process
On formed structure damage it is smaller.
In the present embodiment, the forming method for sacrificing side wall 24 includes: to form covering isolation structure 11, pseudo- gate dielectric layer
20, inside wall 23, hard mask layer 22 roof sacrifice spacer material layer；The sacrifice spacer material layer carve, with shape
At sacrifice side wall 24.
Then, refering to what is shown in Fig. 8, execute Fig. 3 in step S5, remove exposed pseudo- gate dielectric layer 20, that is, remove not by
Sacrifice the pseudo- gate dielectric layer 20 that side wall 24, inside wall 23 and dummy grid 21 cover.
The effect for sacrificing side wall 24 includes: that the pseudo- gate dielectric layer 20 for sacrificing 24 lower section of side wall can be protected not to be removed, this
Sample one, after removing exposed pseudo- gate dielectric layer 20, the two sides of the pseudo- grid structure 2 in input and output device area I can have to the greatest extent
Pseudo- gate dielectric layer 20 more than possible remains.
Then, with reference to shown in Fig. 4 and Fig. 9, the step S6 in Fig. 3 is executed, forms the in the upper surface S1 of isolation structure 11
One groove 110 and the second groove 111, the first groove 110, the second groove 111 are distributed in pseudo- grid structure 2 along 10 extending direction of fin
The two sides of X.
In the present embodiment, the forming method of the first groove 110 and the second groove 111 is dry etching, technological parameter
The flow for including: He is 600SCCM~2000SCCM, NH3Flow be 200SCCM~500SCCM, NF3Flow 20SCCM~
200SCCM, pressure are 2Torr~10Torr, and the time is 20S~500S.Due to being covered with inner sidewall 23 around dummy grid 21
With sacrifice side wall 24, therefore can make the first groove 110 and the second groove 111 on the extending direction X of fin 10 further from puppet
Grid 21.
Then, with reference to Fig. 9 to Figure 10, the step S7 in Fig. 3 is executed, side wall 24 is sacrificed in removal.
In the present embodiment, the minimizing technology for sacrificing side wall 24 is dry etching, and technological parameter includes: N2Flow be
2000SCCM~8000SCCM, H2Flow be 500SCCM~3000SCCM, pressure be 300mtorr~1200mtorr, power
For 1200W~5000W.
Then, with reference to Fig. 4 and Figure 11, the step S8 in Fig. 3 is executed, is formed and is located at around pseudo- grid structure 2 and covers inside
The external wall 24 of wall 23, pseudo- grid structure 2 are covered on the external wall 24 on the part on isolation structure 11 along the first groove
110, the depth direction (i.e. the up and down direction of Figure 11 c) of the second groove 111, extends to the side surface and second of the first groove 110
The side surface of groove 111.
In the present embodiment, the external wall 25 on 110 side surface of the first groove extends to the bottom wall of the first groove 110, the
External wall 25 on two grooves, 111 side surface extends to the bottom wall of the second groove 111.
In the present embodiment, the forming method of external wall 25 includes: to form covering isolation structure 11, the first groove 110
Side surface and bottom wall, the side surface of the second groove 111 and bottom wall, pseudo- gate dielectric layer 20, inside wall 23, hard mask layer 22 roof
External wall material layer；The external wall material layer carve, to form external wall 25.
Then, with reference to Fig. 4, Figure 12 and Figure 13, the step S9 in Fig. 3 is executed, is divided in the fin 10 of pseudo- 2 two sides of grid structure
It Xing Cheng not source/drain 3.
In the present embodiment, the forming method of source/drain 3 includes: and as shown in figure 12, performs etching to fin 10, with
Groove 30 is respectively formed in the fin 10 of pseudo- 2 two sides of grid structure；As shown in figure 13, epitaxial layer is formed in the groove 30
31.When forming epitaxial layer 31 by way of epitaxial growth, because the top of dummy grid 21 is covered with hard mask layer 22, therefore can
Prevent dummy grid 21 from also will do it epitaxial growth at top.
Further, in the present embodiment, groove 30 is ∑ type (as sigma type), and the material of epitaxial layer 31 is SiGe,
To apply stress to the channel of FINFET to improve the carrier mobility of transistor.Further, epitaxial layer 31 exceeds
The upper surface of fin 10, so that source/drain 3 is the source/drain of lifting, to improve the performance of transistor.It should be noted that
In technical solution of the present invention, the construction of source/drain 3 should not be limited to given embodiment, can be according to FINFET device
The performance requirement of part makes corresponding adjustment, for example, groove 30 may be arranged as rectangle, the material of epitaxial layer 31 can also be
SiC。
Then, with reference to figures 13 to Figure 14, the step S10 in Fig. 3 is executed, forms covering fin 10, isolation structure 11, first
Groove 110, the second groove 111, source/drain 3, and around the layer for the pseudo- grid structure 2 for being covered with inside wall 23 and external wall 25
Between dielectric layer 4, the upper surface of interlayer dielectric layer 4 is flushed with the upper surface of dummy grid 21.
In the present embodiment, the forming method of interlayer dielectric layer 4 includes: to form covering fin 10, isolation structure 11, first
Groove 110, the second groove 111, source/drain 3, and around the layer for the pseudo- grid structure 2 for being covered with inside wall 23 and external wall 25
Between dielectric materials layer, the upper surfaces of the interlayer dielectric material layers is higher than the top of hard mask layer 22；Carry out planarization process until
The upper surface of dummy grid 21 is exposed, i.e., by after planarization process, hard mask layer 22 is removed, the interlayer dielectric material layers are super
The part of 21 upper surface of dummy grid is removed out, and remaining interlayer dielectric material layers constitute interlayer dielectric layer 4.
Then, with reference to figs. 14 to Figure 15, the step S11 in Fig. 3 is executed, dummy grid 21 is removed, in interlayer dielectric layer 4
Form gate trench G1.
During removing dummy grid 21, the fin 10 of the pseudo- protection of gate dielectric layer 20 lower section is injury-free.In this implementation
In example, the minimizing technology of dummy grid 21 is wet etching, and etching agent is hydrofluoric acid solution.
Then, with reference to Figure 15 to Figure 16, the step S12 in Fig. 3 is executed, removal core device region II is exposed to grid ditch
The pseudo- gate dielectric layer 20 of pseudo- gate dielectric layer 20 in slot G1, input and output device area I retains and directly as input and output device
The gate dielectric layer of the FINFET device in area I.
In the present embodiment, the method for the pseudo- gate dielectric layer 20 of core device region II being exposed in gate trench G1 is removed
For dry etching, technological parameter includes: that the flow of He is 600SCCM~2000SCCM, NH3Flow be 200SCCM~
500SCCM, NF3Flow 20SCCM~200SCCM, pressure be 2Torr~10Torr, the time be 20S~100S.
As shown in figure 16, when removing the pseudo- gate dielectric layer 20 of core device region II being exposed in gate trench G1, every
It is exposed in etching environment that the upper surface in gate trench G1 is exposed to from structure 11.Since the material of isolation structure 11 is to utilize
The silica that FCVD (Flowable Chemical Vapor Deposition, mobility chemical vapor deposition) technique is formed,
Its quality is more loose, so that the upper surface that isolation structure 11 is exposed to the gate trench G1 is easily etched, and in isolation junction
The upper surface of structure 11 forms over etching slot G2, and over etching slot G2 is connected to gate trench G1, and the two of 10 extending direction X of fin
Distal process is for gate trench G1 (the over etching slot G2 and the T-shaped groove of gate trench G1 that are connected to).But due to gate trench G1
Around be formed with external wall 25, the upper surface that external wall 25 can prevent isolation structure 11 to be exposed in gate trench G1 is being prolonged
It stretches by overetch on the X of direction, so that over etching slot G2 is limited within external wall 25.
In the present embodiment, the material of external wall 25 is silicon nitride, and elching resistant is good, removes core device region in etching
When the II pseudo- gate dielectric layer 20 being exposed in gate trench G1, over etching slot G2 is not easy across external wall 25.Certainly, external wall
25 can also select other materials, as long as the pseudo- gate medium being exposed in gate trench G1 in etching removal core device region II
When layer 20, etching selection ratio with higher between pseudo- gate dielectric layer 20 and external wall 25 can prevent over etching slot G2 from prolonging
It stretches on the X of direction through external wall 25.
Finally, executing the step S13, the gate trench G1 in core device region II in Fig. 3 with reference to Fig. 4, Figure 16 to Figure 17
Interior formation gate structure 5, gate structure 5 include gate dielectric layer 50 and the grid 51 on gate dielectric layer 50.In core device
While part area II forms grid 51, grid 51 is formed also in the gate trench G1 in input and output device area I.
Specifically, in the present embodiment, gate dielectric layer is first formed in the gate trench of core device region II, then formed
It covers interlayer dielectric layer 4 and fills the gate material layers of the gate trench G1 of core device region II and input and output device area I；It is right
The gate material layers are planarized, to remove extra gate material layers, and in the gate trench G1 of core device region II, defeated
Enter in the gate trench G1 in output device area I and is respectively formed grid 51.
It can be seen that in the technical scheme of this embodiment, the gate medium of core device region II and input and output device area I
Layer requires difference, is first unified in core device region II and input and output device area I and is respectively formed pseudo- gate dielectric layer, then removes core
The pseudo- gate dielectric layer of device region II, gate dielectric layer of the remaining puppet gate dielectric layer directly as input and output device, then shape again
At the gate dielectric layer of core devices.
In the present embodiment, gate dielectric layer 50 is high-k gate dielectric layer, and grid 51 is metal gates, II He of core device region
The FINFET in input and output device area I is metal gate transistor.
In conjunction with shown in Fig. 4 and Figure 17, as previously mentioned, the over etching slot G2 on isolation structure 11 be limited in external wall 25 it
It is interior, therefore, grid 51 is located at the bottom end (enclosing region by dotted line in Fig. 4 in the both ends of the bottom end) of the part on isolation structure 11
It is also limited within external wall 25, without between the source electrode 3 that extends on two neighboring fin 10 or between drain electrode 3, or
Person extends between the drain electrode 5 on two neighboring fin 10, because of the problem of being shorted without source-drain electrode 3 and grid 51.
In the alternative of the present embodiment, the external wall 25 on 110 side surface of the first groove can also be with the first groove 110
Bottom wall there are certain intervals, the external wall 25 on 111 side surface of the second groove can also exist with the bottom wall of the second groove 111
Certain intervals, as long as the bottom end of external wall 25 is not higher than over etching slot G2.In this case, it still can be realized grid
51 parts for being located on isolation structure 11 are limited within external wall 25, so that drain electrode 3 be avoided to ask with what grid 51 was shorted
Topic.
By the technical solution of above-mentioned the present embodiment it is found that the FINFET of the present embodiment uses rear grid technique (gate last)
It is formed.That is, the position for first intending being formed gate structure on semiconductor substrate 1 forms pseudo- grid structure, the pseudo- grid knot is then removed
Structure finally forms gate structure in the gate trench to form gate trench.
Certainly, in the inventive solutions, the gate structure of FINFET is can not use rear grid technique (gate
Last it) is formed, but directly forms gate structure in the quasi- region for forming gate structure.For example, formed gate dielectric material layer and
After the gate material layers on gate dielectric material layer, Patterned masking layer is formed in gate material layers, it is graphical with this
Mask layer is that mask performs etching gate material layers, gate dielectric material layer, to form the grid for including gate dielectric layer and grid
Structure, the gate dielectric layer in the gate structure can be low k gate dielectric layer, or high-k gate dielectric layer, the grid can
Think polysilicon or metal.
FINFET device
Fig. 4 is that for FINFET device along the projection view in fin height direction, Figure 17 is Fig. 4 in one embodiment of the present of invention
Diagrammatic cross-section, wherein Figure 17 a is sectional view of the Fig. 4 along the direction AA, and Figure 17 b is sectional view of the Fig. 4 along the direction BB, Figure 17 c
It is sectional view of the Fig. 4 along the direction CC.In order to the important feature in clear explanation FINFET device provided by the present invention, Fig. 4
Interlayer dielectric layer is not shown.It is described in detail below with reference to FINFET device of the Fig. 4 and Figure 17 to the present embodiment.
The FINFET device includes semiconductor substrate 1, and semiconductor substrate 1 has several spaced fins positioned at surface
Piece 10, two neighboring fin 10 are isolated structure 11 and separate, and the upper surface S1 of isolation structure 11 is lower than the upper surface S2 of fin 10.
In the present embodiment, semiconductor substrate 1 be body silicon substrate, material can for monocrystalline substrate, multicrystalline silicon substrate,
Amorphous silicon substrate, germanium silicon substrate, carbon silicon substrate etc..It, can be in the table of the body silicon substrate by being performed etching to the body silicon substrate
Face forms several spaced fins 10.
Further, in the present embodiment, the material of isolation structure 11 is to utilize FCVD (Flowable Chemical
Vapor Deposition, mobility chemical vapor deposition) silica that is formed of technique, why using FCVD technique be because
It can form the higher isolation structure 11 of quality, will not generate gap.Certainly, in other embodiments, isolation structure 11 can also
To be formed using traditional chemical vapor deposition process, atom layer deposition process etc..
It should be noted that in the alternative of the present embodiment, semiconductor substrate 1 or silicon-on-insulator substrate
(SOI) comprising silicon base, insulating layer, the top layer silicon stacked gradually, if by the way that the top layer silicon is patterned and can be formed
Spaced fin 10 is done, the insulating layer is as the isolation structure 11 that two neighboring fin 10 is isolated.
Further, in the present embodiment, semiconductor substrate 1 includes the input and output device for being used to form input and output device
Part area I (i.e. the area IO) and the core device region II (i.e. the area Core) for being used to form core devices, wherein the core devices are used for
Realize the main function of integrated circuit, the input and output device is used to provide corresponding input signal for core devices or will
The corresponding signal of core devices exports.It is to disconnect signal in Fig. 4, between input and output device area I and core device region II.
Wherein, in core device region II: gate structure 5 is across fin 10 and isolation structure 11, and including gate dielectric layer 50
With the grid 51 being located on the gate dielectric layer 50；The upper surface of isolation structure 11 is formed with the first groove 110 and the second groove
111, the first groove 110, the second groove 111 are distributed in the two sides of the gate structure 5 along the extending direction X of fin 10；Grid
External wall 25 is covered on the side wall of structure 5, portion outboard wall 25 extends to the first groove along the thickness direction of semiconductor substrate 1
The side surface of 110 side surface and the second groove 111；Source/drain 3 is formed in the fin 10 of 5 two sides of gate structure.
Isolation structure with gate structure 5 between two adjacent fins 10 and the two neighboring fin 10 in the figure
For 11.In practical applications, gate structure 5 can simultaneously between three or more adjacent fins 10 and fin 10 every
From structure 11.
In the present embodiment, gate dielectric layer 50 is high-k gate dielectric layer, and grid 51 is metal gates, II He of core device region
The FINFET in input and output device area I is metal gate transistor.
In the present embodiment, the external wall 25 on 110 side surface of the first groove extends to the bottom wall of the first groove 110, the
External wall 25 on two grooves, 111 side surface extends to the bottom wall of the second groove 111.
In the alternative of the present embodiment, the external wall 25 on 110 side surface of the first groove can also be with the first groove 110
Bottom wall there are certain intervals, the external wall 25 on 111 side surface of the second groove can also exist with the bottom wall of the second groove 111
Certain intervals.
In the present embodiment, the material of external wall 25 is silicon nitride.Certainly, in other embodiments, external wall 25 can also
With the material for selecting other elching resistants good.
In the present embodiment, source/drain 3 includes the groove 30 being formed in the fin 10 of 5 two sides of gate structure, and
The epitaxial layer 31 being filled in groove 30.
Further, in the present embodiment, groove 30 is ∑ type (as sigma type), and the material of epitaxial layer 31 is SiGe,
To apply stress to the channel of FINFET to improve the carrier mobility of transistor.Further, epitaxial layer 31 exceeds
The upper surface of fin 10, so that source/drain 3 is the source/drain of lifting, to improve the performance of transistor.It should be noted that
In technical solution of the present invention, the construction of source/drain 3 should not be limited to given embodiment, can be according to FINFET device
The performance requirement of part makes corresponding adjustment, for example, groove 30 may be arranged as rectangle, the material of epitaxial layer 31 can also be
SiC。
In the present embodiment, in core device region II: inside wall 23 is also formed between gate structure 5 and external wall 25,
Inside wall 23 is covered on the side wall of gate structure 5, and external wall 25 is covered in inside wall 23.The material of inside wall 23 can be
Silica, silicon nitride, silicon oxynitride etc.；In addition, fin 10, isolation structure 11, the first groove 110, the second groove 111, source electrode/
Interlayer dielectric layer 4 is covered in drain electrode 3, interlayer dielectric layer 4 surrounds the gate structure 5 for being covered with inside wall 23 and external wall 25.
In the present embodiment, the structure in input and output device area I is substantially identical as the structure of core device region II, the two
Between difference be: in input and output device area I, on the one hand, gate structure includes pseudo- gate dielectric layer 20 and is located at pseudo- grid and is situated between
Grid 51 on matter layer 20, pseudo- gate dielectric layer 20 and the gate dielectric layer 50 of core device region II are formed in different processes, another
Aspect, the first groove and the second groove of not formed core device region II in the isolation structure of gate structure two sides.
So far, semiconductor device according to an embodiment of the present invention and its manufacturing method is described in detail.In order to avoid
Cover design of the invention, do not describe some details known in the field, those skilled in the art as described above,
Completely it can be appreciated how implementing technical solution disclosed herein.In addition, each embodiment for being instructed of this disclosure can be with
Independent assortment.It should be appreciated by those skilled in the art, can to embodiments illustrated above carry out it is a variety of modification without departing from
The spirit and scope of the present invention as defined in the appended claims.
Claims (20)
1. a kind of FINFET device characterized by comprising
Semiconductor substrate, have positioned at surface several spaced fins, the two neighboring fin be isolated structure every
It opens, the upper surface of the isolation structure is lower than the upper surface of the fin；
Across the gate structure of the fin and isolation structure, the gate structure include gate dielectric layer and be located at the gate medium
Grid on layer；
The first groove and the second groove of the upper surface of the isolation structure are set, and first groove, the second groove are along institute
The extending direction for stating fin is distributed in the two sides of the gate structure；
The external wall being covered on the gate structure sidewall, thickness direction of the part external wall along the semiconductor substrate
Extend to the side surface of first groove and the side surface of the second groove；
Source electrode and drain electrode in the fin, the source electrode, drain electrode are distributed in the two sides of the gate structure.
2. FINFET device as described in claim 1, which is characterized in that the material of the external wall is silicon nitride.
3. FINFET device as described in claim 1, which is characterized in that thickness of the external wall along the semiconductor substrate
Direction extends to the bottom wall of the bottom wall of first groove, the second groove.
4. FINFET device as described in claim 1, which is characterized in that the source electrode, drain electrode include being arranged in the fin
The epitaxial layer of interior groove and the filling groove.
5. FINFET device as claimed in claim 4, which is characterized in that the groove is sigma type.
6. FINFET device as described in claim 1, which is characterized in that the semiconductor substrate includes being used to form core device
The core device region of part and the input and output device area for being used to form input and output device；
The core devices include the fin, the isolation structure, the gate structure, first groove, described second
Groove, the external wall, the source electrode and the drain electrode；
The input and output device includes the fin, the isolation structure, the gate structure, the external wall, the source
Pole and the drain electrode.
7. FINFET device as described in claim 1, which is characterized in that the material of the isolation structure is to utilize FCVD technique
The silica of formation.
8. FINFET device as described in claim 1, which is characterized in that the gate dielectric layer is high-K gate dielectric layer, the grid
Extremely metal gates.
9. FINFET device as claimed in any one of claims 1 to 8, which is characterized in that the semiconductor substrate is body silicon lining
The lower end at bottom, the fin is surrounded by the isolation structure.
10. a kind of forming method of FINFET device characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate has several spaced fins positioned at surface, two neighboring institute
It states fin and is isolated structure and separate, the upper surface of the isolation structure is lower than the upper surface of the fin；
It is developed across the gate structure of the fin and isolation structure, the gate structure includes gate dielectric layer and is located at the grid
Grid on dielectric layer；
The first groove and the second groove are formed in the upper surface of the isolation structure, first groove, the second groove are described in
The extending direction of fin is distributed in the quasi- region two sides for forming the gate structure；
External wall is formed around the quasi- region for forming the gate structure, the part external wall is along the semiconductor substrate
Thickness direction extends to the side surface of first groove and the side surface of the second groove；
The source electrode and drain electrode being located in the fin is formed, the source electrode, drain electrode are distributed in the quasi- area for forming the gate structure
Domain two sides.
11. forming method as claimed in claim 10, which is characterized in that the forming method of the gate structure includes:
Before forming first groove and the second groove, pseudo- grid structure is formed in the quasi- region for forming the gate structure,
Dummy gate structure includes pseudo- gate dielectric layer and the dummy grid on the pseudo- gate dielectric layer, and the puppet gate dielectric layer at least covers
The fin is covered, the dummy grid covers the fin and isolation structure；
It is formed after first groove and the second groove, forms the external wall in the side wall of dummy gate structure；
It is formed after the external wall, the source electrode, the drain electrode is respectively formed in the fin of dummy gate structure two sides；
Formed after the source electrode and drain electrode, formed cover the fin, isolation structure, the first groove, the second groove, source electrode and
Drain electrode, and surround the interlayer dielectric layer of dummy gate structure, the upper table of the upper surface of the interlayer dielectric layer and the dummy grid
Face flushes；
Dummy gate structure is removed, to form gate trench in the interlayer dielectric layer；
The gate structure is formed in the gate trench.
12. forming method as claimed in claim 11, which is characterized in that the material of the puppet gate dielectric layer is thermal oxidation silicon.
13. forming method as claimed in claim 12, which is characterized in that the material of the isolation structure is to utilize FCVD technique
The silica of formation.
14. forming method as claimed in claim 10, which is characterized in that the material of the external wall is silicon nitride.
15. forming method as claimed in claim 10, which is characterized in that thickness of the external wall along the semiconductor substrate
Direction extends to the bottom wall of the bottom wall of first groove, the second groove.
16. forming method as claimed in claim 10, which is characterized in that the source electrode, drain electrode include being arranged in the fin
The epitaxial layer of interior groove and the filling groove.
17. forming method as claimed in claim 16, which is characterized in that the groove is sigma type.
18. forming method as claimed in claim 10, which is characterized in that the semiconductor substrate includes being used to form core device
The core device region of part and the input and output device area for being used to form input and output device；
The core devices include the fin, the isolation structure, the gate structure, first groove, described second
Groove, the external wall, the source electrode and the drain electrode；
The input and output device includes the fin, the isolation structure, the gate structure, the source electrode and the leakage
Pole.
19. forming method as claimed in claim 10, which is characterized in that the gate dielectric layer is high-K gate dielectric layer, the grid
Extremely metal gates.
20. such as the described in any item forming methods of claim 10 to 19, which is characterized in that the semiconductor substrate is body silicon lining
The lower end at bottom, the fin is surrounded by the isolation structure.
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