CN109239738A - Satellite-signal simulative generator applied to three signal communications system of Beidou - Google Patents

Abstract

The present invention provides a kind of satellite-signal simulative generators applied to three signal communications system of Beidou, A/D samples to obtain noise signal, it is divided into two paths of signals behind the bottom of making an uproar of frequency range needed for being gone DC Module and bandpass filter to generate, the carrier modulation of paired data code has been mixed with numeric data code all the way, another way is multiplied to obtain the noise signal for needing power with the noise coefficient being pre-stored in RAM, and the simulation satellite signal to form final output is combined with carrier signal；Simulation satellite signal deposits output inside FPGA and resolves module to base band, by exporting after digital AGC fixed ampllitude to digital I/O interface；Or the output of analog intermediate frequency frequency signal is converted by D/A.

Description

Satellite-signal simulative generator applied to three signal communications system of Beidou

Technical field

The invention belongs to satellite communication field, be related to it is a kind of applied to No. three Testing Platforms for defending guiding systems of Beidou, More particularly to a kind of No. three signal imitation generators of Beidou based on FPGA design exploitation.

Background technique

It is led in receiver performance test defending, it usually needs compare under the satellite-signal of specified power, receiver receives The carrier-to-noise ratio arrived, positioning accuracy, pseudorange, the bit error rate, the performance indicators such as anti-interference ability are simultaneously analyzed.

The energy of Big Dipper satellite signal is very low, is submerged in noise, and receiver receives satellite-signal and connects usually using satellite Antenna is received to receive star to day or generated by simulation signal generator.

The advantages of antenna receives star to day is close to actual environment, but signal is easy to be shielded from object, weather, and time etc. is natural Factor influences, and the index property of can refer to is poor, and retrospect is difficult, it is complex to receive loop, and signal energy demarcates inaccuracy.

Simulation satellite signal source is to defend guiding systems design phase common satellite-signal occurrence of equipment, it is exported comprising complete Navigation information signal；But signal source is at high cost, and volume is big, carries difficulty, is limited its usage mode, is not easy to exploitation debugging The test in stage uses.

Summary of the invention

For overcome the deficiencies in the prior art, the present invention provides a kind of satellite-signal applied to three signal communications system of Beidou Simulative generator includes basic satellite-signal feature, saves down coversion part, the intermediate frequency that receiver can export the module Signal capture, which receives, to be resolved, and has the advantages that minimize, is inexpensive, configurable and be easy to apply.

The technical solution adopted by the present invention to solve the technical problems is: a kind of defending applied to three signal communications system of Beidou Star signal imitation generator, based on inside FPGA platform A/D, D/A, golden code generation module, remove DC Module, carrier modulation mould Block, RAM, signal export energy control module, digital AGC and number I/O interface.

The A/D samples to obtain noise signal, and noise signal removes A/D via going DC Module to carry out power statistic Bring direct current signal is sampled, then is divided into two paths of signals after 20M bandpass filter generates the bottom of making an uproar of required frequency range, is being carried all the way The carrier modulation of paired data code has been mixed in wave modulation module with numeric data code, has obtained carrier signal, another way is prestored with one group Noise coefficient in RAM obtains needing the noise signal of power, and and carrier wave after signal output energy control module is multiplied Signal combines the simulation satellite signal to form final output；Simulation satellite signal selects to exist according to the difference of output interface demand Deposit output resolves module to base band inside FPGA, by exporting after digital AGC fixed ampllitude to digital I/O interface；Or turned by D/A Turn to the output of analog intermediate frequency frequency signal.

The golden code generation module includes a pair of multistage feedback shift register；Register capacity is by different satellite systems Code rate determine that the position of initial code phase positions and phase selector illustrates the different asterisk of the satellite system, golden code to data The band spectrum modulation gain of code is controlled by the bit wide of system clock frequency and numeric data code.

The golden code generation module includes a pair of multistage feedback shift register；Shift register is second is that shift register One translational Equivalent Sequence, shift register two obtain exporting golden code after being added with one exclusive or of shift register.

The golden code generation module realizes translational Equivalent Sequence by phase selector, and phase selector selection displacement is posted The third level deposit unit of storage two exports, and the result is added with the afterbody of register series one output exclusive or.

The beneficial effects of the present invention are:

1. major function is realized by FPGA internal components, hsrdware requirements are low, convenient for exploitation.

2. entire signal generator is the FPGA development board comprising peripheral circuits such as A/D, D/A, digital output ports, it is easy to Project Realization, and it is low in cost.

3. there are a variety of output interface forms such as number, simulation, the test request of different receivers system can be met, reduced The compatibility issue easily occurred is matched in hardware interface.

4. configuration is flexibly, no replacement is required hardware, the design parameters such as noise coefficient that need to only change just can satisfy receiver Capture demand of the signal to bottom of making an uproar.

5. stable working state is not influenced substantially by external interference signal, application state etc..

6. small in size, entire generator only includes the hardware modules such as FPGA, single channel AD/DA, low-noise amplifier；Power consumption Low, typical case power consumption is not higher than 800mw, can carry, easy-to-use.

Detailed description of the invention

Fig. 1 is signal generator internal signal basic procedure block diagram.

Fig. 2 is signal generator test board interface diagram.

Fig. 3 is golden code generation module structure chart

Fig. 4 is use environment of the present invention in the anti-narrowband disturbed test of receiver.

Specific embodiment

Present invention will be further explained below with reference to the attached drawings and examples, and the present invention includes but are not limited to following implementations Example.

The present invention can produce the base band code (golden code) of the B2a frequency point of imitative Big Dipper satellite signal, and it is completed coding and BOCK modulation, while the quantization of spatial noise signal sampling is acquired, the two group is merged simulation output receiver in actual rings Intermediate-freuqncy signal after the satellite-signal received in border is downconverted, receiver can carry out related, despreading to the signal, and obtain The relevant peaks information similar with actual signal, for common receivers performance tests such as carrier-to-noise ratio assessments, to assess entire hardware The working condition of system, insertion loss, capture ability, the performance indicators such as anti-interference ability.

The present invention is based on FPGA platform, major function is realized by its internal components；Generator includes A/D1, D/A2, gold Code generation module 3 goes DC Module 4, carrier modulation block 5, RAM6, signal output energy control module 7,8 sum number of digital AGC Word input and output I/O9 etc.；Specific structure is as follows:

Golden code (C/A code) i.e. pseudo noise code, it, which is contained, defends the raw information for leading signal, it is a pair of of binary system pseudorandom Number Sequence, by a pair of of binary system preferably to generation, circuit implementations are a pair of multistage feedback shift registers；Register is long Degree determines that the position of initial code phase positions and phase selector illustrates the satellite system by the code rate (bandwidth) of different satellite systems The band spectrum modulation gain of different asterisks, golden code to numeric data code is controlled by the bit wide of system clock frequency and numeric data code, numeric data code Being formed after 20M (the civilian frequency point main lobe bandwidth of B2A) bandpass filtering, there is the baseband signal of respective satellite frequency point bandwidth to give down Grade module.

Fig. 4 is the implementation of the golden code generation module of the present invention, it shifts the translational Equivalent Sequence of shift register one The exclusive or of register two and one obtains exporting golden code after being added.The characteristics of shift register is that the output at per moment is last moment Input, translational Equivalent Sequence is realized by phase selector, and the third level of phase selector selection shift register two is posted Memory cell output, and the result is added with the afterbody of register series one output exclusive or.

Such as Fig. 1, noise sample is obtained by 16 A/D sample quantizations, and A/D input terminal need to connect the low noise of level-one corresponding frequency band Acoustic amplifier, noise signal first pass through 4 power of DC Module statistics removal A/D sampling bring direct current signal (signal Will affect AGC output), then through 20M bandpass filter generate needed for frequency range bottom of making an uproar after be divided into two paths of signals, all the way with numeric data code It is mixed the carrier modulation of 5 complete paired data codes.The noise coefficient that another way noise is pre-stored in memory 6 with one group is exported through signal After energy control module 7 is multiplied, the noise signal for needing power is obtained, and the simulation to form final output is combined with carrier signal Satellite-signal.

Noise coefficient is stored in RAM, and length is determined by A/D digit, controls its numerical value using the online RAM of FPGA, The carrier-to-noise ratio of output signal is obtained according to expectation, by adjusting noise coefficient significance bit, each significance bit can bring making an uproar for 6dB Acoustic gain (carrier-to-noise ratio is 0 when 0 gain), to control the composition of final signal output signal.Simulation satellite signal connects according to output The difference of mouth demand can deposit output to base band directly inside FPGA and resolve module；It exports after 8 fixed ampllitude of digital AGC to number Word interface signal 9；It can also be converted into the output of analog intermediate frequency frequency signal by 16 D/A, be connected to the processing of other hardware acceptances.

The invention belongs to baseband processing portion, simulation is intermediate-freuqncy signal digital processes after radiofrequency signal is downconverted Point, it is 62MHz that three B2A system of Beidou, one typical operating environment, which is clock, signal center frequency 15.48MHz, and signal bandwidth is 20MHz；Numeric data code generation module selects level Four feedback shift register, three times band spectrum modulation, and initial phase selection is set as three Number star.By taking the test environment of the anti-narrowband interference performance of Beidou receiver system as an example, FPGA model is using Xilinx company Kintex7, AD9268 high-speed-differential AD, D/A digit sixteen bit；The sampling of signal generator A/D end interface is produced by vector signal source Raw to be sent into inside FPGA with noisy noise signal, preset noise coefficient is " 0100000000 ", it and sampling noise The product representation internal gain of noise signal (number of significant digit represents 6dB), with noisy noise signal and satellite Signal combination output is connected to receiver card with noisy simulation satellite signal in the form of digital link, and Beidou receives Machine module carries out resolving processing to the signal received, and resolved data is reported to assessment system by serial ports, passes through serial ports Debugging assistant compares the carrier-to-noise ratio information received under disturbance size cases, it can be estimated that the anti-interference energy of the receiver Power.

Claims (4)

1. a kind of satellite-signal simulative generator applied to three signal communications system of Beidou, it is characterised in that: be based on FPGA platform A/D, D/A of inside, golden code generation module go DC Module, carrier modulation block, RAM, signal output energy control module, Digital AGC and number I/O interface；The A/D samples to obtain noise signal, and noise signal carries out power via removing DC Module Statistics, removal A/D samples bring direct current signal, then is divided into two-way after 20M bandpass filter generates the bottom of making an uproar of required frequency range Signal has been mixed the carrier modulation of paired data code in carrier modulation block with numeric data code all the way, obtains carrier signal, another Lu Yuyi group is pre-stored in the noise coefficient in RAM and obtains needing the noise of power to believe after signal output energy control module is multiplied Number, and the simulation satellite signal to form final output is combined with carrier signal；Simulation satellite signal is according to output interface demand Difference, base band resolving module is given in selection deposit output inside FPGA, by exporting after digital AGC fixed ampllitude to digital I/O interface；

Or the output of analog intermediate frequency frequency signal is converted by D/A.

2. the satellite-signal simulative generator according to claim 1 applied to three signal communications system of Beidou, feature exist In: the golden code generation module includes a pair of multistage feedback shift register；Register capacity by different satellite systems code Rate determines that the position of initial code phase positions and phase selector illustrates the different asterisk of the satellite system, golden code to numeric data code Band spectrum modulation gain is controlled by the bit wide of system clock frequency and numeric data code.

3. the satellite-signal simulative generator according to claim 1 applied to three signal communications system of Beidou, feature exist In: the golden code generation module includes a pair of multistage feedback shift register；Shift register is second is that shift register one Translational Equivalent Sequence, shift register two obtain exporting golden code after being added with one exclusive or of shift register.

4. the satellite-signal simulative generator according to claim 3 applied to three signal communications system of Beidou, feature exist In: the golden code generation module realizes that translational Equivalent Sequence, phase selector select shift register by phase selector Two third level deposit unit output, and the result is added with the afterbody of register series one output exclusive or.