CN109189133B

CN109189133B - AC voltage stabilization control method

Info

Publication number: CN109189133B
Application number: CN201811355995.8A
Authority: CN
Inventors: 刘建华; 凌云; 肖会芹
Original assignee: Hunan University of Technology
Current assignee: Baise Power Supply Bureau of Guangxi Power Grid Co Ltd
Priority date: 2018-11-15
Filing date: 2018-11-15
Publication date: 2020-07-31
Anticipated expiration: 2038-11-15
Also published as: CN109189133A

Abstract

The AC voltage stabilizing control method is realized by an AC voltage stabilizer comprising a compensation type main circuit, a sampling comparison unit, a time delay protection unit, a trigger gating control unit, a trigger unit, an error detection judging unit and a protection driving unit, wherein the compensation type main circuit comprises a compensation transformer bank, a thyristor bridge and a relay protection switch. The sampling comparison unit samples the voltage of the alternating current power supply and outputs a trigger gating control value; the trigger gating control unit outputs a trigger control signal according to the delayed trigger gating control value and controls the on-off of the bidirectional thyristor in the thyristor bridge. According to the alternating current voltage stabilization control method, the error detection judging unit and the protection driving unit start/stop the open circuit protection of the thyristor bridge according to whether the trigger gating control value is effective or not while the interlocking control is realized, the power supply of the trigger unit is controlled, the protection force aiming at the abnormity of the working process is effectively enhanced, and the work is more stable and reliable.

Description

AC voltage stabilization control method

Technical Field

The invention relates to the technical field of power supplies, in particular to an alternating current voltage stabilization control method.

Background

The existing compensation type AC voltage stabilizer has the advantages of wide voltage stabilizing range, almost no distortion of waveform, high efficiency of the whole machine and strong load adaptability. The principle is that switching of different winding coils of a primary winding on a compensation transformer is automatically controlled according to the high-low condition of input voltage, bidirectional multi-gear voltage compensation is provided by utilizing the transformation ratio relation of a primary side working winding and a secondary winding or by adjusting the voltage applied to the primary winding, and therefore the purpose of voltage regulation and stabilization is achieved.

The existing compensation type alternating current voltage stabilizer has the defects that when a motor is used for controlling the movement of the carbon brush to change the situation that different voltages are applied to the excitation coil of the compensation transformer, the carbon brush is easy to wear and often fails, when an electronic switch switching mode is used for switching different winding coils of a primary winding on the compensation transformer, or when the voltage applied to the primary winding is adjusted, the delayed turn-off of the electronic switch is easy to cause a power supply short-circuit fault, when a program mode of a single chip microcomputer, P L C and the like is used for controlling the switching of the electronic switch, the problems of program runaway, dead halt and the like can also cause the failure of the voltage stabilizer, or the power supply short-circuit fault.

Disclosure of Invention

In order to solve the problems of the existing compensation type alternating current voltage stabilizer, the invention provides an alternating current voltage stabilizing control method, which comprises the following steps:

dividing the voltage in the alternating current power supply voltage fluctuation interval range into a plurality of voltage grade intervals for compensation control; identifying a voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value corresponding to the voltage grade interval; controlling and selecting 0 or 1 or a plurality of compensation transformers to perform voltage compensation by the on-off combination state of the thyristors in the thyristor bridge, so as to realize the voltage compensation state corresponding to the voltage grade interval; each voltage class interval of the alternating current power supply voltage corresponds to a voltage compensation state.

And judging whether the trigger gating control value is effective or not, and controlling the thyristor bridge to be in an open-circuit protection state when the trigger gating control value is ineffective. Triggering a gating control value to be an M-bit binary value; judging whether the trigger gating control value is effective or not according to the fact that the trigger gating control value is effective when one bit is effective in M-bit binary values of the trigger gating control value; otherwise, triggering the gating control value to be invalid; and M is an integer greater than or equal to 2. Further, the bit in the trigger gating control value is 1 valid and 0 invalid, that is, the high level in the trigger gating control value signal is valid and the low level is invalid; or, the bit in the trigger gating control value is 0 valid and 1 invalid, that is, the low level in the trigger gating control value signal is valid and the high level is invalid; the M trigger gating control values are all effective, and M trigger gating control values are all effective.

And identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value, wherein the trigger gating control value is realized by a sampling comparison unit. The sampling comparison unit comprises an alternating current power supply voltage sampling circuit and a multi-interval voltage comparator circuit, wherein the alternating current power supply voltage sampling circuit converts an effective value of alternating current power supply voltage into a sampling value of the alternating current power supply voltage; the input voltage of the multi-interval voltage comparator circuit is an alternating current power supply voltage sampling value, the input voltage, namely the alternating current power supply voltage sampling value is compared with M-1 threshold voltages to obtain an M-bit comparison output value, and the M-bit comparison output value forms a trigger gating control value. The M-1 threshold voltages are respectively alternating current power supply voltage sampling values corresponding to M-1 intermediate separation values of M voltage grade intervals of the alternating current power supply voltage. The multi-interval voltage comparator circuit comprises M-1 comparators, compares input voltage with M-1 different threshold voltages and outputs M-bit comparison output values; and the M-1 comparators are all powered by a positive single power supply. M-1 different threshold voltages are respectively connected to the non-inverting input ends of the M-1 comparators, and the input voltage is simultaneously connected to the inverting input ends of the M-1 comparators. The high level of the M-bit comparison output value output by the multi-interval voltage comparator is effective, and only one of the M-bit comparison output value is effective. Among the M-1 comparators, the comparator with the lowest threshold voltage directly adopts a positive single power supply to supply power, and other comparators adopt controllable power supplies to supply power; when the comparator is powered by the controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The M-bit comparison output value consists of output values of M-1 comparators and a highest interval judgment value; and when the output values of the M-1 comparators are all low levels, the highest interval judgment value is high level, otherwise, the highest interval judgment value is low level.

The multi-interval voltage comparator circuit comprises M comparators for comparing the input voltage with M different threshold voltages and outputting M-bit comparison output values; the M comparators are all powered by a positive single power supply. The M different threshold voltages are respectively connected to the non-inverting input ends of the M comparators, and the input voltage is simultaneously connected to the inverting input ends of the M comparators. The high level of the M-bit comparison output value output by the multi-interval voltage comparator is effective, and only one of the M-bit comparison output value is effective. Among the M comparators, the comparator with the lowest threshold voltage directly adopts a positive single power supply to supply power, and other comparators adopt controllable power supplies to supply power; when the comparator is powered by a controllable power supply, the output end of the comparator is connected with a pull-down resistor, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, and otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator. The comparator adopts a controllable power supply to supply power, and outputs low level when the controllable power supply stops supplying power to the positive power supply end. The M-bit comparison output value consists of the output values of the M comparators. The M different threshold voltages are respectively the upper limit values of the interval voltages of the M interval voltages.

The positive power supply end of the comparator is connected to the output end of the NOR gate, and the input end of the NOR gate is respectively connected to the output ends of the comparators with the threshold voltages lower than that of the NOR gate. The comparators in the multi-interval voltage comparator circuit preferably adopt a low-power-consumption rail-to-rail operational amplifier powered by a single power supply.

The method for controlling the on-off combination state of the thyristors in the thyristor bridge by the trigger gating control value comprises the steps that the trigger gating control unit triggers the gating matrix selection through the diodes according to the effective trigger gating control value, enables the corresponding trigger control signals to be effective, and controls the on-off combination state of the thyristors in the thyristor bridge.

The thyristor bridge is provided with N thyristors; the diode triggering gating matrix comprises M triggering gating control column lines, N triggering driving row lines and a plurality of diodes; m triggering gating control column lines correspond to M bit triggering gating control values one by one, and an effective triggering gating control value correspondingly enables a signal of one triggering gating control column line to be effective; the N trigger driving row lines correspond to the N thyristors one by one, and the effective correspondence of a trigger driving row line signal enables a trigger control signal of one thyristor to be effective; the trigger control signal effectively turns on the corresponding thyristor. And N is an integer greater than or equal to 4.

When each trigger gating control column line signal is effective, the on-off combination state of a thyristor in a corresponding thyristor bridge is corresponded; when each trigger gating control column line is effective with the column line signal, a diode is arranged between the trigger driving row lines which are required to control the conduction of the thyristor and are in a corresponding on-off combination state for connection, and when a certain trigger gating control column line signal is effective, the diode enables the trigger driving row line signal which is required to control the conduction of the thyristor to be effective.

When the trigger gating control value is changed due to the voltage fluctuation of the alternating current power supply and the thyristors in the thyristor bridge need to be switched to be in different on-off combination states, maintaining a non-trigger area time between the 2 on-off combination states, and turning off all the thyristors in the thyristor bridge.

The maintaining of the one non-trigger area time is realized by a non-trigger area control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; when the control signal of the non-trigger area is effective, the non-trigger area time is maintained. Further, after the trigger gating control value is changed, the width time of a single pulse in the non-trigger area control signal is selected from 10ms to 30 ms.

The trigger control signal for controlling the thyristor bridge is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.

The functions of delaying the trigger gating control value and generating a control signal of a non-trigger area are realized by a delay protection unit; the judgment of whether the trigger gating control value is effective is realized by an error detection judging unit, and the error detection judging unit judges whether the delayed trigger gating control value is effective and outputs a trigger gating control value judging signal.

The method is realized by an alternating current voltage stabilizer comprising a compensation type main circuit, a sampling comparison unit, a delay protection unit, a trigger gating control unit, a trigger unit, an error detection judgment unit and a protection driving unit. The compensation type main circuit comprises a compensation transformer bank and a thyristor bridge; the trigger unit controls the on-off of the thyristor in the thyristor bridge of the main circuit according to the input trigger control signal. The protection driving unit stops/starts open-circuit protection of the thyristor bridge according to whether the trigger gating control value is effective or not, and the specific method is that when the trigger gating control value is ineffective, all upper bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in an open-circuit protection state, or all lower bridge arms of the thyristor bridge are controlled to be disconnected to enable the thyristor bridge to be in the open-circuit protection state; when the thyristor bridge is in an open-circuit protection state, and the error detection judging unit judges that the input trigger gating control value is recovered to be effective, the protection driving unit automatically stops the open-circuit protection state of the thyristor bridge.

The trigger gating control unit comprises a diode trigger gating matrix; the method for enabling the trigger control signal of the thyristor to be effective by enabling the trigger driving row line signal to be effective is that N trigger driving row line signals are directly used as the trigger control signals of N thyristors in a one-to-one correspondence mode. A trigger driving row line signal is effective and corresponds to a method for enabling a trigger control signal of a thyristor to be effective, or the trigger gating control unit further comprises a trigger control signal driving circuit; the input of the trigger control signal driving circuit is N signals for triggering and driving the row lines, and the output is trigger control signals of N thyristors in one-to-one correspondence.

The protection driving unit controls the power supply of the triggering unit according to whether the triggering gating control value is effective or not and whether the control signal of the non-triggering area is effective or not, and the specific method is that only when the triggering gating control value is effective and the control signal of the non-triggering area is ineffective, the power supply of the triggering unit is controlled to be switched on, the triggering unit works normally, and triggering pulse is sent out according to the input triggering control signal; otherwise, the power supply of the trigger unit is cut off, and all trigger pulses are stopped to be sent out.

The thyristors in the thyristor bridge are bidirectional thyristors or thyristor alternating current switches formed by connecting 2 unidirectional thyristors in reverse parallel.

The alternating current voltage stabilization control method has the advantages that only one effective and different trigger gating control value is adopted, gating control of different combination on-off states of the thyristor bridge is realized by the diode trigger gating matrix, the condition that upper and lower bridge arm thyristors of the same full bridge circuit of the thyristor bridge cannot be conducted simultaneously is guaranteed, namely, interlocking control of the upper and lower bridge arm thyristors of the same full bridge circuit is realized, meanwhile, errors occur when voltage grade intervals of alternating current power supply voltage are identified, the invalid trigger gating control value is output, the trigger pulse is stopped being sent out, open circuit protection of the thyristor bridge is carried out, the protection strength aiming at abnormity of the alternating current voltage stabilization working process is effectively enhanced, when the thyristor bridge is in the open circuit protection state, if the trigger gating control value is recovered to be effective, the open circuit protection state of the thyristor bridge can be automatically stopped and is enabled to be in the compensation working state again, and the problem that the single chip microcomputer such as program crash, P L C and the like is not adopted to control the on-off and the on-off switching of the thyristor bridge, and the fault of the thyristor is avoided.

Drawings

FIG. 1 is a block diagram of an AC voltage regulator implementing an AC voltage regulation control method;

FIG. 2 shows an embodiment 1 of a compensated main circuit;

FIG. 3 illustrates an embodiment of a compensated main circuit 2;

FIG. 4 shows a sample comparison unit of example 1;

FIG. 5 shows a sample comparison unit of example 2;

FIG. 6 is a block diagram of an embodiment of a delay protection unit;

FIG. 7 is a diagram of an embodiment of a delay detection circuit 1 of the delay detection module for triggering the strobe control value signal Y10;

FIG. 8 is a circuit diagram of embodiment 2 of the delay detection circuit for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 9 is a block diagram of an embodiment of a delay detection circuit 3 for triggering the strobe control value signal Y10 in the delay detection module;

FIG. 10 is a block diagram of an embodiment of a no trigger area control signal generation module;

FIG. 11 is a diagram illustrating a partial correlation waveform in the delay protection unit;

FIG. 12 is an embodiment of a trigger circuit for triggering the triac SR1 in the trigger unit;

FIG. 13 shows an embodiment of a trigger strobe control unit 1;

FIG. 14 shows an embodiment of a trigger strobe control unit 2;

FIG. 15 shows a trigger strobe control unit embodiment 3;

FIG. 16 shows an embodiment of an error detection and determination unit;

fig. 17 is a protection drive unit embodiment.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a block diagram of an ac voltage regulator implementing an ac voltage stabilization control method, in which a sampling and comparing unit samples the voltage of an ac power supply and outputs a trigger gating control value P2; the delay protection unit inputs a trigger gating control value P2 and outputs a delayed trigger gating control value P3 and a non-trigger area control signal P4; the trigger gating control unit inputs the delayed trigger gating control value P3 and outputs a trigger control signal P5; the trigger unit sends a trigger signal P6 to the compensation type main circuit according to an input trigger control signal P5 to control the on-off of a bidirectional thyristor in a thyristor bridge; the error detection judging unit inputs the delayed trigger gating control value P3 and outputs a trigger gating control value judging signal P7; the protection driving unit inputs a non-trigger area control signal P4 and a trigger gating control value judging signal P7, stops/starts open circuit protection of the thyristor bridge according to whether the trigger gating control value judging signal P7 is effective, and controls the power supply of the trigger unit according to whether the trigger gating control value judging signal P7 is effective and whether the non-trigger area control signal P4 is effective.

Fig. 2 shows a compensation type main circuit embodiment 1, in which a compensation transformer bank is composed of compensation transformers TB1 and TB2, a thyristor bridge is composed of 6 bidirectional thyristors SR1-SR6, a fuse FU1, normally open switches KA-1, KA-2 and KA-3 of a relay, and normally closed switches KA-5 and KA-6 of the relay constitute a relay protection circuit.

In the figure 2, compensation coils of compensation transformers TB and TB are connected in series on a phase line, the input end of the phase line is A, the output end of the compensation transformers TB and TB are A2, voltage on excitation coils of the compensation transformers TB and TB is controlled by a thyristor bridge arm, 1 thyristor full-bridge circuit comprises an upper thyristor bridge arm and a lower thyristor bridge arm, in the figure 2, one ends of the excitation coils TB and TB are connected in parallel and then connected to the thyristor full-bridge circuit formed by the SR and the SR, the other ends of the excitation coils TB and TB are respectively connected to the thyristor full-bridge circuit formed by the SR and the SR, compensation voltages of the TB and the TB are different, no consideration is given to a compensation mode that the compensation voltages are mutually offset, the compensation transformer group has 6 voltage compensation states of a forward TB, a forward TB + TB, a reverse TB and a reverse TB + TB, and a0 voltage compensation state when an input voltage is within a normal range, the AC power supply voltage input at the input end A of the phase line can be divided into 7 voltage intervals at most for compensation control, in the figure 2, N is a zero line, and G.

Fig. 3 shows a compensation type main circuit embodiment 2, in which a compensation transformer bank is composed of compensation transformers TB1, TB2, TB3, a thyristor bridge is composed of 8 bidirectional thyristors SR1-SR8, a fuse FU1, normally open switches KA-1, KA-2, KA-3, KA-4 of relays, and normally closed switches KA-4, KA-5, KA-6 of relays constitute a relay protection circuit.

In fig. 3, the compensation coils of the compensation transformers TB1, TB1 and TB1 are all connected in series on the phase line, the input end of the phase line is 1 a1, the output end of the phase line is 1 a 2. the voltage on the excitation coil of TB1 is controlled by a thyristor bridge, one ends of the excitation coils of TB1, TB1 and TB1 are connected in parallel and then connected to a thyristor full bridge circuit formed by SR1 and SR1, the other ends of the excitation coils of TB1, TB1 and TB1 are connected to the thyristor full bridge circuit formed by SR1 and SR1, the other ends of the excitation coils of SR1, TB1 and TB1 are respectively connected to the thyristor full bridge circuit formed by SR1, SR1 and SR1, the compensation voltages of TB1, TB1 and TB1 are all different, no compensation mode that the compensation voltages are mutually offset is considered, the compensation transformer group has at most 7 forward directions, 14 voltage compensation states, when one input end of an input voltage is in a normal range, the input end of an ac power supply voltage can be controlled by a plurality of a thyristor G, a bidirectional control signal 1, a bidirectional control circuit is a 1.

Each of the triacs of fig. 2 and 3 may be replaced by 2 antiparallel triacs. In fig. 2 and 3, the relay normally open switch and the relay normally closed switch form a relay protection switch.

Dividing the voltage in the alternating current power supply voltage fluctuation interval range into M voltage grade intervals, sampling the alternating current power supply voltage by a sampling comparison unit to obtain an alternating current power supply voltage sampling value, comparing the alternating current power supply voltage sampling value by M comparators, and outputting a trigger gating control value formed by M binary digits; when the alternating current power supply voltage is in one of the M voltage grade intervals, the M bits trigger the corresponding one bit in the gating control value to be valid, and the other bits are invalid. The effective bit of the M bit trigger gating control value is high level, namely binary 1; the invalid bit is low level, i.e. binary 0; or, the effective bit of the M-bit trigger gating control value is low level, namely binary 0; the invalid bit is high, i.e. binary 1.

Fig. 4 shows an embodiment of a sampling comparison unit 1, which performs compensation control with respect to an embodiment 1 of a compensation type main circuit, in an ac power supply voltage sampling circuit, ac power supply voltages input from a phase line L a1 and a neutral line N are stepped down by a transformer TV, rectified by a rectifier bridge composed of diodes DV1-DV4, filtered by a capacitor CV1, and divided by resistors RV1 and RV2, so as to obtain an ac power supply voltage sampling value U1 in a direct proportional relationship with an effective value of the input ac power supply voltage.

In the multi-interval voltage comparator circuit shown in FIG. 4, resistors RF-RF form a voltage divider circuit, 7 threshold voltages UF-UF 7.7 comparators FA-FA are obtained after voltage division is carried out on a power supply + VCC, comparison between an AC power supply voltage sampling value U and 7 threshold voltages UF-UF is achieved, an output trigger gating control value P is formed by output Y-Y of the 7 comparators FA-FA, voltage in the fluctuation interval range of the AC power supply voltage is divided into 7 voltage level intervals 1-7, an operational amplifier FA forms a follower, the AC power supply voltage sampling value U is driven by the follower FA and then simultaneously sent to an inverting input end of the comparators FA-FA, the AC power supply voltage sampling value U can also be directly and simultaneously sent to an inverting input end of the comparators FA without being driven by the follower FA, the 7 threshold voltages UF-FA are respectively sent to a same-phase input end of the comparators FA, in FIG. 4, the power supply + VCC can be replaced by other precise power supplies, the voltage divider circuit divides the threshold voltages more precisely, the operational amplifier voltage and the comparators FA-UF-FA adopt optimized single power supply rails, such as an operational power supply voltage, operational power supply voltage selection rail voltage selection.

In FIG. 4, the NOR gates FH2-FH7 constitute controllable power supplies for the comparators FA2-FA7, i.e., the power supplies for the comparators FA2-FA7 are controlled by the outputs Y11-Y16, respectively; the resistors RB2-RB7 are pull-down resistors of the outputs Y12-Y17 respectively, and when the power supply of the corresponding comparator is close to 0V and the output of the corresponding comparator is in a high-impedance state, the level is pulled to be low. The power supply of the comparator FA1 is connected to the power supply + VCC1, and is in a normal working state, and the output Y11 controls the power supplies of the comparators FA2-FA 7. For example, when the input ac power supply voltage is low and is in the lowest voltage class section 1 of 7 voltage class sections, Y11 outputs high level, all the outputs of nor gates FH2-FH7 are low level, all the single power supply sources of comparators FA2-FA7 are close to 0V, all the outputs are close to 0V or high resistance state, and resistors RB2-RB7 pull the outputs Y12-Y17 low level, respectively. When the input alternating current power supply voltage is not in the lowest voltage class section 1 of the 7 voltage class sections, Y11 outputs low level, NOR gate FH2 outputs high level to provide power supply for comparator FA2, at this time, if the input alternating current power supply voltage is in the voltage class section 2, Y12 outputs high level, NOR gates FH3-FH7 all output low level, single power supply of comparators FA3-FA7 all approach 0V, the output all approach 0V or high impedance state, and resistors RB3-RB7 respectively pull the output Y13-Y17 low level. When the input alternating current power supply voltage is higher than the voltage grade interval 2, Y11 and Y12 both output low level, NOR gates FH2 and FH3 both output high level, and power supplies are respectively provided for comparators FA2 and FA3, at this time, if the input alternating current power supply voltage is in the voltage grade interval 3, Y13 outputs high level, NOR gates FH4-FH7 all output low level, single power supplies of comparators FA4-FA7 all approach 0V, the outputs all approach 0V or are in high resistance state, and resistors RB4-RB7 respectively pull the outputs Y14-Y17 to low level. By analogy, when the input alternating-current power supply voltage is in the voltage class interval 4, the Y14 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage level interval 5, Y15 outputs high level, and other outputs are low level; when the input alternating current power supply voltage is in a voltage class interval 6, Y16 outputs high level, and other outputs are low level; when the input ac power supply voltage is in the voltage class interval 7, Y17 outputs a high level, and the other outputs are low levels. When the nor gate FH2-FH7 selects a 74HC series high-speed CMOS gate, for example, when the 8-input nor gate 74HC4078, the three-input nor gate 74HC27, the four-input nor gate 74HC02, etc. are selected, or when the nor gate function is realized by a 74HC series high-speed CMOS or nor gate, the high-level driving current of the 74HC series high-speed CMOS can reach 4mA, which is enough to drive a single-channel rail-to-rail operational amplifier with the static operating power supply current less than 1 mA. The power supply of the NOR gate FH1-FH6 is power supply + VCC 1.

The fluctuation range of the input alternating current power supply voltage is set as 220V +/-10%, and the input alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. By adopting the sampling comparison unit embodiment 1 in fig. 4, the voltage input between 242V and 198V can be divided into 7 voltage class intervals with the interval voltage size of 6.4V, wherein the voltage of 3 voltage class intervals is higher than the required output voltage range, and voltage reduction compensation is required; the voltage of the 3 voltage class intervals is lower than the required output voltage range, and boosting compensation is needed; the 1 voltage class interval is within the required output voltage range, and 0 voltage compensation is carried out, namely no compensation is carried out. The voltage interval of 6.4V is not more than 220V +/-1.5 percent, and the requirement that the output is controlled within 220V +/-2 percent is met; the fluctuation interval of the alternating current power supply voltage corresponding to 7 voltage class intervals of 6.4V is 242.4V to 197.6V, and the actual fluctuation range is covered. The compensation is carried out by adopting the compensation type main circuit embodiment 1 in the figure 2, the compensation voltage of TB1 is low, and the compensation voltage of TB2 is high; the compensation voltage of the TB2 is 2 times of the compensation voltage of the TB1, and when the voltage on the exciting coil is 220V, the TB1 compensation voltage is 6.4V, and the TB2 compensation voltage is 12.8V. The selection of the threshold voltages UF1-UF7 is related to the ratio between the sampled values of the AC supply voltage U1 and the AC supply voltage; setting the proportion of the alternating current power supply voltage sampling value U1 to the alternating current power supply voltage to be 0.01, namely the alternating current power supply voltage sampling value U1 is 1% of the effective value of the alternating current power supply voltage, and the voltage sampling value range corresponding to the voltage input between 242V and 198V is 2.42V to 1.98V; when the alternating current power supply voltage is divided into 7 voltage class intervals with interval voltage of 6.4V, 7 threshold voltages UF7-UF1 are 2.424V, 2.36V, 2.296V, 2.232V, 2.168V, 2.104V and 2.04V respectively, and correspond to voltage sampling values for dividing the voltage range from 242.4V to 197.6V into the upper limit values of the 7 voltage class intervals respectively; the size of the resistors RF1-RF8 can be calculated according to the size of the 7 threshold voltages UF1-UF7 and + VCC 1.

Since the compensation mode of the compensation type main circuit embodiment 1 automatically has the schmitt characteristic, the comparator FA1 to the comparator FA7 do not constitute a schmitt comparator. The trigger strobe control value output in FIG. 4 is active high; and a stage of inverter is added at the output ends of the comparators FA1-FA7, and the output trigger gating control value becomes active low.

In embodiment 1 of the sampling comparison unit in fig. 4, when the input ac power voltage is lower than the minimum voltage level interval range, the output signal corresponding to the minimum voltage level interval in the output trigger gate control value is valid, that is, the output is Y11 valid; at the moment, the main circuit performs corresponding voltage reduction compensation according to the condition that the input alternating current power supply voltage is in the minimum voltage grade interval. When the voltage of the input alternating current power supply is higher than the range of the maximum voltage level interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment. If the comparator FA7 in the sampling comparison unit embodiment 1 of fig. 4 is removed, the 6 threshold voltages UF6-UF1 of the comparators FA6-FA1 are unchanged, being 7 intermediate divided voltage values of the voltage sample values corresponding to the alternating current power supply voltage values divided by 7 voltage class intervals; the output signal of the nor gate FH7, namely the highest interval judgment value Y17-1, is directly used as Y17 in the trigger gating control value, so that when the input alternating current power supply voltage is in or higher than the range of the maximum voltage class interval, the output of the Y17 is effective, and the main circuit performs corresponding voltage reduction compensation according to the condition that the input alternating current power supply voltage is in the maximum voltage class interval.

Embodiment 1 of fig. 4 may be performed for the compensated main circuit embodiment 2, and in this case, it is necessary to divide the voltage in the ac power supply voltage fluctuation interval range into more voltage class intervals. For example, when the voltage in the fluctuation interval of the ac power supply voltage is divided into 15 voltage class intervals, the circuit of fig. 4 should be extended to 15 comparators for comparison with 15 threshold voltages of different sizes; or 14 comparators are adopted to compare with 14 threshold voltages with different sizes; the output trigger strobe control value P2 would consist of 15 bits, e.g., Y11-Y115.

Fig. 5 shows an embodiment 2 of a sampling comparison unit, which is used for performing compensation control on the embodiment 2 of a compensation type main circuit, in fig. 5, FD1 is a true effective value detection device L TC1966, L TC1966, a transformer TV1, a capacitor CV2 and a capacitor CV3 form an ac power supply voltage sampling circuit, and ac power supply voltages input from a phase line L a1 and a zero line N are measured to obtain ac power supply voltage sampling values U2, UIN1 and UIN2 of L TC1966 are ac voltage differential input terminals, USS is a negative power supply input terminal capable of being grounded, UDD is a positive power supply input terminal, GND is a ground terminal, EN is an enable control input terminal with low level effectiveness, UOUT is a voltage output terminal, and COM is an output voltage return terminal.

In fig. 5, FD2, resistor RD1, resistor RD2, and inverters FB1-FB10 form a multi-interval voltage comparator circuit, FD2 is a 10-stage comparison display driver L M3914, which includes an internal voltage divider circuit formed by connecting 10 1k Ω precision resistors in series, which forms 10 comparison threshold voltages and is respectively connected to positive input terminals of 10 comparators in the circuit, the voltage in the fluctuation interval range of the ac power voltage is divided into 10 voltage class intervals 1-10.6, which are internal voltage divider circuit high terminals and are connected to internal standard power output VREF of pin 7 through resistor RD1, 4, which are internal voltage divider circuit low terminals and are connected to ground through resistor RD2, 8, which are internal standard power source low terminals and are connected to ground, 2, which are negative power source terminals and are connected to ground, 3, which are positive power source terminals and are connected to power supply + VCC1, 5, which are signal input terminals and are connected to ac power supply voltage U2, which are internally connected to negative input terminals of 10 comparators, 10-18, 1, 10-L, which are connected to power supply + VCC1, which are connected to signal input terminals, and are connected to ground through other point comparator circuits, wherein the effective threshold output voltage level of the highest point comparison result of the resistor RD 4642, which is reduced by point comparison circuit 3642, and is also can be controlled by point comparison result of the other point comparison circuit 3642, which is connected to the highest point comparison threshold voltage output voltage of the highest point comparison circuit 3642, and is also connected to the.

In fig. 5, 10 inverters FB1-FB10 are used to invert the output signals L-L respectively to obtain a trigger gating control value p2 consisting of 10 bits of binary Y11-Y110 and effective at high level, where when the ac power voltage is in one of 10 voltage class intervals 1-10, one bit of Y11-Y110 is at high level and the other bits are at low level, for example, when the input ac power voltage is in voltage class interval 10, Y110 outputs high level and the other outputs are at low level, when the input ac power voltage is in voltage class interval 9, Y19 outputs high level and the other outputs are at low level, when the input ac power voltage is in voltage class interval 5, Y15 outputs high level and the other outputs are at low level, when the input ac power voltage is in voltage class interval 1, Y11 outputs high level and the other outputs are at low level, and FB 1-10 in fig. 5 is cancelled, and the output signals FB 6325-85891 are directly used as the trigger gating control value p 2-Y9634 and the trigger gating control value p 3638 and the trigger gating control value p 3-Y3638.

The voltage compensation method comprises the steps of using 10 comparators in L M3914 in FIG. 5, dividing the voltage comparison range of the input alternating power supply voltage fluctuation range into 10 voltage level ranges, setting the fluctuation range of the input alternating power supply voltage to be 220V + 10% to 220V-20%, requiring the input alternating power supply voltage to be stabilized in the range of 220V + -2% for output, adopting an embodiment 2 of a sampling comparison unit in FIG. 5, dividing the voltage input between 242V and 176V into 10 voltage level ranges with the interval voltage size of 7V, wherein the voltage of 3 voltage level ranges is higher than the required output voltage range and needs to be subjected to voltage reduction compensation, adopting a range of 6 voltage level ranges which is lower than the required output voltage range and needs to be subjected to voltage boosting compensation, adopting a range of 1 voltage level range within the required output voltage range, carrying out voltage compensation, namely, wherein the uncompensation is not compensated, the voltage range of 7V is 220V + -1.6%, meeting the requirement of output control within 220V + -2%, the requirement of output voltage range of 7V + -2%, and the fluctuation range of 10 voltage level ranges corresponding to be 220V + -1, 27.6, and 3614V, wherein the fluctuation range of alternating power supply voltage compensation voltage equivalent to be equal to the fluctuation range of a sampling voltage equivalent value of a sampling voltage equivalent to a sampling range of a power supply voltage equivalent 70V equivalent voltage equivalent to a power supply voltage equivalent, a power supply voltage equivalent value equivalent, a sampling range of 1.0825V equivalent to a power supply voltage equivalent 70V equivalent, a power supply voltage equivalent to a power supply voltage range of a power supply voltage equivalent, a power supply voltage equivalent to a power supply voltage equivalent value of a power supply voltage equivalent, a power supply voltage equivalent value of a power supply voltage equivalent to a sampling range of a power supply voltage equivalent to a power supply voltage equivalent to a power supply voltage equivalent value of a power supply voltage equivalent value of a power supply voltage equivalent to a power supply voltage equivalent value of a power supply voltage equivalent voltage.

In embodiment 2 of the sampling comparing unit in fig. 5, when the input ac power voltage is higher than the range of the maximum voltage class interval, the output trigger strobe control value is valid for the output signal corresponding to the maximum voltage class interval, that is, the output is valid for Y110, and the main circuit performs corresponding voltage step-down compensation according to the ac power voltage in the maximum voltage class interval. When the input alternating current power supply voltage is lower than the range of the minimum voltage grade interval, all signals in the output trigger gating control value are invalid, and the main circuit does not perform voltage compensation at the moment.

In fig. 5, 10 comparators of 10 comparators in L M3914 are used to compare and divide the ac power voltage into 10 voltage class intervals, only 9 comparators of 10 comparators in L M3914 are used to compare and divide the ac power voltage into 10 voltage class intervals, for example, the comparison threshold voltage of each comparator is not changed, the comparison threshold voltage of 9 comparators is 9 middle division voltage values of voltage sampling values corresponding to the ac power voltage values divided by 10 voltage class intervals, the output L1 of L M3914 in fig. 5 is not inverted to be used as Y11 in the trigger gate control value, Y11 is selected to be controlled and generated by Y12-Y110 in the trigger gate control value, that is, Y12-Y110 is all invalid, Y11 is invalid, otherwise, Y82923 is invalid, when the input ac power voltage is in or exceeds the maximum voltage class interval, the output trigger control value is Y110, the main circuit performs compensation according to the maximum input ac power voltage, and the main circuit performs compensation according to the minimum input ac power voltage class interval, and when the input ac power voltage is in the minimum voltage compensation range, and the main circuit performs compensation according to the minimum input ac power voltage class interval.

The embodiment 2 of the sampling comparison unit in fig. 5 can also perform compensation control on the compensated main circuit embodiment 1, and at this time, only the voltage within the fluctuation interval range of the input ac power voltage needs to be divided into intervals of no more than 7 voltage classes, that is, the comparison output of no more than 7 classes is selected.

In addition to the sampling comparison unit embodiment of fig. 4 or 5, when compensation control is performed on the compensation type main circuit embodiment 1 or embodiment 2, another ac power supply voltage sampling circuit and comparison circuit may be selected to implement a desired function. The ac power voltage sampling value U1 output by the ac power voltage sampling circuit of fig. 4 may be sent to the multi-interval voltage comparator circuit of fig. 5 for comparison, and a trigger gating control value is output; the sampled value U2 of the ac power voltage output by the ac power voltage sampling circuit of fig. 5 may be sent to the multi-interval voltage comparator circuit of fig. 4 for comparison, and a trigger gating control value is output.

Fig. 6 is a block diagram of an embodiment of a delay protection unit, wherein a delay detection module YC1 respectively delays an input trigger gate control value Y11-Y1M to obtain delayed trigger gate control values Y21-Y2M, and Y21-Y2M form P3; the YC1 module simultaneously and respectively carries out edge detection on signals Y11-Y1M of the trigger gating control value to obtain edge detection signals Y31-Y3M; the no-trigger area control signal generation module YC2 converts the input edge detection signals Y31-Y3M into the no-trigger area control signal P4 for output. In the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 1 of the sampling comparison unit in fig. 4, M is equal to 7; in the block diagram of the embodiment in fig. 6, when the input of the delay detection module YC1 is the trigger gating control value output by the embodiment 2 of the sampling comparison unit in fig. 5, M is equal to 10.

Fig. 7 shows an embodiment 1 of the delay detection circuit for the trigger strobe control value signal Y11 in the delay detection module. The resistor RY0, the capacitor CY0 and the driving gate FY0 realize signal delay of Y11, and a delayed signal Y21 of Y11 is obtained. The resistor RY1, the capacitor CY1, the diode DY1 and the inverter FY1 form a rising edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is output in the output signal YP1 of the inverter FY 1. The resistor RY2, the capacitor CY2, the diode DY2, the inverters FY2 and FY3 constitute a falling edge detection circuit for the input signal Y11, and a single pulse in the form of a negative pulse corresponding to the falling edge of Y11 is output in the output signal YP2 of the inverter FY 3. The nand gate FY4 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY4, that is, when the input signal Y11 changes, the nand gate FY4 outputs a single pulse in the form of a positive pulse. In fig. 7, the drive gate FY0, inverter FY1, inverter FY3 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; the drive gate FY0 may consist of 2 inverters with schmitt inputs.

Fig. 8 shows an embodiment 2 of the delay detection circuit for the trigger strobe control value signal Y11 in the delay detection module. The inverter FY5, the resistor RY3 and the capacitor CY3 invert and delay the input signal Y11 to obtain a delayed inverted signal YP0 of Y11; the inverter FY6 inverts YP0 to obtain a delayed Y11 signal Y21. The signal input by the nand gate FY7 is a delayed inverted signal YP0 of Y11 and Y11, and a single pulse in the form of a negative pulse corresponding to the rising edge of Y11 is generated in the output signal YP 1; the or gate FY8 receives the inverted signals YP0 of Y11 and Y11, and the output signal YP2 generates a single pulse in the form of a negative pulse corresponding to the falling edge of Y11. The nand gate FY9 implements a negative logic or logic function, and when a negative pulse is generated in the input signals YP1 and YP2, a positive pulse is generated in the edge detection signal Y31 output by the nand gate FY9, that is, when the input signal Y11 changes, the nand gate FY9 outputs a single pulse in the form of a positive pulse. In fig. 8, inverter FY6, nand gate FY7, or gate FY8 are preferably devices with schmitt inputs, e.g., inverter select 74HC14, CD40106, etc.; nand gate select 74HC132, CD4093, etc.; or gate select 74HC7032 or 2 inverters with schmitt inputs and 1 nand gate to implement the or gate function.

Fig. 9 is a delay detection circuit embodiment 3 of the delay detection module for the trigger gate control value signal Y11, in which a rising edge detection circuit for the input signal Y11 is composed of a resistor RY1, a capacitor CY1, a diode DY1 and an inverter FY1, and a falling edge detection circuit for the input signal Y11 is composed of a resistor RY2, a capacitor CY2, a diode DY2, an inverter FY2 and an FY3, and a circuit for outputting the edge detection signal Y31 by using a nand gate FY4 is the same as in embodiment 1 of fig. 7. In fig. 9, the signal delay of Y11 is realized by inverters FY11, FY12, FY13, and FY14, and a delayed signal Y21 of Y11 is obtained.

The embodiments 1 to 3 in fig. 7, 8 and 9 are all delay detection circuits for the signal Y11 in the trigger strobe control value, and delay detection circuits for the other signals Y12 to Y1M in the trigger strobe control value, and the circuit structure and function of the delay detection circuit for the input signal Y11 in the corresponding embodiments are the same. The delay detection circuit may also adopt other circuits meeting the requirements to realize the functions thereof.

The function of the no-trigger area control signal generation module is to output a single pulse in the no-trigger area control signal when any one or more of the input edge detection signals for triggering the strobe control value generate a single pulse related to an edge. Fig. 10 shows an embodiment of the no-trigger area control signal generation module, in which a nor gate FY10 including M inputs performs corresponding functions, and the inputs of the nor gate FY10 are edge detection signals Y31-Y3M, and the output is a no-trigger area control signal P4. In the embodiment of fig. 10, the single pulse that does not trigger the output of the zone control signal is a negative pulse, i.e., the low level of the zone control signal is not active; when the nor gate FY10 is replaced by an or gate, the single pulse that does not trigger the zone control signal output is a positive pulse. If the single pulse associated with an edge generated in the input edge detection signals Y31-Y3M is a negative pulse, the nor gate FY10 in fig. 10 should be changed to a nand gate or an and gate to implement an or logic function under negative logic.

All gates in the delay protection unit are powered by a single power supply + VCC 1. Fig. 11 is a schematic diagram of a partial correlation waveform in the delay protection unit. From the principle and requirements of the sampling comparison unit, when the output trigger strobe control value is changed normally, 2 bits are changed every time. In fig. 11, Y11 in the trigger strobe control values has a rising edge change and a falling edge change respectively, and Y21 is the trigger strobe control value of Y11 delayed by T1 time; in embodiment 1 of the delay detection circuit in fig. 7, T1 is determined by the magnitude of the product of the resistor RY0 and the capacitor CY0 (i.e., the magnitude of the time constant); in embodiment 2 of the delay detection circuit in fig. 8, T1 is determined by the product of the resistor RY3 and the capacitor CY 3; in the embodiment 3 of the delay detection circuit in fig. 9, T1 is determined by the gate delay time of the inverters FY11, FY12, FY13 and FY 14. In fig. 11, the negative pulse width of the signal YP1 due to the rising edge of Y11 is T2; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T2 is determined by the magnitude of the product of the resistor RY1 and the capacitor CY 1; in embodiment 2 of the delay detection circuit in fig. 8, T2 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, the negative pulse width generated by the falling edge of Y11 in the signal YP2 is T3; in the delay detection circuit embodiment 1 of fig. 7 and the delay detection circuit embodiment 3 of fig. 9, T3 is determined by the magnitude of the product of the resistor RY2 and the capacitor CY 2; in embodiment 2 of the delay detection circuit in fig. 8, T3 is determined by the product of the resistor RY3 and the capacitor CY 3. In fig. 11, 2 positive pulses in the edge detection signal Y31 correspond to a negative pulse due to a rising edge of Y11 in the signal YP1 and a negative pulse due to a falling edge of Y11 in the signal YP2, respectively. When Y11 in the trigger gate control value in fig. 11 changes in rising edge, Y12 in the trigger gate control value changes in falling edge, and the corresponding edge detection signal Y32 generates a positive pulse correspondingly; when Y11 is changed by a falling edge, Y12 in the trigger gate control value is changed by a rising edge at the same time, and a positive pulse is correspondingly generated in the corresponding edge detection signal Y32; during this period, the other trigger gate control value signals except Y11 and Y12 are unchanged, and the edge detection signals corresponding to the other trigger gate control value signals except Y11 and Y12 are all at low level, which is not shown in fig. 11. According to the logical or function of the non-trigger area control signal generation module, the width of the single pulse output by the non-trigger area control signal generation module is the same as the widest pulse width of the input pulses in the input edge detection signals, and the width difference is caused by the difference between the resistance and capacitance values of T2 and T3 determined in the different delay detection circuits. In fig. 11, the 1 st positive pulse in Y31 is wider than the 1 st positive pulse in Y32, the 2 nd positive pulse in Y31 is narrower than the 2 nd positive pulse in Y32, the 1 st negative pulse width in the no-trigger-region control signal P4 coincides with the 1 st positive pulse width in the edge detection signal Y31, and the 2 nd negative pulse width in the no-trigger-region control signal P4 coincides with the 2 nd positive pulse width in the edge detection signal Y32.

In the embodiment 1 of the delay detection circuit of the delay protection unit in fig. 7, the delay time for the trigger gating control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY1 and FY4 and FY10 in fig. 10, or the sum of the delay times of the gates FY3 and FY4 and FY10 in fig. 10; the selection range of the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY0 and the capacitor CY0 is ms order of magnitude, obviously, is greater than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the no-trigger area control signal, that is, the time of the delay change of the trigger gate control value signal is later than the leading edge time of the single pulse output after the trigger gate control value changes. Strictly speaking, T1 actually includes the sum of the delay time caused by resistor RY0 and capacitor CY0, and the delay time of gate FY 0. In embodiment 1 of fig. 7, when selecting parameters, the value of T2 and the value of T3 are both greater than the value of T1, so that the time of delayed change of the trigger gate control value signal meets the requirement of earlier time of the trailing edge of a single pulse of the control signal of the non-trigger area output after the change of the trigger gate control value.

In the embodiment 2 of the delay detection circuit in the delay protection unit in fig. 8, the delay time for the trigger gate control value to change to the leading edge of the corresponding single pulse of the no-trigger area control signal is the sum of the delay times of the gates FY7 and FY9 and FY10 in fig. 10, or the sum of the delay times of the gates FY8 and FY9 and FY10 in fig. 10; t1 is a value of ms magnitude, and it is obvious that the signal delay time T1 of the trigger gate control value determined by the product of the resistor RY3 and the capacitor CY3 is longer than the delay time of the trigger gate control value changing to the leading edge of the corresponding single pulse of the non-trigger area control signal, i.e. the time of the trigger gate control value signal delay changing is later than the leading edge of the single pulse output after the trigger gate control value changing. In the embodiment 2 of the delay detection circuit in fig. 8, both the time when the trigger gate control value signal changes in delay and the time when the trailing edge of the output single pulse after the trigger gate control value changes are affected by the change of the signal YP 0; the time when the delay of the trigger gating control value signal changes is the delay of the gate circuit FY6 after the signal YP0 changes; the trailing edge time of the single pulse output after the trigger gating control value is the sum of the delay time of the gate circuits FY7 and FY9 after the signal YP0 is changed and FY10 in the graph 10, or the sum of the delay time of the gate circuits FY8 and FY9 after the signal YP0 is changed and FY10 in the graph 10; obviously, the time of the delayed change of the trigger gating control value signal is less than the time of the back edge of the output single pulse after the change of the trigger gating control value by 2 gate circuits, and the requirement that the time of the delayed change of the trigger gating control value signal is earlier than the time of the back edge of the output single pulse after the change of the trigger gating control value is met.

Fig. 12 is a schematic diagram of an embodiment of a trigger circuit for triggering the compensated main circuit 1 in fig. 2 in a trigger unit or triggering the triac SR1 in the compensated main circuit 2 in fig. 3, the trigger circuit is composed of an ac trigger optocoupler UG1, a resistor RG1, and a resistor RG2, and a trigger control signal P51 is active at a low level. The alternating current trigger optocoupler UG1 can be selected from phase-shifting bidirectional thyristor output optocouplers such as MOC3022, MOC3023, MOC3052 and MOC 3053. Power supply + VCCK is the controlled power supply controlled by the protected drive unit. The circuit structure of the trigger circuit for triggering the triacs SR2-SR6 in the compensated main circuit embodiment 1 in FIG. 2 or the triacs SR2-SR8 in the compensated main circuit embodiment 2 in FIG. 3 is the same as that of the triac SR 1. The trigger pulses output by the alternating current trigger optocoupler UG1 in fig. 12 from G11 and G12 and the trigger pulses output by other alternating current trigger optocouplers in the trigger unit jointly form a trigger signal P6.

Fig. 13 is embodiment 1 of a trigger gating control unit, and compensation control is performed on embodiment 1 of the compensation type main circuit of fig. 2; in FIG. 2, the compensation voltage of TB1 is low, the compensation voltage of TB2 is high, the fluctuation range of the AC power supply voltage is 220V +/-10%, and the output is required to be stabilized within the range of 220V +/-2%. In fig. 13, the trigger gate control values Y21-Y27 inputted by the trigger gate control unit are active at high level, 21 diodes D11-D73, trigger gate control column lines Y21-Y27, and trigger drive row lines VK1-VK6 form a diode trigger gate matrix, resistors RS1-RS6 and triodes VS1-VS6 form a drive circuit of trigger control signals P51-P56, and at this time, P51-P56 form a trigger control signal P5.

Table 1 is a trigger gating control function table of the trigger gating control unit in embodiment 1, and lists 7 valid bits in 7 trigger gating control values, that is, on-off combination states of a triac in a thyristor bridge corresponding to the 7 valid trigger gating control values. The 7 effective trigger gating control values correspond to the voltage level interval 1-7, and the trigger gating control unit controls the on-off state of the bidirectional thyristor in the compensation type main circuit embodiment 1 according to the trigger gating control values to perform corresponding voltage compensation; in table 1, 1 represents that the corresponding triac needs to be in the on state, and 0 represents that the corresponding triac is in the off state.

The diode-triggered gating matrix of FIG. 13 is functionally connected as required in Table 1, controlled by the trigger gating control values Y21-Y27; when a certain trigger gating control column line is effective, the diode enables a signal of the trigger driving column line which needs to be conducted with the bidirectional thyristor to be effective. For example, when the input voltage is at the lowest voltage level 1, that is, Y21 is at a high level, diodes D11, D12, and D13 in the trigger gating matrix are turned on, transistors VS1, VS4, and VS6 are controlled to be turned on to trigger and drive row lines VK1, VK4, and VK6 to be at a high level, respectively, so that P51, P54, and P56 effectively turn on the triacs SR1, SR4, and SR6, and other diodes in the trigger gating matrix are turned off to control and turn off the triacs SR2, SR3, and SR5, so that TB1 and TB2 are both forward-compensated; when the input voltage is in a voltage class 2, namely Y22 is effectively in a high level, diodes D21, D22 and D23 in the trigger gating matrix are switched on, triodes VS1, VS3 and VS6 are respectively controlled to be switched on to trigger and drive row lines VK1, VK3 and VK6 to be in a high level, so that the P51, P53 and P56 effectively turn on the bidirectional thyristors SR1, SR3 and SR6, other diodes in the trigger gating matrix are switched off, the bidirectional thyristors SR2, SR4 and SR5 are controlled to be switched off, and only TB2 is subjected to forward compensation; when the input voltage is in a voltage level of 4, namely Y24 is effectively in a high level, diodes D41, D42 and D43 in the trigger gating matrix are switched on, transistors VS1, VS3 and VS5 are respectively controlled to be switched on by triggering and driving row lines VK1, VK3 and VK5 to be in a high level, so that the P51, P53 and P55 effectively turn on the bidirectional thyristors SR1, SR3 and SR5, other diodes in the trigger gating matrix are switched off, the bidirectional thyristors SR2, SR4 and SR6 are controlled to be switched off, and 0 voltage compensation is realized, namely both TB1 and TB2 are not compensated; when the input voltage is at voltage level 5, namely Y25 is effectively at high level, diodes D51, D52 and D53 in the trigger gating matrix are switched on, triodes VS2, VS3 and VS6 are respectively controlled to be switched on to enable P52, P53 and P56 to effectively turn on the bidirectional thyristors SR2, SR3 and SR6 when trigger driving row lines VK2, VK3 and VK6 to be at high level, other diodes in the trigger gating matrix are switched off to control the bidirectional thyristors SR1, SR4 and SR5 to be switched off, and only TB1 is subjected to reverse compensation; when the input voltage is in a voltage level of 7, namely Y27 is effectively in a high level, diodes D71, D72 and D73 in the trigger gating matrix are switched on, triodes VS2, VS3 and VS5 are respectively controlled to be switched on by triggering and driving row lines VK2, VK3 and VK5 to be in a high level, so that the P52, P53 and P55 effectively turn on the bidirectional thyristors SR2, SR3 and SR5, other diodes in the trigger gating matrix are switched off, and the bidirectional thyristors SR1, SR4, SR6, TB1 and TB2 are controlled to be switched off; and so on.

TABLE 1

Fig. 14 is embodiment 2 of a trigger gating control unit, and compensation control is performed on embodiment 1 of the compensation type main circuit in fig. 2; in FIG. 2, the compensation voltage of TB1 is low, the compensation voltage of TB2 is high, and the compensation voltage of TB2 is 2 times of the compensation voltage of TB 1; the fluctuation range of the alternating current power supply voltage is 220V +/-10%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. In fig. 14, the trigger gate control values Y21-Y27 inputted by the trigger gate control unit are active at low level, 21 diodes D11-D73, the trigger gate control column lines Y21-Y27 and the trigger drive row lines P51-P56 form a diode trigger gate matrix, and the trigger gate matrix directly outputs active low level trigger control signals P51-P56. In this embodiment 2, there is no driving circuit for triggering the control signals P51-P56.

The diode-triggered gating matrix of FIG. 14 is functionally connected as required in Table 1, controlled by the trigger gating control values Y21-Y27; for example, when the input voltage is at the lowest voltage level 1, that is, Y21 is active low, diodes D11, D12 and D13 in the gating matrix are triggered to be turned on, so that P51, P54 and P56 become active low levels to turn on the triacs SR1, SR4 and SR6, and other diodes in the gating matrix are triggered to be turned off, so that the triacs SR2, SR3 and SR5 are controlled to be turned off, and the triacs TB1 and TB2 are all compensated in the forward direction; when the input voltage is in a voltage class 2, namely Y22 is in an effective low level, diodes D21, D22 and D23 in the gating matrix are triggered to be switched on, P51, P53 and P56 are enabled to be in an effective low level to switch on the bidirectional thyristors SR1, SR3 and SR6 respectively, other diodes in the gating matrix are triggered to be switched off, the bidirectional thyristors SR2, SR4 and SR5 are controlled to be switched off, and only TB2 is enabled to perform forward compensation; when the input voltage is in a voltage level of 4, namely Y24 is effectively in a low level, diodes D41, D42 and D43 in the gating matrix are triggered to be switched on, P51, P53 and P55 are enabled to become effective low levels to switch on the bidirectional thyristors SR1, SR3 and SR5 respectively, other diodes in the gating matrix are triggered to be switched off, the bidirectional thyristors SR2, SR4 and SR6 are controlled to be switched off, and 0 voltage compensation is achieved, namely TB1 and TB2 are not compensated; when the input voltage is in a voltage level 5, namely Y25 is effectively in a low level, diodes D51, D52 and D53 in the gating matrix are triggered to be switched on, P52, P53 and P56 are enabled to be in an effective low level to switch on the bidirectional thyristors SR2, SR3 and SR6 respectively, other diodes in the gating matrix are triggered to be switched off, the bidirectional thyristors SR1, SR4 and SR5 are controlled to be switched off, and only TB1 is subjected to reverse compensation; when the input voltage is in a voltage level of 7, namely Y27 is effectively in a low level, diodes D71, D72 and D73 in the gating matrix are triggered to be switched on, P52, P53 and P55 are enabled to be in an effective low level to switch on the bidirectional thyristors SR2, SR3 and SR5 respectively, other diodes in the gating matrix are triggered to be switched off, and the bidirectional thyristors SR1, SR4, SR6, TB1 and TB2 are controlled to be switched off to perform reverse compensation; and so on.

In fig. 14, the low level in the trigger gating control values Y21-Y27 needs to directly drive the light emitting diodes at the input ends of the three ac trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 30mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, 15mA of driving current is needed.

Fig. 15 is embodiment 3 of a trigger gating control unit, and compensation control is performed on embodiment 2 of the compensation type main circuit of fig. 3; in FIG. 3, TB1 has the lowest compensation voltage, and TB3 has the highest compensation voltage; and the compensation voltage of TB2 is 2 times of the compensation voltage of TB1, and the compensation voltage of TB3 is 2 times of the compensation voltage of TB 2. The fluctuation range of the alternating current power supply voltage is 220V + 10% to 220V-20%, and the alternating current power supply voltage is required to be stabilized within the range of 220V +/-2% for output. In fig. 15, the trigger gate control values Y21-Y210 input by the trigger gate control unit are active at high level, 40 diodes D01-D94, trigger gate control column lines Y21-Y210, and trigger drive row lines VK1-VK8 form a diode trigger gate matrix, resistors RS1-RS8 and transistors VS1-VS8 form a drive circuit of trigger control signals P51-P58, and at this time, the trigger control signals P5 are formed by P51-P58.

Table 2 is a trigger gating control function table of the trigger gating control unit in embodiment 3, and lists 10 valid bits in the 10-bit trigger gating control value, that is, the on-off combination state of the triac in the thyristor bridge corresponding to the 10 valid trigger gating control values. The 10 effective trigger gating control values correspond to the voltage levels of 1-10, and the trigger gating control unit controls the on-off state of the bidirectional thyristor in the compensation type main circuit embodiment 2 according to the trigger gating control values to perform corresponding voltage compensation; in table 2, 1 represents that the corresponding triac needs to be in the on state, and 0 represents that the corresponding triac needs to be in the off state. The diode triggered gating matrix of fig. 15 is functionally connected as required in table 2, controlled by triggered gating control values Y21-Y210; for example, when the input voltage is at voltage level 7, that is, Y27 is active at high level, diodes D71, D72, D73, and D74 in the trigger gating matrix are turned on, and trigger driving row lines VK1, VK3, VK5, and VK7 are at high level to control transistors VS1, VS3, VS5, and VS7 to be turned on respectively, so that P51, P53, P55, and P57 effectively turn on triacs SR1, SR3, SR5, and SR7, and other diodes in the trigger gating matrix are turned off to turn off triacs SR2, SR4, SR6, and SR8, thereby implementing 0-voltage compensation, that is, none of TB1, TB2, and TB3 is compensated; when the input voltage is at a voltage level of 8, that is, Y28 is effectively at a high level, diodes D81, D82, D83, and D84 in the trigger gating matrix are turned on, and trigger driving row lines VK2, VK3, VK6, and VK8 are at a high level to respectively control transistors VS2, VS3, VS6, and VS8 to be turned on so that P52, P53, P56, and P58 effectively turn on bidirectional thyristors SR2, SR3, SR6, and SR8, and trigger other diodes in the gating matrix to be turned off, turn off bidirectional thyristors SR1, SR4, SR5, and SR7, so that TB1 performs reverse compensation; when the input voltage is in a voltage level 9, namely Y29 is effectively in a high level, diodes D91, D92, D93 and D94 in the trigger gating matrix are switched on, and trigger driving row lines VK2, VK4, VK5 and VK8 are in a high level to respectively control triodes VS2, VS4, VS5 and VS8 to be switched on so as to effectively turn on P52, P54, P55 and P58 to turn on bidirectional thyristors SR2, SR4, SR5 and SR8, and other diodes in the trigger gating matrix are switched off to turn off bidirectional thyristors SR1, SR3, SR6 and SR7 so as to perform reverse compensation on TB 2; when the input voltage is at voltage level 10, that is, Y210 is active high, diodes D01, D02, D03 and D04 in the trigger gating matrix are turned on, transistors VS2, VS3, VS5 and VS8 are controlled to be turned on respectively by triggering and driving row lines VK2, VK3, VK5 and VK8 to be high, so that P52, P53, P55 and P58 effectively turn on bidirectional thyristors SR2, SR3, SR5 and SR8, and other diodes in the trigger gating matrix are turned off, turn off bidirectional thyristors SR1, SR4, SR6 and SR7, and reverse compensation is performed simultaneously by TB1 and TB 2.

TABLE 2

For another example, when the input voltage is at voltage level 6, that is, Y26 is active at high level, diodes D61, D62, D63 and D64 in the trigger gating matrix are turned on, and trigger driving row lines VK1, VK4, VK5 and VK7 are high level to control transistors VS1, VS4, VS5 and VS7 to be turned on respectively, so that P51, P54, P55 and P57 effectively turn on triacs SR1, SR4, SR5 and SR7, and trigger other diodes in the gating matrix to be turned off, so that triacs SR2, SR3, SR6 and SR8 are turned off, and TB1 performs forward compensation; when the input voltage is in a voltage level 4, that is, Y24 is at a high level, diodes D41, D42, D43 and D44 in the trigger gating matrix are turned on, and trigger driving row lines VK1, VK4, VK6 and VK7 are at a high level to respectively control triodes VS1, VS4, VS6 and VS7 to be turned on so that P51, P54, P56 and P57 effectively turn on bidirectional thyristors SR1, SR4, SR6 and SR7, and other diodes in the trigger gating matrix are turned off to turn off the bidirectional thyristors SR2, SR3, SR5 and SR8, so that TB1 and TB2 perform forward compensation at the same time; when the input voltage is in a voltage level 3, that is, Y23 is effectively at a high level, diodes D31, D32, D33, and D34 in the trigger gating matrix are turned on, and trigger driving row lines VK1, VK3, VK5, and VK8 are at a high level to respectively control transistors VS1, VS3, VS5, and VS8 to be turned on so that P51, P53, P55, and P58 effectively turn on bidirectional thyristors SR1, SR3, SR5, and SR8, and trigger other diodes in the gating matrix to be turned off, turn off bidirectional thyristors SR2, SR4, SR6, and SR7, so that TB3 performs forward compensation; when the input voltage is at voltage level 1, that is, Y21 is at a high level, diodes D11, D12, D13 and D14 in the trigger gating matrix are turned on, and trigger driving row lines VK1, VK3, VK6 and VK8 are at a high level to control transistors VS1, VS3, VS6 and VS8 to be turned on respectively, so that P51, P53, P56 and P58 effectively turn on bidirectional thyristors SR1, SR3, SR6 and SR8, and other diodes in the trigger gating matrix are turned off, so that the bidirectional thyristors SR2, SR4, SR5 and SR7 are turned off, and TB2 and TB3 perform forward compensation at the same time; and so on.

When the trigger gate control values Y21-Y210 in table 2 are active at low level, the trigger gate matrix is composed of 40 diodes D01-D94, trigger gate control column lines Y21-Y210, and trigger control row lines P51-P58, and the trigger gate matrix directly outputs the active low level trigger control signals P51-P58, according to the method of embodiment 2 of the trigger gate control unit in fig. 14. At this time, the low level in the trigger gating control value Y21-Y210 needs to directly drive the input end light emitting diodes of the four alternating current trigger optocouplers to emit light; when the alternating current trigger optocoupler selects MOC3022, MOC3052 and the like, a driving current of 40mA is needed; when the alternating current trigger optocoupler selects MOC3023, MOC3053 and the like, a driving current of 20mA is required.

FIG. 16 is a diagram of an embodiment of an error detection and determination unit, which determines the trigger strobe control value P3, i.e. the high-level valid 10-bit trigger strobe control values Y21-Y210, and outputs a trigger strobe control value determination signal P7 with valid high level and invalid low level; that is, the output P7 is 1, indicating that the trigger strobe control value is valid; the output P7 is 0 indicating that the trigger strobe control value is invalid. In fig. 16, the FD3 is a ROM memory having a 10-bit address input and a 1-bit data output, 10-bit trigger strobe control values Y21-Y210 are connected to the 10-bit address inputs a0-a9, respectively, and a trigger strobe control value decision signal P7 is output from the data output terminal D0. Table 3 is a logic truth table of the error detection and determination unit, and is also a data table of the contents of the ROM memory in fig. 16.

TABLE 3

The function of the error detection judging unit is to enable the output trigger gating control value judging signal P7 to be effective when judging that only one of M bits of the trigger gating control value is effective, or to enable the output trigger gating control value judging signal P7 to be ineffective; that is, when not only one of the M bits of the trigger strobe control value is valid, or when no one of the M bits of the trigger strobe control value is valid, the output trigger strobe control value determination signal P7 is invalidated. The contents of the ROM memory cell of fig. 16 are written according to the data of table 3, where 10-bit toggle strobe control values Y21-Y210 are all active high and inactive low in table 3; the output trigger gating control value judges whether the signal P7 is effective at high level or ineffective at low level; when only 1 of the input signals Y21-Y210 is 1, the output P7 is 1; with Y21-Y210 being other inputs, the output P7 is 0.

If the input 10-bit trigger strobe control values Y21-Y210 are all active at low level and inactive at high level, all 0's of the address contents of the first 10 rows input in table 3 are changed to 1's and all 1's are changed to 0's. If the trigger strobe control value determination signal P7 to be output is active at low level and inactive at high level, all 0's in the last 1 column of data in table 3 are changed to 1's and all 1's in the last 1 column of data are changed to 0's.

When the error detection judging unit needs to judge the other-digit trigger strobe control value P3, the same ROM memory can be used. The trigger strobe control value P3 input in table 4 has 7 bits, and is all active at high level and inactive at low level; the output trigger strobe control value discrimination signal P7 is active at high level and inactive at low level. With a ROM memory having a 7-bit address input and a 1-bit data output, 10-bit trigger strobe control values Y21-Y27 are connected to the 7-bit address inputs a0-a6, respectively, and a trigger strobe control value decision signal P7 is output from a data output terminal D0; the contents of the ROM memory storage location are written in accordance with the contents of table 4.

TABLE 4

The logic function of the error detection decision unit can also be implemented in other ways, for example, tables 3 and 4 are logic truth tables, and the function can be implemented by combining with or not logic gate. The ROM memory in the error detection judging unit or the logic gate is used for realizing the function, and the single power supply + VCC1 is used for supplying power.

FIG. 17 shows an embodiment of the protection driving unit, wherein the high level of the input trigger gate control value determining signal P7 is asserted, i.e. P7 is 1 to indicate that the trigger gate control value is asserted; the P7 is inactive low, i.e., P7 is 0, indicating that the trigger strobe control value is inactive. The low level of an input control signal P4 of the non-trigger area is effective, namely when P4 is equal to 0, the fact that the alternating current power supply voltage fluctuates indicates that the trigger gating control value changes needs to be switched on and off states of a bidirectional thyristor in a thyristor bridge, and a compensation mode is changed; in the switching process, in order to avoid the power supply short circuit caused by the factor of delayed turn-off of the bidirectional thyristor when the upper and lower bridge arms in the thyristor bridge are switched, all the bidirectional thyristors in the thyristor bridge are turned off during the period when the control signal of the trigger zone is not valid, i.e., when P4 in the embodiment is equal to 0.

In fig. 17, a transistor VT, a relay coil KA, a freewheeling diode VD, and a resistor RK1 form a protection control circuit, a transistor VK1, a transistor VK2, a resistor RK2, a resistor RK3, and an and gate FY21 form a trigger unit controlled power control circuit, and the and gate FY21 is powered by a single power supply + VCC 1. The + VCC2 is the power supply for the relay coil and the source supply for the controlled power supply + VCCK in the trigger unit. When the input trigger gating control value judging signal P7 is at a low level, namely the trigger gating control value is invalid, the AND gate FY21 outputs a low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not have a power supply and does not work, namely, the trigger unit does not send out trigger pulses for triggering the bidirectional thyristor; p7 is a low level and simultaneously controls the cutoff of the triode VT, the relay coil KA loses power, so that the normally open switches KA-1, KA-2 and KA-3 of the relay in the embodiment 1 of the compensation type main circuit in the figure 2 are disconnected, or the normally open switches KA-1, KA-2, KA-3 and KA-4 of the relay in the embodiment 2 of the compensation type main circuit in the figure 3 are disconnected, and the open circuit protection of the thyristor bridge is realized; the control is performed such that the normally closed relay switches KA-5 and KA-6 in the compensation main circuit example 1 of fig. 2 are closed to set the voltage applied to the exciting coil TB1 and TB2 to 0, or the control is performed such that the normally closed relay switches KA-5, KA-6 and KA-7 in the compensation main circuit example 2 of fig. 3 are closed to set the voltage applied to the exciting coil TB1, TB2 and TB3 to 0. When the sampling comparison unit fails to cause the trigger gating control value to be invalid, or the input alternating current power supply voltage is lower than the minimum voltage level interval range to cause the output trigger gating control value to be invalid, the protection driving unit cuts off the power supply of the trigger unit no matter whether the input non-trigger area control signal P4 is valid or not, stops sending out trigger pulses of all the bidirectional thyristors, and simultaneously controls to cut off all bridge arms of the thyristor bridge to realize open-circuit protection of the thyristor bridge. When the input trigger gating control value judging signal P7 is at a high level, that is, the trigger gating control value is valid, the control triode VT is turned on, and the relay coil KA is powered on, so that the normally open switches KA-1, KA-2, KA-3 of the relay in the compensation main circuit embodiment 1 in fig. 2 are closed, and the normally closed switches KA-5, KA-6 of the relay are opened, or the normally open switches KA-1, KA-2, KA-3, KA-4 of the relay in the compensation main circuit embodiment 2 in fig. 3 are closed, and the normally closed switches KA-5, KA-6, KA-7 of the relay are opened, and the thyristor bridge is in a compensation working state. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is valid, namely P4 is equal to 0, the AND gate FY21 outputs low level, the triodes VK1 and VK2 are cut off, the controlled power supply + VCCK loses power, the trigger unit does not work, namely, the trigger pulse for triggering the bidirectional thyristor is not sent out, all the bidirectional thyristors in the thyristor bridge are cut off, the alternating-current power supply voltage is fluctuated at the moment, the trigger gating control value is changed, the electronic switch needs to be switched, and the compensation mode is changed. When the trigger gating control value is valid, namely P7 is 1, and the control signal of the non-trigger area is invalid, namely P4 is equal to 1, the AND gate FY21 outputs high level, the triodes VK1 and VK2 are both conducted, the controlled power supply + VCCK is electrified, the trigger unit normally works, the trigger gating control unit selects the corresponding trigger control signal to be valid according to the valid trigger gating control value corresponding to a certain voltage grade interval, the trigger unit sends out trigger pulse to control the on-off state of the bidirectional thyristor in the thyristor bridge, and the main circuit is in a compensation working state corresponding to the voltage grade interval.

When the error detection judging unit judges that the input trigger gating control value is invalid, the protection driving unit sends a protection control signal to the main circuit, so that the thyristor bridge is in an open circuit protection state, the alternating current voltage stabilizer does not compensate the input voltage, and the voltage output by the voltage stabilizer is the input alternating current power supply voltage. When the thyristor bridge is in the open-circuit protection state, if the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit automatically stops the open-circuit protection state of the thyristor bridge, and the thyristor bridge is in the compensation working state again.

As can be known from the above embodiments and the working process thereof, when the input is an effective trigger gating control value, the trigger gating control unit ensures that the bidirectional thyristors of the upper and lower bridge arms of the same full-bridge circuit are not simultaneously conducted, that is, the interlocking control of the bidirectional thyristors of the upper and lower bridge arms of the same full-bridge circuit is realized; when the trigger gating control value is invalid, the protection driving unit simultaneously disconnects all bridge arms of the thyristor bridge on the basis of rapidly cutting off the power supply of the trigger unit and avoiding short circuit caused by error conduction of the bidirectional thyristor, so that the thyristor bridge is in an open-circuit protection state. When the thyristor bridge is in the open-circuit protection state, if the error detection judging unit judges that the alternating-current voltage stabilizer enters the normal logic control state again, namely the error detection judging unit judges that the input trigger gating control value is recovered to be an effective signal, the protection driving unit can automatically stop the open-circuit protection state of the thyristor bridge and enable the thyristor bridge to be in the compensation working state again. The function effectively strengthens the protection strength of the alternating current voltage stabilizer against the abnormity of the working process, so that the working process of the alternating current voltage stabilization control method is more reliable.

Besides the technical features described in the specification, other techniques of the ac voltage stabilization control method are conventional techniques that are known to those skilled in the art.

Claims

1. An alternating current voltage stabilization control method is characterized in that: dividing the voltage in the alternating current power supply voltage fluctuation interval range into a plurality of voltage grade intervals for compensation control; identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value; triggering a gating control value to control the on-off combination state of a thyristor in a thyristor bridge; controlling and selecting 0 of a plurality of compensation transformers or at least 1 compensation transformer to perform voltage compensation by the on-off combination state of the thyristors in the thyristor bridge, so as to realize a voltage compensation state corresponding to a voltage grade interval; each voltage grade interval of the alternating current power supply voltage corresponds to a voltage compensation state;

judging whether the delayed trigger gating control value is effective or not by an error detection judging unit which is a logic circuit; when the trigger gating control value is invalid, the protection control circuit controls the thyristor bridge to be in an open-circuit protection state; the delay protection unit inputs a trigger gating control value and outputs the delayed trigger gating control value;

trigger gating control value ofMA bit binary value; the criterion for judging whether the trigger gating control value is valid is thatMIf one and only one bit in the binary bit values is valid, the gating control value is triggered to be valid; otherwise, triggering the gating control value to be invalid; the above-mentionedMIs an integer of 2 or more;

identifying the voltage grade interval of the alternating-current power supply voltage to obtain a trigger gating control value, wherein the trigger gating control value is realized by a sampling comparison unit; the sampling comparison unit comprises an alternating current power supply voltage sampling circuit and a multi-interval voltage comparator circuit, wherein the alternating current power supply voltage sampling circuit converts an effective value of alternating current power supply voltage into a sampling value of the alternating current power supply voltage; sampling value of multi-interval voltage comparator circuit to AC power supply voltage andM-1 threshold voltage is compared to obtainMA bit triggered gating control value;

the method for controlling the on-off combination state of the thyristors in the thyristor bridge by the trigger gating control value comprises the following steps that the trigger gating control unit triggers the gating matrix selection through the diodes according to the trigger gating control value, enables the corresponding trigger control signals to be effective and controls the on-off combination state of the thyristors in the thyristor bridge;

in the thyristor bridgeNA plurality of thyristors; the diode triggered gating matrix comprisesMA root trigger gating control column line,NRoot triggeringDriving the row lines and the plurality of diodes;Mroot-triggered strobe control column line andMthe bit trigger gating control values correspond to one another, and one trigger gating control value correspondingly enables one trigger gating control column line signal to be effective; the N trigger driving row lines correspond to the N thyristors one by one, and the effective correspondence of a trigger driving row line signal enables a trigger control signal of one thyristor to be effective; the above-mentionedNIs an integer of 4 or more;

2. The ac voltage stabilization control method according to claim 1, characterized in that: a multi-interval voltage comparator circuit includesM-1 number of comparators to be compared,M-1 comparator is powered by a positive single power supply;M-1 different threshold voltages are connected toM-1 non-inverting input of comparators with simultaneous connection of sampled values of the AC supply voltageM-1 inverting input of a comparator;Mamong the 1 comparators, the comparator with the lowest threshold voltage is directly powered by a positive single power supply, and the other comparators are powered by controllable power supplies; when the comparator is powered by a controllable power supply, the controllable power supply supplies power to the positive power supply end of the comparator only when all the comparators with the threshold voltages lower than the threshold voltages output low levels, otherwise, the controllable power supply stops supplying power to the positive power supply end of the comparator; the comparator adopts a controllable power supply to supply power, and outputs a low level when the controllable power supply stops supplying power to the positive power supply end;Mbit-triggered gating control valueM-1 comparator output value and highest interval decision value; when in useM-when all of the output values of the 1 comparators are at low level, the highest interval judgment value is at high level, otherwise, the highest interval judgment value is at low level.

3. The ac voltage stabilization control method according to claim 1, characterized in that: when the trigger gating control value changes and the thyristors in the thyristor bridge need to be switched to be in different on-off combination states, maintaining a non-trigger area time between the 2 on-off combination states, and turning off all the thyristors in the thyristor bridge.

4. The ac voltage stabilization control method according to claim 3, characterized in that: the maintaining of the one non-trigger area time is realized by a non-trigger area control signal; controlling the control signal of the non-trigger area to output a single pulse after the trigger gating control value is changed; the control signal of the non-trigger area is effective in the period of outputting the single pulse and is ineffective in the period of not outputting the single pulse; and when the control signal of the non-trigger area is effective, maintaining a time of the non-trigger area.

5. The ac voltage stabilization control method according to claim 4, characterized in that: the trigger control signal for controlling the thyristor bridge is generated by the delayed trigger gating control value; the delayed signal change time of the trigger gating control value is later than the leading edge time of a single pulse in the non-trigger area control signal after the trigger gating control value is changed and earlier than the trailing edge time of the single pulse in the non-trigger area control signal after the trigger gating control value is changed.