CN109165177A - A kind of communication means and relevant apparatus of PCIE interface - Google Patents
A kind of communication means and relevant apparatus of PCIE interface Download PDFInfo
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- CN109165177A CN109165177A CN201811108504.XA CN201811108504A CN109165177A CN 109165177 A CN109165177 A CN 109165177A CN 201811108504 A CN201811108504 A CN 201811108504A CN 109165177 A CN109165177 A CN 109165177A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
This application discloses a kind of communication means of PCIE interface, comprising: the data packet that PCIE interface arrangement sends AVALON-ST bus is decoded processing, obtains command packet；Judge whether the command packet matches with flash controller according to the register identification in the command packet；If so, determining corresponding PCIE format conversion operation according to the type of the command packet, the PCIE format conversion operation is executed, the transformation result is sent to flash controller.By being decoded processing to data packet, flash controller matching and format conversion processing obtain flash memory and control readable data, flash controller is attached by realization by PCIE interface, improves the speed of data transmission, and ensure that the reliability of data transmission.Disclosed herein as well is a kind of PCIE interface arrangement, device and computer readable storage mediums, have the above beneficial effect.
Description
Technical field
This application involves field of computer technology, in particular to a kind of communication means of PCIE interface, PCIE interface arrangement,
Device and computer readable storage medium.
Background technique
With the development of information technology, the data volume stored in internet has also obtained considerable growth, so that depositing
Storage system is constantly regenerated upgrading.Especially using flash memory as the storage system of medium, advantage in terms of capacity and cost is obtained
It is widely applied.
But in the prior art due to using SATA/SAS interface to remove connection flash memory, due to the limitation of interface rate itself,
So that the bandwidth of interface is unable to get good release, the rate of data transmission is limited, is unable to satisfy flash memory for read-write speed
The requirement of degree reduces the efficiency of transmission of flash memory, also reduces the utilization rate of flash memory.
Therefore, the Important Problems that the bandwidth for transmission rate of interface is those skilled in the art's concern how to be improved.
Summary of the invention
The core that the purpose of the application is to provide the application is to provide a kind of communication means of PCIE interface, PCIE interface dress
It sets, device and computer readable storage medium, by being decoded processing, flash controller matching and format to data packet
Conversion process obtains flash memory and controls readable data, and flash controller is attached by realization by PCIE interface, improves number
According to the speed of transmission, and it ensure that the reliability of data transmission.
In order to solve the above technical problems, the application provides a kind of communication means of PCIE interface, comprising:
The data packet that PCIE interface arrangement sends AVALON-ST bus is decoded processing, obtains command packet；
According to the register identification in the command packet judge the command packet whether with flash controller
Match；
If so, corresponding PCIE format conversion operation is determined according to the type of the command packet, described in execution
The transformation result is sent to flash controller by PCIE format conversion operation.
Optionally, further includes:
When the command packet and the flash controller mismatch, the command packet is deleted.
Optionally, the data packet that PCIE interface arrangement sends AVALON-ST bus is decoded processing, obtains command number
According to packet, comprising:
The data packet is stored in corresponding caching by the PCIE interface arrangement, carries out the school CRC to the data packet
Test processing；
When CRC check processing passes through, processing is decoded to the data packet according to AVALON-ST bus protocol
Obtain the command packet.
Optionally, corresponding PCIE format conversion operation is determined according to the type of the command packet, described in execution
The transformation result is sent to flash controller by PCIE format conversion operation, comprising:
When the type of the command packet is to write type, the command packet is carried out at configuration information decoding
Reason, obtains configuration information, carries out data acquisition process to the command packet according to the configuration information, obtains data；
Processing is formatted to the configuration information according to the write request format of the flash controller, obtains writing and ask
It asks；
Bit width conversion processing is carried out to the data according to the data bit width of the flash controller, obtains data to be written；
The write request and the data to be written are sent to the flash controller.
Optionally, corresponding PCIE format conversion operation is determined according to the type of the command packet, described in execution
The transformation result is sent to flash controller by PCIE format conversion operation, comprising:
When the type of the command packet is to read type, the command packet is carried out at configuration information decoding
Reason, obtains configuration information；
Processing is formatted to the configuration information according to the read request format of the flash controller, obtains reading to ask
It asks；
The read request is sent to the flash controller.
Optionally, further includes:
When the PCIE interface arrangement receives returned data, the returned data is carried out according to PCIE configuration information
Format conversion processing obtains return command data packet；
Coded treatment is carried out to the return command data packet according to AVALON-ST bus protocol, obtains returned data packet；
The returned data packet is sent to the main side PCIE device.
The application also provides a kind of PCIE interface arrangement, comprising:
Decoded packet data module, the data packet for sending to AVALON-ST bus are decoded processing, obtain command number
According to packet；
Register mapping module, for judge the register identification in the data packet whether the deposit with flash controller
Device matching；
Data packet format conversion module, for working as the register mapping of the register identification and the flash controller
When, corresponding PCIE format conversion operation is determined according to the type of the command packet, executes the PCIE format conversion behaviour
Make, the transformation result is sent to flash controller.
Optionally, the decoded packet data module, comprising:
Verification unit carries out at CRC check the data packet for the data packet to be stored in corresponding caching
Reason；
Decoding unit, for when the CRC check processing pass through when, according to AVALON-ST bus protocol to the data
Packet is decoded processing and obtains the command packet.
The application also provides a kind of device, comprising:
Memory, for storing computer program；
Processor, the step of communication means as described above is realized when for executing the computer program.
The application also provides a kind of computer readable storage medium, and calculating is stored on the computer readable storage medium
The step of machine program, the computer program realizes communication means as described above when being executed by processor.
The communication means of a kind of PCIE interface provided herein, comprising: PCIE interface arrangement is to AVALON-ST bus
The data packet of transmission is decoded processing, obtains command packet；According to the register identification judgement in the command packet
Whether the command packet matches with flash controller；If so, being determined according to the type of the command packet corresponding
PCIE format conversion operation, executes the PCIE format conversion operation, and the transformation result is sent to flash controller.
By the way that data packet is decoded processing, the command number that can be parsed to data content and data format is obtained
According to packet, then judge whether the order data matches with flash controller, upon a match, to the order and data in command packet
The conversion of PCIE format is carried out, command packet is converted to the format of flash controller from PCIE format, to meet flash memory control
The call format of device, is finally sent to flash controller for transformation result, realize by flash controller by PCIE interface into
Row connection, improves the speed of data transmission, and ensure that the reliability of data transmission.
The application also provides a kind of PCIE interface arrangement, device and computer readable storage medium, has above beneficial
Effect, this will not be repeated here.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of flow chart of the communication means of PCIE interface provided by the embodiment of the present application；
Fig. 2 is the flow chart for writing type format conversion operation in communication means provided by the embodiment of the present application；
Fig. 3 is the flow chart of the reading type format conversion operation in communication means provided by the embodiment of the present application；
Fig. 4 is the flow chart of the returned data processing method in communication means provided by the embodiment of the present application；
Fig. 5 is a kind of structural schematic diagram of PCIE interface arrangement provided by the embodiment of the present application.
Specific embodiment
The core of the application is to provide communication means, PCIE interface arrangement, device and the computer of a kind of PCIE interface
Readable storage medium storing program for executing, by being decoded processing to data packet, flash controller matching and format conversion processing obtain flash memory
Readable data are controlled, flash controller is attached by realization by PCIE interface, the speed of data transmission is improved, and
It ensure that the reliability of data transmission.
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall in the protection scope of this application.
In the prior art due to using SATA/SAS interface to go connection flash memory, and the limitation of interface itself rate, so that connecing
The bandwidth of mouth is unable to get good release, limits the rate of data transmission, is unable to satisfy flash memory and read or write speed is wanted
It asks, reduces the efficiency of transmission of flash memory, also reduce the utilization rate of flash memory.
Therefore, the application provides a kind of communication means of PCIE interface, and by the way that data packet is decoded processing, obtaining can
With the command packet parsed to data content and data format, then judge the order data whether with flash controller
Match, upon a match, the conversion of PCIE format is carried out to the order and data in command packet, by command packet from PCIE format
The format of flash controller is converted to, to meet the call format of flash controller, transformation result is finally sent to flash memory control
Device processed realizes and is attached flash controller by PCIE interface, improves the speed of data transmission, and ensure that number
According to the reliability of transmission.
Referring to FIG. 1, Fig. 1 is a kind of flow chart of the communication means of PCIE interface provided by the embodiment of the present application.
This method may include:
The data packet that S101, PCIE interface arrangement send AVALON-ST bus is decoded processing, obtains order data
Packet；
This step is intended to be decoded processing to the data packet for receiving the transmission of AVALON-ST bus, obtains order data
Packet.Wherein, PCIE is peripheral component interconnect express, is a kind of high speed serialization computer
Expansion bus standard, PCIE interface arrangement are the interface control unit for meeting PCIE standard, in the present embodiment PCIE interface
One end of device is connect with bus, and the other end is connect with flash controller, is attached flash memory by PCIE interface with realizing
Improve the read or write speed of flash data.
Wherein, AVALON-ST bus is a kind of transport protocol of AVALON bus.AVALON-ST interface is a kind of unidirectional
Point-to-point high-speed interface is primarily directed to the transmission of high-speed data-flow, reduces the bottleneck in Data Stream Processing.
The data packet received in this step is to meet the data packet of AVALON-ST agreement, wherein encapsulation is wanted
The data of operation, it is therefore desirable to be decoded to obtain command packet.Specifically, the method being decoded to data packet can
Coding/decoding method with any one the AVALON-ST protocol data packet provided using the prior art, is not specifically limited herein.
Wherein, the command packet being decoded and the data packet operation carried out are different and different, specifically,
When data packet is the data packet of write request, which includes write order and data.When the number that data packet is read request
When according to packet, which includes read command.
It should be noted that the data packet in this step is that same bus is sent, the coding that have passed through bus can not
Direct data are read out, need to be decoded processing, obtain the command packet that can be parsed out command information and data, with
Continue after an action of the bowels and data processing is continued to the command packet.
It further include that data check is carried out to data decoded in decoding process in this step.
Specifically, the integrality in order to guarantee data packet, this step may include:
Data packet is stored in corresponding caching by step 1, PCIE interface arrangement, is carried out at CRC check to data packet
Reason；
Step 2 is decoded processing to data packet according to AVALON-ST bus protocol when CRC check processing passes through
Obtain command packet.
It is mainly handled by CRC check in this concrete scheme, relevant checking treatment is carried out to data packet.Wherein, CRC
(Cyclic Redundancy Check) is that a kind of generated according to data such as network packet or computer documents briefly fixes digit
A kind of method of calibration of check code.
S102 judges whether command packet matches with flash controller according to the register identification in command packet；
If so, executing S103；If it is not, then executing S104；
On the basis of step S101, this step is intended to judge order data according to the register identification in command packet
Whether packet matches with flash controller；
There are 6 32 BAR (deposits in the PCIE interface arrangement of the present embodiment, that is, in the configuration space of PCIE
Device title) register.The function of general register each in the interface arrangement of PCIE needs the demand according to technical staff
It is set, register in the present embodiment is for storing PCIE device (flash controller in this implementation) in PCIE
Base address in the space of location to use the base address to be matched with corresponding PCIE device, and carries out data manipulation.Relatively
Answer, the command packet in this implementation saves register identification, for in interface arrangement BER register carry out
Match, obtains the base address of PCIE device for being matched with PCIE device, be specifically exactly 8 bit wides in the command packet
Data, for matching corresponding BAR register, to obtain the base address of the PCIE device in BAR register.
It is, the register identification for first passing through in this step in command packet judges whether there is corresponding BAR and posts
Storage gets the base address of the PCIE device in the register if there is being exactly, that is, carries out with flash controller
Match.
When command packet is matched with flash controller, expression can carry out data interaction with the flash controller,
Just it is to continue with subsequent operating process.
When command packet and flash controller mismatch, expression can not be matched to corresponding flash controller, can not
Carry out subsequent operating process.
S103 determines corresponding PCIE format conversion operation according to the type of command packet, executes the conversion of PCIE format
Operation, is sent to flash controller for transformation result.
On the basis of command packet has been matched to corresponding flash controller, this step is intended to according to command packet
Type execute corresponding PCIE format conversion operation.
Specifically, the command packet known to S101 in the present embodiment can be divided into two kinds, that is, write request command number
According to packet and read request command data packet.Data included in every kind of data packet are not identical, therefore carry out to it different
PCIE format conversion operation.
Specifically, including write request and writing data in write request command packet, need to carry out for the two different
The conversion of PCIE format.Read request is only included in read request command data packet, therefore only needs to carry out PCIE format to read request to turn
It changes.
In short, this step be exactly the data of PCIE format are converted into flash controller by PCIE format conversion operation can
With the formatted data handled.
S104, delete command data packet.
On the basis of command packet can not be matched to flash controller, this step is intended to delete the command packet,
Since command packet is to need to delete it, so as to subsequent there are in the memory elements such as register in PCIE interface arrangement
Data can continue to handle.
It optionally, can also include to the processing of synchronizing of command packet, that is, in command number before S103
Subsequent processing is carried out again after waiting the command packet whole end of transmission of a unit during according to packet transmission, is avoided out
Now during processing loss of data the case where.
Above step realizes PCIE interface connection flash controller, since there are PCIE interface itself faster data to pass
Defeated speed and higher reliability, therefore the data transmission bauds of flash memory and the reliability of data transmission can be improved.
To sum up, the present embodiment is by being decoded processing for data packet, obtain can to data content and data format into
The command packet of row parsing, then judge whether the order data matches with flash controller, upon a match, to command packet
In order and data carry out the conversion of PCIE format, command packet is converted to the format of flash controller from PCIE format,
To meet the call format of flash controller, transformation result is finally sent to flash controller, is realized flash controller
It is attached by PCIE interface, improves the speed of data transmission, and ensure that the reliability of data transmission.
Based on a upper embodiment, this implementation primarily directed in a upper embodiment how to write the command packet of type into
Do one of row format conversion operation illustrates, and other parts are substantially the same with a upper embodiment, and same section can refer to
A upper embodiment, this will not be repeated here.
Referring to FIG. 2, Fig. 2 is the stream for writing type format conversion operation in communication means provided by the embodiment of the present application
Cheng Tu.
The operation may include:
S201 carries out configuration information decoding process to command packet, obtains when the type of command packet is to write type
To configuration information, data acquisition process is carried out to command packet according to configuration information, obtains data；
This step is intended to when the type of command packet is to write type, that is, includes write order in command packet
And data, it needs to format processing for different objects.Configuration information decoding process first is carried out to command packet, is obtained
It include that write order and the information about data therefore can be according to the configuration informations pair in the configuration information to configuration information
Command packet carries out data acquisition process, obtains data.
Be primarily due to generally during data transmission, data can not end of transmission immediately, therefore, PCIE interface dress
Command portion may be first received in setting, that is, can be parsed out the data of configuration information.Further according to configuration information to subsequent
Data received, that is, processing is acquired to command packet.
Wherein, it in configuration information may include identification code about data beginning and end, be also possible to indicate that data are long
The information of degree can also be the information of end of data.It is assured that the end of data according to configuration information, therefore can adopt
Collect complete data.Wherein, the particular content of configuration information is not unique, is not specifically limited herein.
S202 formats processing to configuration information according to the write request format of flash controller, obtains write request；
On the basis of step S201, this step is intended to carry out configuration information according to the write request format of flash controller
Format conversion processing obtains write request.This step namely meets the write request of format in order to obtain.
Specifically, can first swap out write order from configuration information transfer, then write request is carried out according to write request format
Format is converted to write request, can be and write order is encapsulated as write request according to write request format, always obtains meeting writing and ask
Seek the request command of format.
S203 carries out bit width conversion processing to data according to the data bit width of flash controller, obtains data to be written；
On the basis of step S201, this step is intended to carry out bit width conversion processing to data, obtains data to be written.Due to
Data bit width in PCIE format is different with the bit wide of processing data in flash controller, it is therefore desirable to convert bit wide.
For example, the data bit width in PCIE is 32, and the bit wide of flash controller is 16, therefore 32 data are converted to 16
Position.Also, the data bit width in usual PCIE is greater than the bit wide of flash controller.
It should be noted that there is no sequencing, Ke Yisui for the execution sequence in the present embodiment between S202 and S203
Meaning is executed.
Write request and data to be written are sent to flash controller by S204.
On the basis of step S202 and S203, this step is intended to write request and data to be written being sent to flash memory control
Device, so as to complete to write type command packet format conversion operation.
Based on a upper embodiment, this implementation primarily directed in a upper embodiment how to read type command packet into
Do one of row format conversion operation illustrates, and other parts are substantially the same with a upper embodiment, and same section can refer to
A upper embodiment, this will not be repeated here.
Referring to FIG. 3, Fig. 3 is the stream of the reading type format conversion operation in communication means provided by the embodiment of the present application
Cheng Tu.
The operation may include:
S301 carries out configuration information decoding process to command packet, obtains when the type of command packet is to read type
To configuration information；
This step is intended to only include read command in command packet, therefore only need when command packet is reads type
Parse configuration information.
S302 formats processing to configuration information according to the read request format of flash controller, obtains read request；
On the basis of S301, this step is intended to format configuration information, obtains read request.
Read request is sent to flash controller by S303.
On the basis of S302, this step is intended to for read request being sent in flash controller, to transmit read command
To flash memory.
On the basis of all of above embodiment, the application also provides the embodiment of transmission returned data.Namely when connecing
When receiving returned data, PCIE interface arrangement handles returned data, to handle returned data, is back to
The main side PCIE device.
Referring to FIG. 4, Fig. 4 is the process of the returned data processing method in communication means provided by the embodiment of the present application
Figure.
This method may include:
S401 carries out lattice to returned data according to PCIE configuration information when PCIE interface arrangement receives returned data
Formula conversion process obtains return command data packet；
S402 carries out coded treatment to return command data packet according to AVALON-ST bus protocol, obtains returned data
Packet；
Returned data packet is sent to the main side PCIE device by S403.
The returned data that the present embodiment is intended to receive formats processing and coded treatment, and obtaining can be right
The returned data packet that the main side PCIE device is fed back.Wherein, PCIE configuration information include order in command packet and
The format of data, to format processing to returned data according to the format.
Specifically, returned data is exactly CPL (completion) report when returned data is the returned data of write order
Text transmits to terminate this data of writing.Wherein, CPL message refers to the completion message for not carrying data.Therefore, Ke Yizhi
Road, the returned data only carry out processing relevant to order when formatting processing, comprising: according to command format pair
Returned data carries out command format conversion, then carries out DESC said shank and obtain return command data packet.
When returned data is the returned data of read command, returned data is exactly CPLD (completion with data)
Message terminates read data transmission to be returned to read data, wherein CPLD message refers to the completion report for carrying data
Text.Therefore, it formats processing to the returned data to need to be respectively processed message part and data portion, to report
Literary part needs to carry out command format conversion to data are put back to according to command format, and data portion needs to carry out bit width conversion,
The transformation result of the two is carried out to DESC said shank together and obtains return command data packet.
In addition, there are two types of optional dispositions when handling read request.The configuration information that command packet is parsed
In judged whether need returned data immediately.If it is returned data immediately, then returned data is waited, when receiving return number
According to being handled and sent at once.If you do not need to returned data immediately, then can continue with other requests, return when receiving
Data are returned, is identified by the identification code and address of the returned data, is sent to correspondence after which is handled
Address.
Optionally, return command synchronizing of data packet can also be handled in the present embodiment, it can be real with reference to first
The synchronization process in example is applied, this will not be repeated here.
After the present embodiment is by formatting processing and coded treatment for returned data, obtain being returned
Returned data packet is sent to the main side PCIE by data packet, is transmitted to complete this data.
A kind of PCIE interface arrangement provided by the embodiments of the present application is introduced below, a kind of PCIE described below connects
Mouthful device can correspond to each other reference with a kind of above-described communication means of PCIE interface.
Referring to FIG. 5, Fig. 5 is a kind of structural schematic diagram of PCIE interface arrangement provided by the embodiment of the present application.
The apparatus may include:
Decoded packet data module 100, the data packet for sending to AVALON-ST bus are decoded processing, are ordered
Enable data packet；
Register mapping module 200, for judge the register identification in data packet whether the deposit with flash controller
Device matching；
Data packet format conversion module 300, for when the register mapping of register identification and flash controller, according to
The type of command packet determines corresponding PCIE format conversion operation, executes PCIE format conversion operation, transformation result is sent out
It send to flash controller.
Optionally, decoded packet data module 100 may include:
Verification unit carries out CRC check processing to data packet for data packet to be stored in corresponding caching；
Decoding unit, for being solved to data packet according to AVALON-ST bus protocol when CRC check processing passes through
Code processing obtains command packet.
The embodiment of the present application also provides a kind of device, comprising:
Memory, for storing computer program；
Processor, when for executing computer program the step of the realization such as communication means of above embodiments.
The embodiment of the present application also provides a kind of computer readable storage medium, and meter is stored on computer readable storage medium
Calculation machine program, when computer program is executed by processor the step of the realization such as communication means of above embodiments.
The computer readable storage medium may include: USB flash disk, mobile hard disk, read-only memory (Read-Only
Memory, ROM), random access memory (Random Access Memory, RAM), magnetic or disk etc. is various to deposit
Store up the medium of program code.
Each embodiment is described in a progressive manner in specification, the highlights of each of the examples are with other realities
The difference of example is applied, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is referring to method part illustration
?.
Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure
And algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Profession
Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered
Think beyond scope of the present application.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Above to communication means, PCIE interface arrangement, device and the calculating of a kind of PCIE interface provided herein
Machine readable storage medium storing program for executing is described in detail.Specific case used herein carries out the principle and embodiment of the application
It illustrates, the description of the example is only used to help understand the method for the present application and its core ideas.It should be pointed out that for
For those skilled in the art, under the premise of not departing from the application principle, if can also be carried out to the application
Dry improvement and modification, these improvement and modification are also fallen into the protection scope of the claim of this application.
Claims (10)
1. a kind of communication means of PCIE interface characterized by comprising
The data packet that PCIE interface arrangement sends AVALON-ST bus is decoded processing, obtains command packet；
Judge whether the command packet matches with flash controller according to the register identification in the command packet；
If so, determining corresponding PCIE format conversion operation according to the type of the command packet, the PCIE lattice are executed
The transformation result is sent to flash controller by formula conversion operation.
2. communication means according to claim 1, which is characterized in that further include:
When the command packet and the flash controller mismatch, the command packet is deleted.
3. communication means according to claim 1, which is characterized in that PCIE interface arrangement sends AVALON-ST bus
Data packet be decoded processing, obtain command packet, comprising:
The data packet is stored in corresponding caching by the PCIE interface arrangement, is carried out at CRC check to the data packet
Reason；
When CRC check processing passes through, processing is decoded to the data packet according to AVALON-ST bus protocol and is obtained
The command packet.
4. communication means according to claim 1, which is characterized in that determined and corresponded to according to the type of the command packet
PCIE format conversion operation, execute the PCIE format conversion operation, the transformation result be sent to flash controller, wrap
It includes:
When the type of the command packet is to write type, configuration information decoding process is carried out to the command packet, is obtained
To configuration information, data acquisition process is carried out to the command packet according to the configuration information, obtains data；
Processing is formatted to the configuration information according to the write request format of the flash controller, obtains write request；
Bit width conversion processing is carried out to the data according to the data bit width of the flash controller, obtains data to be written；
The write request and the data to be written are sent to the flash controller.
5. communication means according to claim 1, which is characterized in that determined and corresponded to according to the type of the command packet
PCIE format conversion operation, execute the PCIE format conversion operation, the transformation result be sent to flash controller, wrap
It includes:
When the type of the command packet is to read type, configuration information decoding process is carried out to the command packet, is obtained
To configuration information；
Processing is formatted to the configuration information according to the read request format of the flash controller, obtains read request；
The read request is sent to the flash controller.
6. communication means according to any one of claims 1 to 5, which is characterized in that further include:
When the PCIE interface arrangement receives returned data, format is carried out to the returned data according to PCIE configuration information
Conversion process obtains return command data packet；
Coded treatment is carried out to the return command data packet according to AVALON-ST bus protocol, obtains returned data packet；
The returned data packet is sent to the main side PCIE device.
7. a kind of PCIE interface arrangement characterized by comprising
Decoded packet data module, the data packet for sending to AVALON-ST bus are decoded processing, obtain order data
Packet；
Register mapping module, for judge the register identification in the data packet whether the register with flash controller
Match；
Data packet format conversion module, for when the register mapping of the register identification and the flash controller, root
Corresponding PCIE format conversion operation is determined according to the type of the command packet, executes the PCIE format conversion operation, it will
The transformation result is sent to flash controller.
8. PCIE interface arrangement according to claim 7, which is characterized in that the decoded packet data module, comprising:
Verification unit carries out CRC check processing to the data packet for the data packet to be stored in corresponding caching；
Decoding unit, for when the CRC check processing pass through when, according to AVALON-ST bus protocol to the data packet into
Row decoding process obtains the command packet.
9. a kind of device characterized by comprising
Memory, for storing computer program；
Processor realizes the step such as communication means as claimed in any one of claims 1 to 6 when for executing the computer program
Suddenly.
10. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program realizes the step such as communication means as claimed in any one of claims 1 to 6 when the computer program is executed by processor
Suddenly.
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