CN109164290B - Suspension voltage sampling circuit and method - Google Patents
Suspension voltage sampling circuit and method Download PDFInfo
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- CN109164290B CN109164290B CN201811165205.XA CN201811165205A CN109164290B CN 109164290 B CN109164290 B CN 109164290B CN 201811165205 A CN201811165205 A CN 201811165205A CN 109164290 B CN109164290 B CN 109164290B
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Abstract
The invention discloses a floating voltage sampling circuit and a method, wherein the circuit comprises: the first voltage dividing circuit is electrically connected between a first floating voltage node and a grounding end, so that the voltage of the node opposite to the grounding end is sampled at the first voltage dividing node of the first voltage dividing circuit, the first switching tube circuit is connected between the first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit in series, the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground, the first voltage dividing node of the second voltage dividing circuit is electrically connected with a positive-phase input end of the first operational amplifier circuit, an output end of the first operational amplifier circuit is electrically connected with a switch control end of the first switching tube circuit, and an inverting input end of the first operational amplifier circuit is electrically connected with the second voltage dividing node through a negative feedback circuit.
Description
Technical Field
The invention relates to a floating voltage sampling circuit and a method.
Background
The inventor of the present invention has found that in the application of an emergency car starting power supply, it is necessary to detect the voltage of an external car battery to determine that the starting is not suitable. Therefore, a method for detecting the voltage of the battery of the automobile even though the emergency starting power supply and the battery of the automobile are not commonly used is needed.
Disclosure of Invention
One of the purposes of the embodiments of the present invention is to provide a floating voltage sampling circuit and method, and to apply the technical scheme of the embodiment, in which a zero potential reference point of a voltage testing device is used as a ground terminal, so that a voltage of a floating node, which is not commonly grounded to the ground terminal of the voltage testing device, relative to a floating ground can be measured.
In a first aspect, an embodiment of the present invention provides a method for sampling a floating voltage, including:
sampling the voltage of a first voltage division node of a first voltage division circuit relative to a ground terminal, wherein the first voltage division circuit is electrically connected between the first suspension voltage node and the ground terminal;
calculating the voltage of the first floating voltage node relative to floating ground according to the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, the impedance between the first voltage division node of the first voltage division circuit and the ground terminal, the impedance between the second voltage division node of the first voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of the second voltage division circuit and the first floating voltage node, and the impedance of the second voltage division circuit;
a first switching tube circuit is connected in series between a first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, in the first voltage dividing circuit, the second voltage dividing node is electrically connected between the first voltage dividing node and the first floating voltage node, the second voltage dividing node of the first voltage dividing circuit is electrically connected with an inverting input end of a first operational amplifier circuit through a negative feedback circuit, a non-inverting input end of the first operational amplifier circuit is electrically connected with the first voltage dividing node of the second voltage dividing circuit, an output end of the first operational amplifier circuit is electrically connected with a control end of the first switching tube circuit, and the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground.
Optionally, calculating the voltage of the first floating voltage node relative to floating ground includes:
according to the following steps: i1 =vtest 11/R2, the current I1 of the first voltage divider circuit is calculated,
vtest11 is the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, and R2 is the impedance between the first voltage division node of the first voltage division circuit and the ground terminal;
according to the following steps: v1=i1×r1, calculating a voltage VR1 between the second voltage dividing node of the first voltage dividing circuit and the first floating voltage node,
r1 is the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node;
according to the following: VR 1=vr3, i.e. the voltage VR3 between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node is obtained;
according to the following steps: i2 =vr3/R3, i.e. the current I2, R3 of the second voltage dividing circuit is the impedance between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node;
according to the following: and (r3+r4) to obtain the voltage VB1 between the first floating voltage node and the floating ground, where (r3+r4) is the impedance of the second voltage divider circuit.
Optionally, the first voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the first switching tube circuit is a semiconductor switching tube.
Optionally, the semiconductor switch tube is a MOS tube or a transistor.
Optionally, the method further comprises:
calculating the voltage of a second floating voltage node relative to the floating ground according to the current of the second voltage dividing circuit, the impedance between the second voltage dividing node of the second voltage dividing circuit and the floating ground, the impedance between the first voltage dividing node of a third voltage dividing circuit and the floating ground and the impedance of the third voltage dividing circuit;
the third voltage dividing circuit is electrically connected between the second floating voltage node and the floating ground, the first voltage dividing node of the third voltage dividing circuit is electrically connected with the non-inverting input end of the second operational amplifying circuit, the output end of the second operational amplifying circuit is electrically connected with the control end of the second switching tube circuit,
the inverting input end of the second operational amplifier circuit is electrically connected with a second voltage division node of the second voltage division circuit through a negative feedback circuit, the second voltage division node of the second voltage division circuit is positioned between the first voltage division node of the second voltage division circuit and the floating ground,
the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
Optionally, calculating a voltage of the second floating voltage node relative to the floating ground includes:
according to the following steps: VR4 = I2R 4, the second voltage division node of the second voltage division circuit being with respect to the voltage VR4 between the floating grounds, R4 being the impedance between the second voltage division node of the second voltage division circuit and the floating ground;
according to the following steps: VR 6=vr4, i.e. the voltage between the first voltage dividing node of the third voltage dividing circuit and the floating ground,
according to the following steps: i3 =vr6/R6, the current I3 of the third voltage divider circuit is calculated, R6 is the impedance between the first voltage divider node of the third voltage divider circuit and the floating ground,
according to the following steps: vb2=i3 (r5+r6), and the voltage of the second floating voltage node relative to the floating ground is calculated.
Optionally, the third voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second switching tube circuit is a semiconductor switching tube.
Optionally, the semiconductor switch tube is a MOS tube or a transistor.
In a second aspect, an embodiment of the present invention provides a method for sampling a floating voltage, including:
sampling the voltage of a first voltage division node of a first voltage division circuit relative to a ground terminal, wherein the first voltage division circuit is electrically connected between the first suspension voltage node and the ground terminal;
calculating the voltage of a second floating voltage node relative to the floating ground according to the voltage of a first voltage division node of the first voltage division circuit relative to the ground terminal, the impedance between the first voltage division node of the first voltage division circuit and the ground terminal, the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of the second voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of a third voltage division circuit and the floating ground, and the impedance of the third voltage division voltage;
a first switching tube circuit is connected in series between a first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, in the first voltage dividing circuit, the second voltage dividing node is electrically connected between the first voltage dividing node and the first floating voltage node, the second voltage dividing node of the first voltage dividing circuit is electrically connected with an inverting input end of a first operational amplifier circuit through a negative feedback circuit, a non-inverting input end of the first operational amplifier circuit is electrically connected with the first voltage dividing node of the second voltage dividing circuit, an output end of the first operational amplifier circuit is electrically connected with a control end of the first switching tube circuit, and the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground;
the third voltage dividing circuit is electrically connected between the second floating voltage node and the floating ground, a first voltage dividing node of the third voltage dividing circuit is electrically connected with a positive input end of the second operational amplifying circuit, an output end of the second operational amplifying circuit is electrically connected with a control end of the second switching tube circuit, an opposite phase input end of the second operational amplifying circuit is electrically connected with a second voltage dividing node of the second voltage dividing circuit through a negative feedback circuit, the second voltage dividing node of the second voltage dividing circuit is located between a first voltage dividing node of the second voltage dividing circuit and the floating ground, and the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
Optionally, calculating a voltage of the second floating voltage node relative to the floating ground includes:
according to the following steps: i1 =vtest 11/R2, the current I1 of the first voltage divider circuit is calculated,
vtest11 is the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, and R2 is the impedance between the first voltage division node of the first voltage division circuit and the ground terminal;
according to the following steps: v1=i1×r1, calculating a voltage VR1 between the second voltage dividing node of the first voltage dividing circuit and the first floating voltage node,
r1 is the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node;
according to the following: VR 1=vr3, i.e. the voltage VR3 between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node is obtained;
according to the following steps: i2 =vr3/R3, i.e. the current I2, R3 of the second voltage dividing circuit is the impedance between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node;
according to the following steps: VR4 = I2R 4, the second voltage division node of the second voltage division circuit being with respect to the voltage VR4 between the floating grounds, R4 being the impedance between the second voltage division node of the second voltage division circuit and the floating ground;
according to the following steps: VR 6=vr4, i.e. the voltage between the first voltage dividing node of the third voltage dividing circuit and the floating ground,
according to the following steps: i3 =vr6/R6, the current I3 of the third voltage divider circuit is calculated, R6 is the impedance between the first voltage divider node of the third voltage divider circuit and the floating ground,
according to the following steps: vb2=i3 (r5+r6), and the voltage of the second floating voltage node relative to the floating ground is calculated.
Optionally, the first voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the first switching tube circuit is a semiconductor switching tube.
Optionally, the semiconductor switch tube is a MOS tube or a transistor.
Optionally, the third voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second switching tube circuit is a semiconductor switching tube.
Optionally, the semiconductor switch tube is a MOS tube or a transistor.
In a third aspect, an embodiment of the present invention provides a floating voltage sampling circuit, including:
a first voltage dividing circuit, a second voltage dividing circuit, a first operational amplifier circuit, a first switch Guan Dianlu,
the first voltage dividing circuit is electrically connected between a first floating voltage node and a ground terminal to sample the voltage of the node relative to the ground terminal at the first voltage dividing node of the first voltage dividing circuit,
the first switch Guan Dianlu is connected in series between the first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, which is electrically connected between the first floating voltage node and a floating ground,
the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground, the first voltage dividing node of the second voltage dividing circuit is electrically connected with the normal phase input end of the first operational amplifying circuit, the output end of the first operational amplifying circuit is electrically connected with the switch control end of the first switching tube circuit, and the reverse phase input end of the first operational amplifying circuit is electrically connected with the second voltage dividing node of the first voltage dividing circuit through the negative feedback circuit.
Optionally, the first voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the first switching tube circuit is a semiconductor switching tube.
Optionally, the first switching transistor circuit is a MOS transistor or a transistor.
Optionally, a third voltage dividing circuit, a second operational amplifier circuit, a second switch Guan Dianlu,
the third voltage dividing circuit is electrically connected between the floating ground and the second floating voltage node, the first voltage dividing node of the third voltage dividing circuit is electrically connected with the non-inverting input end of the second operational amplifier circuit, and the output end of the second operational amplifier circuit is electrically connected with the control end of the second switching tube circuit;
the inverting input end of the second operational amplifier circuit is electrically connected with a second voltage division node of the second voltage division circuit through a negative feedback circuit, the second voltage division node of the second voltage division circuit is positioned between the first voltage division node of the second voltage division circuit and the floating ground,
the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
Optionally, the third voltage dividing circuit is an impedance voltage dividing circuit.
Optionally, the second switching tube circuit is a semiconductor switching tube.
Optionally, the semiconductor switch tube is a MOS tube or a transistor.
From the above, with the sampling circuit of the embodiment, sampling of the floating voltage can be achieved by sampling the GND voltage of the ground terminal, so as to achieve real-time monitoring of the floating voltage.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate and together with the description serve to explain the invention.
Fig. 1 is a schematic diagram of a floating voltage sampling circuit according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a floating voltage sampling circuit according to embodiment 2 of the present invention.
Description of the embodiments
The present invention will now be described in detail with reference to the drawings and the specific embodiments thereof, wherein the exemplary embodiments and descriptions of the present invention are provided for illustration of the invention and are not intended to be limiting.
Examples
Referring to fig. 1, the present embodiment provides a floating voltage sampling circuit, which mainly includes:
the first voltage divider circuit, the second voltage divider circuit, the first operational amplifier circuit A1 and the first switching tube circuit Q1. The first voltage dividing circuit is electrically connected between the first floating voltage node B1+ and the ground terminal GND, and a first voltage dividing node test11 and a second voltage dividing node test12 are disposed in the first voltage dividing circuit, and the second voltage dividing node test12 is located between the first voltage dividing node test11 and the first floating voltage node B1+.
The voltage sampling is performed on the first voltage division node test11, so as to obtain a sampling voltage of the first voltage division node test11 with respect to the ground GND, which is denoted as Vtest11.
The first switch Guan Dianlu Q1 is connected in series in the first voltage dividing circuit and is located between the first voltage dividing node test11 and the second voltage dividing node test 12.
The second voltage dividing circuit is electrically connected between the first floating voltage node B1+ and the floating ground. The floating ground in this embodiment is a reference zero potential node that is not grounded, i.e., not grounded to the ground GND.
The positive phase input end "+" of the first operational amplifier circuit A1 is connected to the first voltage division node test21 of the second voltage division circuit, the negative phase input end "-" is electrically connected with the second voltage division node test12 of the first voltage division circuit through the negative feedback circuit, and the output end is electrically connected with the switch control end of the first switch tube circuit Q1.
As an illustration of the present embodiment, the present embodiment implements a first voltage dividing circuit using an impedance voltage dividing circuit composed of resistors R1, R2 as shown in fig. 1;
as an illustration of the present embodiment, the present embodiment implements the second voltage dividing circuit using an impedance voltage dividing circuit composed of resistors R3, R4 as shown in fig. 1.
As an illustration of the present embodiment, the first switch Guan Dianlu Q1 of the present embodiment is implemented by a transistor as shown in fig. 1, and the transistor may be a triode, a MOS transistor, a field effect transistor, or the like. For example, in this embodiment, the first switching tube circuit Q1 is implemented by using a P-type MOS tube.
As an illustration of the present embodiment, the negative feedback circuit of the first operational amplifier circuit A1 of the present embodiment may be configured such that the inverting input terminal "-" of the first operational amplifier circuit A1 is directly electrically connected to the second voltage dividing node test12 of the first voltage dividing circuit, as shown in fig. 1 and 2; in order to further accelerate the negative feedback response efficiency, a capacitor, a resistor, etc. may be provided in the negative feedback circuit, which may be implemented in the prior art, but is not limited thereto.
As an illustration of the present embodiment, the first operational amplifier circuit A1 of the present embodiment may be implemented using an operational amplifier.
The working principle of the circuit is as follows:
the voltage sampling is performed at the first voltage dividing node test11 of the first voltage dividing circuit, and the voltage of the first voltage dividing node test11 with respect to the ground GND is measured and denoted as Vtest11.
According to ohm's law: i1 =vtest 11/R2, the current I1 of the first voltage divider circuit can be calculated;
according to ohm's law: the voltage VR1 between the second voltage division node test12 and the first floating voltage node b1+ of the first voltage division circuit can be calculated by VR 1=i1=r1=vtest 11×r1/R2.
Since, in the circuit of the present embodiment, the voltage at the non-inverting input terminal "+" and the voltage at the inverting input terminal of the first operational amplifier A1 are equal,
VR 1=vr3=vtest 11×r1/R2, i.e. a voltage VR3 between the first voltage dividing node test21 of the second voltage dividing circuit and the first floating voltage node b1+;
according to ohm's law: i2 =vr3/r3= (Vtest 11×r1)/(r2×r3), and the current I2 of the second voltage divider circuit is obtained.
According to ohm's law: vb1=i2 ] = (r3+r4) = (Vtest 11×r1 ] (r3+r4))/(r2×r3), and the voltage VB1 between the first floating voltage node b1+ and the floating ground is obtained, so as to obtain the floating voltage VB1 of the embodiment.
From the above, with the sampling circuit of the embodiment, sampling of the floating voltage can be achieved by sampling the GND voltage of the ground terminal, so as to achieve real-time monitoring of the floating voltage.
As an illustration of this embodiment, a current limiting resistor R0 may be further connected between the first voltage dividing node test11 of the first voltage dividing circuit and the voltage sampling pin, so as to limit the sampling current, and avoid burning out the sampling circuit caused by excessive sampling current.
Examples
As shown in fig. 2, the present embodiment is different from the circuit of embodiment 1 mainly in that:
the floating voltage sampling circuit of this embodiment further includes: a third voltage dividing circuit, a second operational amplifier circuit A2 and a second switching tube circuit Q2.
The third voltage dividing circuit is electrically connected between the floating ground and the second floating voltage node B < 2+ >;
the positive phase input end "+" of the second operational amplifier circuit A2 is electrically connected with the first voltage division node text31 of the third voltage division circuit, the negative phase input end "-" is electrically connected with the second voltage division node test22 of the second voltage division circuit through the negative feedback circuit, and the output end is electrically connected with the control end of the second switching tube circuit Q2.
The second voltage division node test22 of the second voltage division circuit is located between the first voltage division node test21 of the second voltage division circuit and the floating ground, and the second switching tube circuit Q2 is connected in series in the second voltage division circuit and is connected in series between the first voltage division node test21 and the second voltage division node test22 of the second voltage division circuit.
As an illustration of the present embodiment, the present embodiment implements a third voltage dividing circuit using an impedance voltage dividing circuit composed of resistors R5, R6 as shown in fig. 2;
as an illustration of the present embodiment, the second switching transistor circuit Q2 of the present embodiment is implemented by a transistor as shown in fig. 2, and the transistor may be a triode, a MOS transistor, a field effect transistor, or the like. For example, in this embodiment, the second switching tube circuit Q2 is implemented by using an N-type MOS tube.
As an illustration of the present embodiment, the negative feedback circuits of the first operational amplifier circuit A1 and the second operational amplifier circuit A2 of the present embodiment may be configured such that the inverting input terminals "-" of the first operational amplifier circuit A1 and the second operational amplifier circuit A2 are directly electrically connected to the second voltage dividing node test12 of the first voltage dividing circuit and the second voltage dividing node test22 of the second voltage dividing circuit, respectively, as shown in fig. 2; in order to further accelerate the negative feedback response efficiency, a capacitor, a resistor, etc. may be provided in the negative feedback circuit, which may be implemented in the prior art, but is not limited thereto.
As an illustration of the present embodiment, the second operational amplifier circuit A2 of the present embodiment may be implemented using an operational amplifier.
The method of sampling the second floating voltage node B2+ using the circuit shown in fig. 2 is as follows:
as described in embodiment 1, after the voltage sampling is performed at the first voltage dividing node test11 of the first voltage dividing circuit and the voltage Vtest11 of the first voltage dividing node test11 with respect to the ground GND is measured, the current I2 of the second voltage dividing circuit is calculated according to the principle described in embodiment 1:
I2= VR3/R3=( Vtest11*R1)/(R2*R3)；
from the current I2 of the second voltage dividing circuit, the voltage VR4 between the second voltage dividing node test22 of the second voltage dividing circuit with respect to the floating ground is calculated:
VR4= I2*R4=VR3*R4/R3=( Vtest11*R1*R4)/(R2*R3)；
since the voltages at the non-inverting input "+" and the inverting input of the operational amplifier A2 are equal in the circuit of the present embodiment, the following applies:
VR6= VR4= I2*R4=VR3*R4/R3=( Vtest11*R1*R4)/(R2*R3)；
according to ohm's law:
i3 =vr6/r6= (Vtest 11×r1×r4)/(r2×r3×r6), to obtain the current I3 of the third voltage divider circuit,
according to ohm's law:
vb2=i3+ (r5+r6) = (Vtest 11×r1×r4 (r5+r6))/(r2×r3×r6), i.e. the voltage VB2 between the second floating voltage node B2+ and the floating ground is obtained, i.e. the second floating voltage VB2 of the present embodiment is obtained.
From the above, with the sampling circuit of the embodiment, the sampling of the floating voltage can be realized by sampling the voltage of the ground terminal GND, so that the real-time monitoring of the floating voltage is realized.
Note that, in the embodiments 1 and 2, the first switching transistor circuit and the second switching transistor circuit are implemented by MOS transistors as an illustration, but the present invention is not limited thereto, and the switching transistors in the first switching transistor circuit and the second switching transistor circuit may be various semiconductor switching transistors, such as transistors and other MOS transistors.
The above-described embodiments do not limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above embodiments should be included in the scope of the present invention.
Claims (29)
1. A method of sampling a levitation voltage, comprising:
sampling the voltage of a first voltage division node of a first voltage division circuit relative to a grounding end, wherein the first voltage division circuit is electrically connected between a first suspension voltage node and the grounding end;
calculating the voltage of the first floating voltage node relative to floating ground according to the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, the impedance between the first voltage division node of the first voltage division circuit and the ground terminal, the impedance between the second voltage division node of the first voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of the second voltage division circuit and the first floating voltage node, and the impedance of the second voltage division circuit;
a first switching tube circuit is connected in series between a first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, in the first voltage dividing circuit, the second voltage dividing node is electrically connected between the first voltage dividing node and the first floating voltage node, the second voltage dividing node of the first voltage dividing circuit is electrically connected with an inverting input end of a first operational amplifier circuit through a negative feedback circuit, a non-inverting input end of the first operational amplifier circuit is electrically connected with the first voltage dividing node of the second voltage dividing circuit, an output end of the first operational amplifier circuit is electrically connected with a control end of the first switching tube circuit, and the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground.
2. The method for sampling levitation voltage according to claim 1, wherein,
calculating a voltage of the first floating voltage node relative to floating ground, comprising:
according to the following steps: i1 =vtest 11/R2, the current I1 of the first voltage divider circuit is calculated,
vtest11 is the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, and R2 is the impedance between the first voltage division node of the first voltage division circuit and the ground terminal;
according to the following steps: v1=i1×r1, calculating a voltage VR1 between the second voltage dividing node of the first voltage dividing circuit and the first floating voltage node,
r1 is the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node;
according to the following: VR 1=vr3, i.e. the voltage VR3 between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node is obtained;
according to the following steps: i2 =vr3/R3, i.e. the current I2, R3 of the second voltage dividing circuit is the impedance between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node;
according to the following: and (r3+r4) to obtain the voltage VB1 between the first floating voltage node and the floating ground, where (r3+r4) is the impedance of the second voltage divider circuit.
3. The method for sampling levitation voltage according to claim 1, wherein,
the first voltage dividing circuit is an impedance voltage dividing circuit.
4. The method for sampling levitation voltage according to claim 1, wherein,
the second voltage dividing circuit is an impedance voltage dividing circuit.
5. The method for sampling levitation voltage according to claim 1, wherein,
the first switching tube circuit is a semiconductor switching tube.
6. The method for sampling levitation voltage according to claim 5, wherein,
the semiconductor switch tube is an MOS tube or a transistor.
7. The floating voltage sampling method as claimed in claim 1, further comprising:
calculating the voltage of a second floating voltage node relative to the floating ground according to the current of the second voltage dividing circuit, the impedance between the second voltage dividing node of the second voltage dividing circuit and the floating ground, the impedance between the first voltage dividing node of a third voltage dividing circuit and the floating ground and the impedance of the third voltage dividing circuit;
the third voltage dividing circuit is electrically connected between the second floating voltage node and the floating ground, the first voltage dividing node of the third voltage dividing circuit is electrically connected with the non-inverting input end of the second operational amplifying circuit, the output end of the second operational amplifying circuit is electrically connected with the control end of the second switching tube circuit,
the inverting input end of the second operational amplifier circuit is electrically connected with a second voltage division node of the second voltage division circuit through a negative feedback circuit, the second voltage division node of the second voltage division circuit is positioned between the first voltage division node of the second voltage division circuit and the floating ground,
the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
8. The method for sampling levitation voltage according to claim 7, wherein,
calculating a voltage of a second levitation voltage node relative to the levitation ground, comprising:
according to the following steps: VR4 = I2R 4, the second voltage division node of the second voltage division circuit being with respect to the voltage VR4 between the floating grounds, R4 being the impedance between the second voltage division node of the second voltage division circuit and the floating ground;
according to the following steps: VR 6=vr4, i.e. the voltage between the first voltage dividing node of the third voltage dividing circuit and the floating ground,
according to the following steps: i3 =vr6/R6, the current I3 of the third voltage divider circuit is calculated, R6 is the impedance between the first voltage divider node of the third voltage divider circuit and the floating ground,
according to the following steps: vb2=i3 (r5+r6), and the voltage of the second floating voltage node relative to the floating ground is calculated.
9. The method for sampling levitation voltage according to claim 7, wherein,
the third voltage dividing circuit is an impedance voltage dividing circuit.
10. The method for sampling levitation voltage according to claim 7, wherein,
the second switching tube circuit is a semiconductor switching tube.
11. The method for sampling levitation voltage according to claim 10, wherein,
the semiconductor switch tube is an MOS tube or a transistor.
12. A method of sampling a levitation voltage, comprising:
sampling the voltage of a first voltage division node of a first voltage division circuit relative to a grounding end, wherein the first voltage division circuit is electrically connected between a first suspension voltage node and the grounding end;
calculating the voltage of a second floating voltage node relative to the floating ground according to the voltage of a first voltage division node of the first voltage division circuit relative to the ground terminal, the impedance between the first voltage division node of the first voltage division circuit and the ground terminal, the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of the second voltage division circuit and the first floating voltage node, the impedance between the first voltage division node of a third voltage division circuit and the floating ground, and the impedance of the third voltage division voltage;
a first switching tube circuit is connected in series between a first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, in the first voltage dividing circuit, the second voltage dividing node is electrically connected between the first voltage dividing node and the first floating voltage node, the second voltage dividing node of the first voltage dividing circuit is electrically connected with an inverting input end of a first operational amplifier circuit through a negative feedback circuit, a non-inverting input end of the first operational amplifier circuit is electrically connected with the first voltage dividing node of the second voltage dividing circuit, an output end of the first operational amplifier circuit is electrically connected with a control end of the first switching tube circuit, and the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground;
the third voltage dividing circuit is electrically connected between the second floating voltage node and the floating ground, a first voltage dividing node of the third voltage dividing circuit is electrically connected with a positive input end of the second operational amplifying circuit, an output end of the second operational amplifying circuit is electrically connected with a control end of the second switching tube circuit, an opposite phase input end of the second operational amplifying circuit is electrically connected with a second voltage dividing node of the second voltage dividing circuit through a negative feedback circuit, the second voltage dividing node of the second voltage dividing circuit is located between a first voltage dividing node of the second voltage dividing circuit and the floating ground, and the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
13. The method for sampling levitation voltages according to claim 12, wherein,
calculating a voltage of a second levitation voltage node relative to the levitation ground, comprising:
according to the following steps: i1 =vtest 11/R2, the current I1 of the first voltage divider circuit is calculated,
vtest11 is the voltage of the first voltage division node of the first voltage division circuit relative to the ground terminal, and R2 is the impedance between the first voltage division node of the first voltage division circuit and the ground terminal;
according to the following steps: v1=i1×r1, calculating a voltage VR1 between the second voltage dividing node of the first voltage dividing circuit and the first floating voltage node,
r1 is the impedance between a second voltage division node of the first voltage division circuit and the first floating voltage node;
according to the following: VR 1=vr3, i.e. the voltage VR3 between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node is obtained;
according to the following steps: i2 =vr3/R3, i.e. the current I2, R3 of the second voltage dividing circuit is the impedance between the first voltage dividing node of the second voltage dividing circuit and the first floating voltage node;
according to the following steps: VR4 = I2R 4, the second voltage division node of the second voltage division circuit being with respect to the voltage VR4 between the floating grounds, R4 being the impedance between the second voltage division node of the second voltage division circuit and the floating ground;
according to the following steps: VR 6=vr4, i.e. the voltage between the first voltage dividing node of the third voltage dividing circuit and the floating ground,
according to the following steps: i3 =vr6/R6, the current I3 of the third voltage divider circuit is calculated, R6 is the impedance between the first voltage divider node of the third voltage divider circuit and the floating ground,
according to the following steps: vb2=i3 (r5+r6), and the voltage of the second floating voltage node relative to the floating ground is calculated.
14. The method for sampling levitation voltages according to claim 12, wherein,
the first voltage dividing circuit is an impedance voltage dividing circuit.
15. The method for sampling levitation voltages according to claim 12, wherein,
the second voltage dividing circuit is an impedance voltage dividing circuit.
16. The method for sampling levitation voltages according to claim 12, wherein,
the first switching tube circuit is a semiconductor switching tube.
17. The method of claim 16, wherein,
the semiconductor switch tube is an MOS tube or a transistor.
18. The method for sampling levitation voltages according to claim 12, wherein,
the third voltage dividing circuit is an impedance voltage dividing circuit.
19. The method for sampling levitation voltages according to claim 12, wherein,
the second switching tube circuit is a semiconductor switching tube.
20. The method of claim 19, wherein the floating voltage sampling is performed,
the semiconductor switch tube is a MOS tube or a transistor.
21. A floating voltage sampling circuit, comprising:
a first voltage dividing circuit, a second voltage dividing circuit, a first operational amplifier circuit, a first switch Guan Dianlu,
the first voltage dividing circuit is electrically connected between a first floating voltage node and a ground terminal to sample the voltage of the node relative to the ground terminal at the first voltage dividing node of the first voltage dividing circuit,
the first switch Guan Dianlu is connected in series between the first voltage dividing node and a second voltage dividing node of the first voltage dividing circuit, which is electrically connected between the first floating voltage node and a floating ground,
the second voltage dividing circuit is electrically connected between the first floating voltage node and the floating ground, the first voltage dividing node of the second voltage dividing circuit is electrically connected with the normal phase input end of the first operational amplifying circuit, the output end of the first operational amplifying circuit is electrically connected with the switch control end of the first switching tube circuit, and the reverse phase input end of the first operational amplifying circuit is electrically connected with the second voltage dividing node of the first voltage dividing circuit through the negative feedback circuit.
22. The floating voltage sampling circuit of claim 21, wherein,
the first voltage dividing circuit is an impedance voltage dividing circuit.
23. The floating voltage sampling circuit of claim 21, wherein,
the second voltage dividing circuit is an impedance voltage dividing circuit.
24. The floating voltage sampling circuit of claim 21, wherein,
the first switching tube circuit is a semiconductor switching tube.
25. The floating voltage sampling circuit of claim 24, wherein,
the first switching tube circuit is an MOS tube or a transistor.
26. The floating voltage sampling circuit of claim 21, wherein,
also comprises a third voltage dividing circuit, a second operational amplifier circuit and a second switch Guan Dianlu,
the third voltage dividing circuit is electrically connected between the floating ground and the second floating voltage node, the first voltage dividing node of the third voltage dividing circuit is electrically connected with the non-inverting input end of the second operational amplifier circuit, and the output end of the second operational amplifier circuit is electrically connected with the control end of the second switching tube circuit;
the inverting input end of the second operational amplifier circuit is electrically connected with a second voltage division node of the second voltage division circuit through a negative feedback circuit, the second voltage division node of the second voltage division circuit is positioned between the first voltage division node of the second voltage division circuit and the floating ground,
the second switch Guan Dianlu is connected in series between the first voltage dividing node and the second voltage dividing node of the second voltage dividing circuit.
27. The floating voltage sampling circuit of claim 26, wherein,
the third voltage dividing circuit is an impedance voltage dividing circuit.
28. The floating voltage sampling circuit of claim 26, wherein,
the second switching tube circuit is a semiconductor switching tube.
29. The floating voltage sampling circuit of claim 28, wherein,
the semiconductor switch tube is an MOS tube or a transistor.
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| CN114236217B (en) * | 2022-02-23 | 2022-06-28 | 苏州贝克微电子股份有限公司 | Floating type chip voltage detection circuit |
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