CN109119016B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN109119016B CN109119016B CN201811099729.3A CN201811099729A CN109119016B CN 109119016 B CN109119016 B CN 109119016B CN 201811099729 A CN201811099729 A CN 201811099729A CN 109119016 B CN109119016 B CN 109119016B
- Authority
- CN
- China
- Prior art keywords
- shift register
- input end
- transistor
- register unit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000725 suspension Substances 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 18
- 230000005669 field effect Effects 0.000 claims description 17
- 230000001960 triggered effect Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007562 laser obscuration time method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0283—Arrangement of drivers for different directions of scanning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The application discloses display panel and display device, wherein, display panel's gate drive circuit includes a plurality of consecutive scanning time sequence sections, and every scanning time sequence section includes scanning signal time sequence section and unsettled signal time sequence section, and when scanning signal time sequence section, gate drive circuit normally provides scanning signal for present line display pixel, and when unsettled signal time sequence section, gate line that gate drive circuit will connect present line display pixel is connected with predetermined gate line electricity to make remaining electric charge can release through predetermined gate line in the present line display pixel, avoided because remaining electric charge in the display pixel and the incomplete image problem of demonstration that leads to. And because the display panel does not need to be frequently switched to the working state of the charge pump for providing the power supply voltage by the grid drive circuit, and a device for controlling the working state of the charge pump does not need to be arranged in the power supply, the cost of the power supply is reduced, and the problem of stronger electromagnetic interference caused by the power supply is avoided.
Description
Technical Field
The present application relates to the field of display device technologies, and more particularly, to a display panel and a display apparatus.
Background
With the development of display technologies, users have increasingly high requirements for the quality of the display screen of the display panel. Among them, the problem of image sticking is one of the key factors of the display quality of the image frame.
The prior art approach to solve the image sticking problem of the display panel is usually implemented by adding a charge draining path and an enabling circuit for controlling a charge pump in a device for providing a power supply voltage to a gate driving circuit. Specifically, in the working process, the enabling circuit provides a determined time sequence signal for the charge pump, controls the charge pump to normally work when the time sequence signal is in a high level, and provides a driving power supply for the gate driving circuit so as to enable the gate driving circuit to provide a scanning signal for the display pixel, and at the moment, the charge leakage path does not work; when the time sequence signal is in low level, the charge pump is controlled to stop working, and at the moment, the residual charges in the display pixels are released through the charge leakage path, so that the problem of image retention caused by the residual charges in the display pixels is solved.
However, in this way of controlling the intermittent operation of the charge pump, radiation noise is generated during the process of continuously switching the operation state of the charge pump, and the radiation noise may cause strong Electromagnetic Interference (EMI) to devices around the charge pump.
Disclosure of Invention
In order to solve the above technical problem, the present application provides a display panel and a display device, so as to achieve the purpose of solving the problem of image retention of the display panel on the basis of not generating strong electromagnetic interference.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a display panel, comprising:
a first substrate;
a plurality of display pixels arranged in an array on the first substrate;
a plurality of gate lines electrically connected to the display pixels, and a gate driving circuit electrically connected to the gate lines;
the grid driving circuit comprises a plurality of scanning time sequence sections which are sequentially connected, the scanning time sequence sections are sequentially triggered, each scanning time sequence section corresponds to one row of display pixels, and each scanning time sequence section comprises a scanning signal time sequence section and a suspension signal time sequence section;
during the scanning signal time sequence section, the gate drive circuit is used for providing scanning signals for the display pixels of the current line, and the display pixels of the current line are the display pixels of the line corresponding to the currently triggered scanning signal time sequence section;
when the suspension signal time sequence section is finished, the grid drive circuit is used for electrically connecting the grid line connected with the display pixels on the current line with a preset grid line so as to release residual charges in the display pixels on the current line, and triggering the next scanning time sequence section when the suspension signal time sequence section is finished; and the display pixels connected with the preset gate lines are not adjacent to the display pixels on the current row.
A display device comprising a display panel as claimed in one of the above claims.
It can be seen from the foregoing technical solutions that the present application provides a display panel and a display device, wherein a gate driving circuit of the display panel includes a plurality of scanning timing sections connected in sequence, each scanning timing section includes a scanning signal timing section and a suspension signal timing section, when the scanning signal timing sections are used, the gate driving circuit normally provides a scanning signal for a current row of display pixels, and when the suspension signal timing sections are used, the gate line connected to the current row of display pixels is electrically connected to a preset gate line, so that charges remaining in the current row of display pixels can be released through the preset gate line, and the problem of display image retention caused by the charges remaining in the display pixels is avoided. And because the display panel does not need to be frequently switched to the working state of the charge pump for providing the power supply voltage by the grid drive circuit, and a device for controlling the working state of the charge pump does not need to be arranged in the power supply, the cost of the power supply is reduced, and the problem of stronger electromagnetic interference caused by the power supply is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic top view of a display panel according to another embodiment of the present disclosure;
fig. 3 is a schematic partial enlarged structural diagram of a display panel according to an embodiment of the present application;
FIG. 4 is a signal timing diagram of each node of the gate driving circuit shown in FIG. 3;
fig. 5 is a schematic partial enlarged structural diagram of a display panel according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
An embodiment of the present application provides a display panel, as shown in fig. 1, fig. 1 is a schematic view of a top view structure of the display panel, where the display panel includes:
a first substrate 100;
a plurality of display pixels 60 arrayed on the first substrate 100;
a plurality of gate lines 10 electrically connected to the display pixels 60, and a gate driving circuit 50 electrically connected to the gate lines 10;
the gate driving circuit 50 includes a plurality of sequentially connected scan timing segments, the plurality of scan timing segments are sequentially triggered, each scan timing segment corresponds to a row of display pixels 60, and each scan timing segment includes a scan signal timing segment and a floating signal timing segment;
during the scan signal timing segment, the gate driving circuit 50 is configured to provide a scan signal to a current row of display pixels 60, where the current row of display pixels 60 is a row of display pixels 60 corresponding to a currently triggered scan signal timing segment;
during the suspension signal timing segment, the gate driving circuit 50 is configured to electrically connect the gate line 10 connected to the display pixel 60 on the current row with a preset gate line 10, so as to release the residual charge in the display pixel 60 on the current row, and trigger the next scanning timing segment when the suspension signal timing segment ends; the display pixels 60 connected by the preset gate line 10 are not adjacent to the display pixels 60 on the current row.
The gate driving circuit 50 includes a plurality of scan time segments connected in sequence, each scan time segment corresponding to a row of the display pixels 60 in the display panel, so that the gate driving circuit 50 can illuminate the display pixels 60 of the display panel row by row after passing through the scan time segments. In the embodiment, each scan timing segment is further added with a suspension signal timing segment after the normal scan signal timing segment, so that the gate line 10 of the display pixel 60 in the current row is electrically connected to the preset gate line 10 by the gate driving circuit 50 during the suspension signal timing segment, so that the electric charge remaining in the display pixel 60 in the current row after being just lit can be released through the preset gate line 10, thereby avoiding the problem of image sticking of the display panel, and the display panel does not need to be frequently switched to the working state of the charge pump for providing the power voltage by the gate driving circuit 50, thereby avoiding the problem of strong electromagnetic interference caused thereby.
In addition to the gate lines 10, the gate driving circuit 50, the display pixels 60, and the first substrate 100, the data lines 20 and the data driving circuit 40 are also shown in fig. 1.
It should be noted that, a switching circuit (such as the switching selection circuit 30 shown in fig. 1) or an enabling circuit may be disposed between the gate line 10 connecting the display pixels 60 on the current row and the preset gate line 10, so that the gate driving circuit 50 may electrically connect the gate line 10 connecting the display pixels 60 on the current row and the preset gate line 10 through the switching circuit or the enabling circuit during the floating signal timing period.
Optionally, the gate driving circuit 50 is further configured to provide turn-off signals for the display pixels 60 other than the display pixel 60 in the current row, so as to control the pixel circuits in the display pixels 60 to be in a turn-off state, and avoid the problem of false lighting of the display pixels 60 due to the problems of signal crosstalk and the like.
In general, in a display panel, a plurality of display pixels 60 are arranged in an array as N rows of display pixels 60, and it is necessary that N gate lines 10 are connected to the N rows of display pixels 60 respectively in the prior art, but in an embodiment of the present application, referring to fig. 2, fig. 2 is a schematic top view structure diagram of the display panel, the number of the gate lines 10 is N +1, and a plurality of display pixels 60 are arranged as N rows of display pixels 60, and each display pixel 60 is located between two adjacent gate lines 10. In fig. 2, the (N + 1) th gate line 10 is not responsible for transmitting the scan signal to the display pixel 60, and may also be referred to as a dummy gate line 11, and in practical applications, the dummy gate line 11 is only used for providing a drain path of residual charges to the display pixel 60.
When the display pixel 60 in the current row is not the display pixel 60 in the last row, the preset gate line 10 is the gate line 10 in the next row of the gate lines 10 adjacent to the gate line 10 connected to the display pixel 60 in the current row; when the current row of pixels is the last row of display pixels 60, the preset gate line 10 is the previous row of gate lines 10 connected to the gate line 10 of the current row of display pixels 60; that is, the display pixels 60 in N rows are numbered from 1 to N, and the gate lines 10 in N +1 are numbered from 1 to N +1, so that when the number of the display pixels 60 in the current row is i (i ≠ N), the number of the gate line 10 connected to the display pixels 60 in the current row is i, and the number of the preset gate line 10 is i + 2; when the number of the display pixels 60 on the current row is N, the number of the gate line 10 connected to the display pixels 60 on the current row is N, and the number of the preset gate line 10 is N-1. Therefore, the length of the connecting line arranged on the display pixels 60 in the current row or the enabling circuit can be reduced as much as possible, and the problem of short circuit or signal crosstalk possibly caused by too many and too long wires arranged on the display panel can be avoided. However, in other embodiments of the present application, the predetermined numbers of the gate lines 10 may be N + 1. The present application does not limit this, which is determined by the actual situation.
On the basis of the above-mentioned embodiment, in an embodiment of the present application, still referring to fig. 2, the display panel further includes: a selection switch circuit 30 electrically connected to each of the N +1 gate lines 10;
in the time sequence of the floating signal, the gate driving circuit 50 is configured to provide a floating signal for the gate line 10 connected to the display pixel 60 in the current row, and is configured to provide a selection switch signal for the display pixel 60 in the next row of the display pixel 60 in the current row, so that the gate line 10 connected to the display pixel 60 in the current row is electrically connected to a predetermined gate line 10 through the selection switch circuit 30.
The selection switch circuit 30 may be a plurality of semiconductor devices having a switching function, such as thin film transistors or switching diodes, connected to the gate lines 10; one embodiment of the present application provides a feasible structure of the gate driving circuit 50 and the selection switch circuit 30, referring to fig. 3, fig. 3 is a partially enlarged schematic diagram of a display panel, and the selection switch circuit 30 includes N thin film transistors 301 numbered sequentially from 1; wherein,
the gate of the thin film transistor 301 numbered i is electrically connected with the gate line 10 numbered i +1, the source of the thin film transistor 301 numbered i is electrically connected with the gate line 10 numbered i, the drain of the thin film transistor 301 numbered i is electrically connected with the gate line 10 numbered i +2, wherein i is more than or equal to 1 and less than N, and the gate lines 10 are sequentially numbered from 1 in the arrangement order;
the gate of the thin film transistor 301 numbered N is electrically connected to the gate line 10 numbered N +1, the source is electrically connected to the gate line 10 numbered N, and the drain is electrically connected to the gate line 10 numbered N-1;
the selection switch signal is a high level signal.
Still referring to fig. 3, the gate driving circuit 50 includes: n first shift register units 51 and one second shift register unit 52 numbered sequentially from 1; wherein,
the first shift register unit 51 comprises a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first signal output end and a second signal output end;
the second shift register unit 52 comprises a sixth input terminal, a seventh input terminal, a third signal output terminal and a fourth signal output terminal;
a first input end of the first shift register 511 is configured to receive a gate shift signal, a third input end of the first shift register 511 is configured to receive a high level signal, a fourth input end of the first shift register 511 is configured to receive a low level signal, a first signal output end of the first shift register 511 is electrically connected to the gate line 10, and outputs a scan signal during a scan time interval, provides a floating signal during a floating signal time interval, and outputs a low level signal at other times;
a second input end of the first shift register unit 51 with the number 1 is used for receiving a gate start signal, a second signal output end is electrically connected with a second input end of the first shift register unit 51 with the number 2, and a fifth input end is electrically connected with a second signal output end of the first shift register unit 51 with the number 2;
the second input end of the first shift register unit 51 with the number i is electrically connected with the second signal output end of the first shift register unit 51 with the number i-1, the fifth input end is electrically connected with the second signal output end of the first shift register 511 with the number i +1, and i is more than 1 and less than N;
a second input end of the first shift register unit 51 with the number of N is electrically connected with a second signal output end of the first shift register unit 51 with the number of N-1, a fifth input end is electrically connected with a third signal output end of the second shift register unit 52, and a second signal output end is electrically connected with a seventh input end of the second shift register unit 52;
a sixth input terminal of the second shift register unit 52 is configured to receive a gate moving signal, and a fourth signal output terminal of the second shift register unit 52 is electrically connected to the gate line 10 numbered N + 1.
Alternatively, still referring to fig. 3, the first shift register unit 51 includes: a first shift register 511, a first inverter 514, a first transistor Q1, a second transistor Q2, a first and gate 513, and a first or gate 512;
the clock signal input end of the first shift register 511 is used as the first input end of the first shift register unit 51, the input end of the first shift register 511 is used as the second input end of the first shift register unit 51, and the output end of the first shift register 511 is connected to the input end of the first inverter 514 and the first input end of the first and gate 513;
the output terminal of the second inverter 522 is electrically connected to the gate of a first transistor Q1, the drain of the first transistor Q1 is used as the third input terminal of the first shift register unit 51, and the source of the first transistor Q1 is connected to the source of a second transistor Q2 and is used as the first signal output terminal of the first shift register unit 51;
the drain of the second transistor Q2 is used as the fourth input terminal of the first shift register unit 51, and the gate of the second transistor Q2 is connected to the output terminal of the first and gate 513;
a second input end of the first and gate 513 is connected to an output end of the first or gate 512, a first input end of the first or gate 512 is connected to a clock signal input end of the first shift register 511, a second input end of the first or gate 512 of the first shift register 511, which is numbered i, is connected to a second signal output end of the first shift register 511, which is numbered i +1, i is an integer greater than or equal to 1 and less than or equal to N;
the first transistor Q1 is a P-type field effect transistor;
the second transistor Q2 is an N-type field effect transistor.
Alternatively, still referring to fig. 3, the second shift register unit 52 includes a second shift register 521, a second inverter 522, a third transistor Q3, and a fourth transistor Q4; wherein,
the input end of the second shift register 521 is connected to the second signal output end of the first shift register unit 51 with the number N, the clock signal input end of the second shift register 521 serves as the sixth input end of the second shift register unit 52, and the output end of the second register is connected to the input end of the second inverter 522 to serve as the third signal output end of the second shift register unit 52;
an output end of the second inverter 522 is electrically connected with a gate of the third transistor Q3 and a gate of the fourth transistor Q4;
the drain of the third transistor Q3 is used for receiving a high level signal, and the source of the third transistor Q3 is connected to the source of the fourth transistor Q4 as the fourth signal output terminal of the second shift register unit 52;
the drain of the fourth transistor Q4 is used for receiving a low level signal;
the third transistor Q3 is a P-type field effect transistor;
the fourth transistor Q4 is an N-type field effect transistor.
In the display panel shown in fig. 3, the selection switch circuit 30 is formed by N thin film transistors, and the formation processes of the thin film transistors in the pixel circuits of the display pixels 60 in a display panel are matched, so that the selection switch circuit and the thin film transistors can be formed together in the formation process of the thin film transistors of the pixel circuits, which is beneficial to simplifying the preparation process of the display panel.
Referring to fig. 4, fig. 4 is a signal timing diagram of each node of the gate driving circuit 50 shown in fig. 3, in the present embodiment, when the turn-on pulse STV received by the gate driving circuit 50 is at a high level and the driving pulse CPV falls, the signal CG1 inside the gate driving circuit 50 transitions to a low level. Thereafter, each time the driving pulse CPV is decreased, CGm (2. ltoreq. m.ltoreq.N + 1) is sequentially changed to a low level. The duration of the low level coincides with the period t1 of the drive pulse.
In the scan signal timing section, the first transistor Q1Pch1 driving the gate line 10 to a high level signal VGH of a high level and the second transistor Q2 driving the low level signal VGL of a low level are connected. When the first gate control signal Pch m received by the gate of the first transistor Q1 is low, the first transistor Q1 is turned on; when the second gate control signal Nch m received by the gate of the second transistor Q2 is high, the second transistor Q2 is turned on; the waveform of the first gate control signal Pch m is identical to that of CG m, but the waveform of the second gate control signal Nch m delays the time of transition to the high level due to the effects of the first and gate 513 and the first or gate 512 for the same duration as the low level width t2 of the driving pulse CPV. In the process where the first gate control signal Pch m is at a high level and the second gate control signal Nch m is at a low level (the period indicated by oblique lines in fig. 4), both the first transistor Q1 and the second transistor Q2 are turned off, and the output Scan m of the gate line 10 numbered m becomes a suspended signal.
During the duration when the output Scan m of the gate line 10 numbered m becomes the floating signal, the gate line 10 numbered m +1 is driven by the high level VGH, the thin film transistor connected to the mth gate line 10 is turned on, the gate line 10 numbered m and the gate line 10 receiving the off signal (driven by the VGL) (the gate line 10 numbered m + 2) are electrically connected to form a short circuit state, and the charge remaining on the gate line 10 numbered m is discharged. The discharge time of the charges is determined by the duration of the low level of the driving pulse CPV, and the control of the discharge duration of the charges can be achieved by controlling the duration of the low level of the driving pulse CPV.
The specific implementation manner provided by this embodiment can directly perform charge release in the display area of the display panel, and can save devices for controlling the operating state of the charge pump of the power supply of the gate driving circuit 50, reduce the cost of the power supply, and also avoid the problem of electromagnetic interference caused by frequently switching the operating state of the charge pump that provides the power supply voltage for the gate driving circuit 50.
In another embodiment of the present application, as shown in fig. 5, fig. 5 is a schematic top view of a display panel, and the gate driving circuit 50 includes: a signal output module 53 and a selection switch module 54; wherein,
during the scanning signal time sequence segment, the signal output module 53 is configured to provide a scanning signal to a current row of display pixels 60, where the current row of display pixels 60 is a row of display pixels 60 corresponding to the currently triggered scanning signal time sequence segment;
in the time sequence of the floating signal, the signal output module 53 is configured to provide a floating signal for the gate line 10 connected to the display pixel 60 in the current row, and is configured to provide a selection switch signal for the display pixel 60 in the next row of the display pixel 60 in the current row, so as to electrically connect the gate line 10 connected to the display pixel 60 in the current row to a preset gate line 10 through the selection switch module 54.
In the present embodiment, the selection switch module 54 that electrically connects the gate line 10 connecting the display pixels 60 of the current row and the preset gate line 10 is integrated in the gate driving circuit 50, still referring to fig. 5, the selection switch module 54 includes N switching units 541 numbered sequentially from 1; wherein,
the first connection end of the switch unit 541 numbered i is electrically connected with the gate line 10 numbered i +1, the second connection end of the switch unit 541 numbered i is electrically connected with the gate line 10 numbered i, the third connection end of the switch unit 541 numbered i is electrically connected with the gate line 10 numbered i +2, wherein i is more than or equal to 1 and less than N, and the gate lines 10 are sequentially numbered from 1 according to the arrangement sequence;
the first connection end of the switch unit 541 numbered N is electrically connected to the gate line 10 numbered N +1, the second connection end is electrically connected to the gate line 10 numbered N, and the third connection end is electrically connected to the gate line 10 numbered N-1;
the selection switch signal is a high level signal.
Alternatively, still referring to fig. 5, the switching unit 541 includes a first resistor R1 and a fifth transistor Q5;
one end of the first resistor R1 is used as a second connection end of the switch unit 541, and the other end of the first resistor R1 is connected with the source of a fifth transistor Q5;
a gate of the fifth transistor Q5 serves as a first connection terminal of the switch unit 541, and a drain of the fifth transistor Q5 serves as a third connection terminal of the switch unit 541.
Alternatively, still referring to fig. 5, the signal output module 53 includes:
n third shift register units 531 and one fourth shift register unit 532 numbered sequentially from 1; wherein,
the third shift register unit 531 comprises a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first signal output terminal and a second signal output terminal;
the fourth shift register unit 532 includes a sixth input terminal, a seventh input terminal, a third signal output terminal, and a fourth signal output terminal;
a first input end of the third shift register unit 531 is configured to receive a gate moving signal, a third input end of the third shift register unit 531 is configured to receive a high level signal, a fourth input end of the third shift register unit 531 is configured to receive a low level signal, a first signal output end of the third shift register unit 531 is electrically connected to the gate line 10, and outputs a scan signal during a scan period, provides a floating signal during a floating signal period, and outputs a low level signal at other times;
a second input end of the third shift register unit 531 with the number of 1 is used for receiving a gate start signal, a second signal output end is electrically connected with a second input end of the third shift register unit 531 with the number of 2, and a fifth input end is electrically connected with a second signal output end of the third shift register unit 531 with the number of 2;
the second input end of the third shift register unit 531 with the number i is electrically connected with the second signal output end of the third shift register unit 531 with the number i-1, the fifth input end is electrically connected with the second signal output end of the third shift register 5311 with the number i +1, and i is more than 1 and less than N;
a second input end of the third shift register unit 531 with the number N is electrically connected to a second signal output end of the third shift register unit 531 with the number N-1, a fifth input end is electrically connected to a third signal output end of the fourth shift register unit 532, and the second signal output end is electrically connected to a seventh input end of the fourth shift register unit 532;
a sixth input terminal of the fourth shift register unit 532 is configured to receive a gate moving signal, and a fourth signal output terminal of the fourth shift register unit 532 is electrically connected to the gate line 10 numbered N + 1.
Optionally, still referring to fig. 5, the third shift register unit 531 includes: a third shift register 5311, a third inverter 5312, a sixth transistor Q6, a seventh transistor Q7, a second and gate 5314, and a second or gate 5313;
a clock signal input end of the third shift register 5311 is used as a first input end of the third shift register unit 531, an input end of the third shift register 5311 is used as a second input end of the third shift register unit 531, and an output end of the third shift register 5311 is connected to both an input end of the third inverter 5312 and a first input end of the second and gate 5314;
an output terminal of the third inverter 5312 is electrically connected to a gate of a sixth transistor Q6, a drain of the sixth transistor Q6 is used as a third input terminal of the third shift register unit 531, and a source of the sixth transistor Q6 is connected to a source of a seventh transistor Q7 and is used as a first signal output terminal of the third shift register unit 531;
the drain of the seventh transistor Q7 is used as the fourth input terminal of the third shift register unit 531, and the gate of the seventh transistor Q7 is connected to the output terminal of the second and gate 5314;
a second input end of the second and gate 5314 is connected to an output end of the second or gate 5313, a first input end of the second or gate 5313 is connected to a clock signal input end of the third shift register 5311, a second input end of the second or gate 5313 of the third shift register 5311 numbered i is connected to a second signal output end of the third shift register 5311 numbered i +1, i is an integer greater than or equal to 1 and less than or equal to N;
the sixth transistor Q6 is a P-type field effect transistor;
the seventh transistor Q7 is an N-type field effect transistor.
Alternatively, still referring to fig. 5, the fourth shift register unit 532 includes a fourth shift register 5321, a fourth inverter 5322, an eighth transistor Q8, and a ninth transistor Q9; wherein,
an input end of the fourth shift register 5321 is connected to a second signal output end of a fourth shift register unit 532 with the number N, a clock signal input end of the fourth shift register 5321 serves as a sixth input end of the fourth shift register unit 532, and an output end of the fourth shift register 5321 is connected to an input end of the fourth inverter 5322 and serves as a third signal output end of the fourth shift register unit 532;
an output terminal of the fourth inverter 5322 is electrically connected to a gate of the eighth transistor Q8 and a gate of a ninth transistor Q9;
the drain of the eighth transistor Q8 is used for receiving a high level signal, the source of the eighth transistor Q8 is connected to the source of the ninth transistor Q9 as the fourth signal output terminal of the fourth shift register unit 532;
the drain of the ninth transistor Q9 is used for receiving a low level signal;
the eighth transistor Q8 is a P-type field effect transistor;
the ninth transistor Q9 is an N-type field effect transistor.
The main difference between the display panel shown in fig. 5 and the display panel shown in fig. 3 is that the selection switch module 54 is integrated in the gate driving circuit 50, and the switch unit 541 of the selection switch module 54 is formed by the first resistor R1 and the fifth transistor Q5, and since the fifth transistor Q5 is formed simultaneously with other devices of the gate driving circuit 50, it is preferable to use an N-type field effect transistor as the fifth transistor Q5, so that the forming process of the switch unit 541 matches the forming process of the silicon-based semiconductor device, which is beneficial to simplifying the manufacturing process of the display panel.
In the display panel shown in fig. 5, the switch unit 541 further includes a first resistor R1, and the first resistor R1 is used to provide a suitable voltage working environment for the fifth transistor Q5, so as to avoid the problem of abnormal switching state caused by a higher voltage or damage to the fifth transistor Q5 caused by an excessively high voltage.
The signal timing of each node in the gate driving circuit 50 of the display panel shown in fig. 5 is consistent with the signal timing of the gate driving circuit 50 shown in fig. 3, and the working principle of the selection switch module 54 is consistent with the working principle of the selection switch circuit 30 shown in fig. 3, which is not described herein again.
Correspondingly, an embodiment of the present application further provides a display device, including the display panel according to any of the above embodiments.
To sum up, the embodiment of the present application provides a display panel and a display device, wherein, display panel's gate drive circuit includes a plurality of consecutive scanning time sequence sections, and every scanning time sequence section includes scanning signal time sequence section and unsettled signal time sequence section, and when scanning signal time sequence section, gate drive circuit normally provides scanning signal for present row display pixel, and when unsettled signal time sequence section, gate line that gate drive circuit will connect present row display pixel and the electric connection of predetermined gate line to make remaining electric charge can be released through predetermined gate line in the present row display pixel, avoided because remaining electric charge in the display pixel and the display residual image problem that leads to. And because the display panel does not need to be frequently switched to the working state of the charge pump for providing the power supply voltage by the grid drive circuit, and a device for controlling the working state of the charge pump does not need to be arranged in the power supply, the cost of the power supply is reduced, and the problem of stronger electromagnetic interference caused by the power supply is avoided.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A display panel, comprising:
a first substrate;
a plurality of display pixels arranged in an array on the first substrate;
the display device comprises a plurality of gate lines and a gate driving circuit, wherein the gate lines are electrically connected with the display pixels, the gate driving circuit is electrically connected with the gate lines, the number of the gate lines is N +1, the display pixels are arranged into N rows of display pixels, and each display pixel is positioned between two adjacent gate lines;
the grid driving circuit comprises a plurality of scanning time sequence sections which are sequentially connected, the scanning time sequence sections are sequentially triggered, each scanning time sequence section corresponds to one row of display pixels, and each scanning time sequence section comprises a scanning signal time sequence section and a suspension signal time sequence section;
during the scanning signal time sequence section, the gate drive circuit is used for providing scanning signals for the display pixels of the current line, and the display pixels of the current line are the display pixels of the line corresponding to the currently triggered scanning signal time sequence section;
when the suspension signal time sequence section is started, the grid drive circuit is used for electrically connecting the grid line connected with the display pixels on the current line with a preset grid line so as to release residual charges in the display pixels on the current line and trigger the next scanning time sequence section; the display pixels connected with the preset gate lines are not adjacent to the display pixels on the current row;
the selection switch circuit is electrically connected with the N +1 grid lines; during the suspension signal timing section, the gate driving circuit is used for providing suspension signals for the gate lines connected with the display pixels on the current row and providing selection switch signals for the display pixels on the next row of the display pixels on the current row so as to electrically connect the gate lines connected with the display pixels on the current row with the preset gate lines through the selection switch circuit;
the selection switch circuit comprises N thin film transistors which are numbered from 1 in sequence; the grid electrode of the thin film transistor numbered i is electrically connected with the grid line numbered i +1, the source electrode of the thin film transistor numbered i is electrically connected with the grid line numbered i, the drain electrode of the thin film transistor numbered i is electrically connected with the grid line numbered i +2, wherein i is more than or equal to 1 and less than N, and the grid lines are numbered from 1 in sequence; the grid electrode of the thin film transistor with the number of N is electrically connected with the grid line with the number of N +1, the source electrode of the thin film transistor is electrically connected with the grid line with the number of N, and the drain electrode of the thin film transistor is electrically connected with the grid line with the number of N-1; the selection switch signal is a high level signal;
or,
the gate driving circuit includes: the signal output module and the selection switch module; when the scanning signal is in the time sequence section, the signal output module is used for providing a scanning signal for a current row of display pixels, and the current row of display pixels is a row of display pixels corresponding to the currently triggered time sequence section of the scanning signal; during the suspension signal timing segment, the signal output module is used for providing suspension signals for the gate lines connected with the display pixels on the current row and providing selection switch signals for the display pixels on the next row of the display pixels on the current row so as to electrically connect the gate lines connected with the display pixels on the current row with the preset gate lines through the selection switch module;
the selection switch module comprises N switch units which are numbered from 1 in sequence; the first connecting end of the switch unit numbered i is electrically connected with the gate line numbered i +1, the second connecting end of the switch unit numbered i is electrically connected with the gate line numbered i, the third connecting end of the switch unit numbered i is electrically connected with the gate line numbered i +2, wherein i is more than or equal to 1 and less than N, and the gate lines are sequentially numbered from 1 according to the arrangement sequence; the first connecting end of the switch unit with the number of N is electrically connected with the gate line with the number of N +1, the second connecting end is electrically connected with the gate line with the number of N, and the third connecting end is electrically connected with the gate line with the number of N-1; the selection switch signal is a high level signal.
2. The display panel of claim 1, wherein the gate driving circuit is further configured to provide turn-off signals for other display pixels except for the display pixel on the current row.
3. The display panel according to claim 1, wherein the gate driving circuit comprises: n first shift register units and a second shift register unit which are numbered from 1 in sequence; wherein,
the first shift register unit comprises a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first signal output end and a second signal output end;
the second shift register unit comprises a sixth input end, a seventh input end, a third signal output end and a fourth signal output end;
the first input end of the first shift register is used for receiving a grid moving signal, the third input end of the first shift register is used for receiving a high level signal, the fourth input end of the first shift register is used for receiving a low level signal, the first signal output end of the first shift register is electrically connected with the grid line, the scanning signal is output in a scanning time sequence section, the suspension signal is provided in a suspension signal time sequence section, and the low level signal is output in other time;
the second input end of the first shift register unit with the number of 1 is used for receiving a grid starting signal, the second signal output end is electrically connected with the second input end of the first shift register unit with the number of 2, and the fifth input end is electrically connected with the second signal output end of the first shift register unit with the number of 2;
the second input end of the first shift register unit with the number i is electrically connected with the second signal output end of the first shift register unit with the number i-1, the fifth input end of the first shift register unit with the number i +1 is electrically connected with the second signal output end of the first shift register with the number i +1, and i is more than 1 and less than N;
the second input end of the first shift register unit with the number of N is electrically connected with the second signal output end of the first shift register unit with the number of N-1, the fifth input end is electrically connected with the third signal output end of the second shift register unit, and the second signal output end is electrically connected with the seventh input end of the second shift register unit;
and a sixth input end of the second shift register unit is used for receiving a gate moving signal, and a fourth signal output end of the second shift register unit is electrically connected with the gate line with the serial number of N + 1.
4. The display panel according to claim 3, wherein the first shift register unit comprises: the first shift register, the first inverter, the first transistor, the second transistor, the first AND gate and the first OR gate;
a clock signal input end of the first shift register serves as a first input end of the first shift register unit, an input end of the first shift register serves as a second input end of the first shift register unit, and an output end of the first shift register is connected with an input end of the first inverter and a first input end of the first and gate;
the output end of the phase inverter is electrically connected with the grid electrode of a first transistor, the drain electrode of the first transistor is used as the third input end of the first shift register unit, and the source electrode of the first transistor is connected with the source electrode of a second transistor and is used as the first signal output end of the first shift register unit;
the drain electrode of the second transistor is used as a fourth input end of the first shift register unit, and the grid electrode of the second transistor is connected with the output end of the first AND gate;
the second input end of the first AND gate is connected with the output end of the first OR gate, the first input end of the first OR gate is connected with the clock signal input end of the first shift register, the second input end of the first OR gate of the first shift register with the number of i is connected with the second signal output end of the first shift register with the number of i +1, and i is an integer which is greater than or equal to 1 and less than or equal to N;
the first transistor is a P-type field effect transistor;
the second transistor is an N-type field effect transistor.
5. The display panel according to claim 3, wherein the second shift register unit includes a second shift register, a second inverter, a third transistor, and a fourth transistor; wherein,
the input end of the second shift register is connected with the second signal output end of the first shift register unit with the number of N, the clock signal input end of the second shift register is used as the sixth input end of the second shift register unit, and the output end of the second shift register is connected with the input end of the second inverter and is used as the third signal output end of the second shift register unit;
an output end of the second inverter is electrically connected with a grid electrode of the third transistor and a grid electrode of the fourth transistor;
the drain of the third transistor is used for receiving a high-level signal, and the source of the third transistor is connected with the source of the fourth transistor and used as a fourth signal output end of the second shift register unit;
the drain electrode of the fourth transistor is used for receiving a low-level signal;
the third transistor is a P-type field effect transistor;
the fourth transistor is an N-type field effect transistor.
6. The display panel according to claim 1, wherein the switching unit includes a first resistor and a fifth transistor;
one end of the first resistor is used as a second connecting end of the switch unit, and the other end of the first resistor is connected with a source electrode of the fifth transistor;
the grid electrode of the fifth transistor is used as a first connecting end of the switch unit, and the drain electrode of the fifth transistor is used as a third connecting end of the switch unit.
7. The display panel according to claim 1, wherein the signal output module comprises:
n third shift register units and a fourth shift register unit which are numbered in sequence from 1; wherein,
the third shift register unit comprises a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a first signal output end and a second signal output end;
the fourth shift register unit comprises a sixth input end, a seventh input end, a third signal output end and a fourth signal output end;
the first input end of the third shift register unit is used for receiving a grid moving signal, the third input end of the third shift register unit is used for receiving a high level signal, the fourth input end of the third shift register unit is used for receiving a low level signal, the first signal output end of the third shift register unit is electrically connected with the grid line, a scanning signal is output in a scanning time sequence section, a suspension signal is provided in a suspension signal time sequence section, and the low level signal is output at other times;
the second input end of the third shift register unit with the number of 1 is used for receiving a gate start signal, the second signal output end is electrically connected with the second input end of the third shift register unit with the number of 2, and the fifth input end is electrically connected with the second signal output end of the third shift register unit with the number of 2;
the second input end of the third shift register unit with the number i is electrically connected with the second signal output end of the third shift register unit with the number i-1, the fifth input end of the third shift register unit with the number i +1 is electrically connected with the second signal output end of the third shift register unit with the number i +1, and i is more than 1 and less than N;
the second input end of the third shift register unit with the number of N is electrically connected with the second signal output end of the third shift register unit with the number of N-1, the fifth input end of the third shift register unit is electrically connected with the third signal output end of the fourth shift register unit, and the second signal output end of the third shift register unit is electrically connected with the seventh input end of the fourth shift register unit;
and a sixth input end of the fourth shift register unit is used for receiving a gate moving signal, and a fourth signal output end of the fourth shift register unit is electrically connected with the gate line with the serial number of N + 1.
8. The display panel according to claim 7, wherein the third shift register unit comprises: the first shift register, the first inverter, the second transistor, the seventh transistor, the first AND gate and the second OR gate are connected in series;
a clock signal input end of the third shift register is used as a first input end of the third shift register unit, an input end of the third shift register is used as a second input end of the third shift register unit, and an output end of the third shift register is connected with an input end of the third inverter and a first input end of the second and gate;
the output end of the third inverter is electrically connected with the gate of a sixth transistor, the drain of the sixth transistor is used as the third input end of the third shift register unit, and the source of the sixth transistor is connected with the source of a seventh transistor and is used as the first signal output end of the third shift register unit;
the drain electrode of the seventh transistor is used as the fourth input end of the third shift register unit, and the grid electrode of the seventh transistor is connected with the output end of the second AND gate;
the second input end of the second AND gate is connected with the output end of the second OR gate, the first input end of the second OR gate is connected with the clock signal input end of the third shift register, the second input end of the second OR gate of the third shift register with the number of i is connected with the second signal output end of the third shift register with the number of i +1, and i is an integer which is greater than or equal to 1 and less than or equal to N;
the sixth transistor is a P-type field effect transistor;
the seventh transistor is an N-type field effect transistor.
9. The display panel according to claim 8, wherein the fourth shift register unit includes a fourth shift register, a fourth inverter, an eighth transistor, and a ninth transistor; wherein,
the input end of the fourth shift register is connected with the second signal output end of a fourth shift register unit with the number of N, the clock signal input end of the fourth shift register is used as the sixth input end of the fourth shift register unit, and the output end of the fourth shift register is connected with the input end of the fourth inverter and is used as the third signal output end of the fourth shift register unit;
an output end of the fourth inverter is electrically connected with a gate of the eighth transistor and a gate of the ninth transistor;
the drain of the eighth transistor is configured to receive a high-level signal, and the source of the eighth transistor is connected to the source of the ninth transistor and serves as a fourth signal output end of the fourth shift register unit;
the drain electrode of the ninth transistor is used for receiving a low-level signal;
the eighth transistor is a P-type field effect transistor;
the ninth transistor is an N-type field effect transistor.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811099729.3A CN109119016B (en) | 2018-09-20 | 2018-09-20 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811099729.3A CN109119016B (en) | 2018-09-20 | 2018-09-20 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109119016A CN109119016A (en) | 2019-01-01 |
| CN109119016B true CN109119016B (en) | 2021-10-29 |
Family
ID=64859862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811099729.3A Active CN109119016B (en) | 2018-09-20 | 2018-09-20 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109119016B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110930926B (en) * | 2019-12-09 | 2023-07-25 | 厦门天马微电子有限公司 | Display panel driving method, display driving device and electronic equipment |
| CN115223483A (en) * | 2022-07-29 | 2022-10-21 | 上海中航光电子有限公司 | Long pulse generating circuit, display panel, and electronic device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661173A (en) * | 2008-08-27 | 2010-03-03 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN103280199A (en) * | 2013-04-19 | 2013-09-04 | 合肥京东方光电科技有限公司 | Circuit for eliminating shutdown ghost shadows and array substrate |
| CN103632642A (en) * | 2012-08-22 | 2014-03-12 | 三星显示有限公司 | Gate driving circuit and display apparatus having the same |
| CN107731180A (en) * | 2017-09-12 | 2018-02-23 | 昆山龙腾光电有限公司 | Gate driving circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201145238A (en) * | 2010-06-01 | 2011-12-16 | Au Optronics Corp | Display apparatus and method for eliminating ghost thereof |
-
2018
- 2018-09-20 CN CN201811099729.3A patent/CN109119016B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661173A (en) * | 2008-08-27 | 2010-03-03 | 上海天马微电子有限公司 | Liquid crystal display panel |
| CN103632642A (en) * | 2012-08-22 | 2014-03-12 | 三星显示有限公司 | Gate driving circuit and display apparatus having the same |
| CN103280199A (en) * | 2013-04-19 | 2013-09-04 | 合肥京东方光电科技有限公司 | Circuit for eliminating shutdown ghost shadows and array substrate |
| CN107731180A (en) * | 2017-09-12 | 2018-02-23 | 昆山龙腾光电有限公司 | Gate driving circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109119016A (en) | 2019-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10892028B2 (en) | Shift register and method of driving the same, gate driving circuit and display device | |
| US11417256B2 (en) | Shift register unit and driving method thereof, gate drive circuit and display device | |
| US10319452B2 (en) | Shift register units and driving methods, gate driving circuits and touch display devices | |
| US11127478B2 (en) | Shift register unit and driving method thereof, gate driving circuit, and display device | |
| TWI587190B (en) | Touch display apparatus and shift register thereof | |
| US20200184872A1 (en) | Shift register circuit, gate driving circuit and method for driving the same, and display apparatus | |
| CN106898287B (en) | Shift register, driving method thereof and grid driving circuit | |
| CN107731170B (en) | Compensation module, gate driving unit, circuit, driving method of circuit and display device | |
| CN109710113B (en) | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device | |
| US11393384B2 (en) | Shift register circuit, driving method thereof, gate driving circuit, and display apparatus | |
| US11778446B2 (en) | Gate driving unit, gate driving method, gate driving circuit and display device | |
| CN107301833B (en) | Gate driving unit, gate driving circuit, driving method of gate driving circuit and display device | |
| US20160299587A1 (en) | Touch display screen and time division driving method thereof | |
| KR20130005097A (en) | Gate driving circuit | |
| US20190333595A1 (en) | Shift register, driving circuit and display device | |
| CN109671386B (en) | Gate driving unit and driving method thereof, gate driving circuit and display device | |
| CN111243487B (en) | Display panel, driving method of display panel and display device | |
| US11249591B2 (en) | Shift register unit and driving method, gate driver, touch display panel, and touch display device | |
| US20200302845A1 (en) | Shift register unit, driving method thereof, gate driver on array and display apparatus | |
| CN109119016B (en) | Display panel and display device | |
| CN105355186A (en) | Drive circuit, touch display panel, driving method of touch display panel and touch display device | |
| CN108877721A (en) | Shift register cell, gate driving circuit, display device and driving method | |
| CN108389540B (en) | Shifting register unit, grid driving circuit and driving method thereof and display device | |
| CN111149150A (en) | Compensated tri-gate drive circuit, method and display device | |
| US10832614B2 (en) | Resetting circuit, shift register, gate driving circuit and driving method thereof, and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |