CN109101448B - Address extension circuit and I2C communication interface chip with same - Google Patents
Address extension circuit and I2C communication interface chip with same Download PDFInfo
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Abstract
The invention provides an address expansion circuit and an I2C communication interface chip with the same.A first trigger module generates a trigger signal according to a first signal and a second signal, wherein the first signal is a delayed address signal, and the second signal is a clock signal output by a clock line interface end; the second trigger module generates a first address signal according to the first signal, the second signal and the trigger signal; the third trigger module generates a second address signal according to the first signal, the second signal and the trigger signal; the fourth trigger module generates a third address signal according to the first signal, the second signal and the trigger signal; the address encoder generates address codes according to the first address signal, the second address signal and the third address signal, and when the address end is respectively connected with the power end, the grounding end, the data line interface end and the clock line interface end, the address codes generated by the address encoder are different, so that the expansion of the chip address can be realized under the condition of not increasing ports.
Description
Technical Field
The invention relates to the technical field of I2C communication, in particular to an address expansion circuit and an I2C communication interface chip with the same.
Background
The I2C (Inter-Integrated Circuit) bus is a synchronous serial bus developed by philips, which enables data transfer between devices via serial data line SDA and serial clock line SCL. Among them, a device that initializes data transfer of the I2C bus and generates a clock signal allowing the transfer is called a master, and any device that is addressed, i.e., transferred or output, data is called a slave.
Wherein, in order to facilitate the access of the host, each slave needs to have a unique address. In order to mount more slaves on the I2C bus, it is common practice to extend the addresses of the slaves. For example, one type of conventional I2C communication interface chip that can be used as a slave device uses a single port as the address terminal ADDR of the device, and connects the address terminal ADDR to the ground terminal GND or the power supply terminal VDD to distinguish the addresses of the device.
However, even if only two addresses are available for one device, there is a case where the addresses collide due to too few device address selections, however, if the address expansion is achieved by increasing the number of address terminals ADDR, the chip size and test time will increase accordingly, resulting in an increase in the cost of the chip.
Disclosure of Invention
In view of this, the present invention provides an address expansion circuit and an I2C communication interface chip having the same to expand an alternative address of the I2C communication interface chip.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an address expansion circuit is applied to a chip with an I2C communication interface, the chip comprises at least one address end, a power end, a grounding end, a data line interface end and a clock line interface end, the data line interface end is connected with a serial data line in an I2C bus, the clock line interface end is connected with a serial clock line in the I2C bus, the address expansion circuit comprises at least one trigger group and an address encoder, and the trigger group comprises a first trigger module to a fourth trigger module;
the first trigger module is used for generating a trigger signal according to a first signal and a second signal, wherein the first signal is a delayed address signal output by a delay circuit connected with the corresponding address terminal, and the second signal is a clock signal output by the clock line interface terminal;
the second trigger module is used for generating a first address signal according to the first signal, the second signal and the trigger signal; the third trigger module is used for generating a second address signal according to the first signal, the second signal and the trigger signal; the fourth trigger module is used for generating a third address signal according to the first signal, the second signal and the trigger signal;
The address encoder is used for generating address codes according to the first address signal, the second address signal and the third address signal, and when the address end is respectively connected with the power end, the grounding end, the data line interface end and the clock line interface end, the address codes generated by the address encoder are different.
Optionally, the first trigger module includes a first trigger; the second trigger module comprises a second trigger, a first AND gate, a second AND gate, a third AND gate and a third AND gate; the third trigger module comprises a third trigger, a first inverter, a second inverter, a fourth AND gate, a second AND gate, a third AND gate and a sixth AND gate; the first trigger is an asynchronous reset trigger triggered by a rising edge, and the second trigger to the third trigger are asynchronous set triggers triggered by a falling edge;
the input end of the first trigger is connected with the address end through the delay circuit, and the clock signal ends of the first trigger to the third trigger are connected with the clock line interface end;
the first input end of the first AND gate is connected with the output end of the first trigger, and the second input end of the first AND gate is connected with the input end of the first trigger; the first input end of the second AND gate is connected with the output end of the second trigger, the second input end of the second AND gate is connected with the output end of the first AND gate, and the output end of the second AND gate is connected with the input end of the second trigger; the first input end of the third AND gate is connected with the output end of the second trigger, the second input end of the third AND gate is connected with the output end of the first AND gate, and the output end of the third AND gate is connected with the address encoder;
The input end of the first inverter is connected with the output end of the first trigger, the input end of the second inverter is connected with the input end of the first trigger, the first input end of the fourth AND gate is connected with the output end of the first inverter, and the second input end of the fourth AND gate is connected with the output end of the second inverter; the first input end of the fifth AND gate is connected with the output end of the third trigger, the second input end of the fifth AND gate is connected with the output end of the fourth AND gate, and the output end of the fifth AND gate is connected with the input end of the third trigger; the first input end of the sixth AND gate is connected with the output end of the third trigger, the second input end of the sixth AND gate is connected with the output end of the fourth AND gate, and the output end of the sixth AND gate is connected with the address encoder.
Optionally, the fourth trigger module includes a fourth trigger, a third inverter, a seventh and gate to a ninth and gate, where the fourth trigger is an asynchronous set trigger triggered by a falling edge;
the clock signal end of the fourth trigger is connected with the clock line interface end;
The input end of the third inverter is connected with the output end of the first trigger, and the output end of the third inverter is connected with the first input end of the seventh AND gate; the second input end of the seventh AND gate is connected with the input end of the first trigger; the first input end of the eighth AND gate is connected with the output end of the fourth trigger, the second input end of the eighth AND gate is connected with the output end of the seventh AND gate, and the output end of the eighth AND gate is connected with the input end of the fourth trigger; the first input end of the ninth AND gate is connected with the output end of the fourth trigger, the second input end of the ninth AND gate is connected with the output end of the seventh AND gate, and the output end of the ninth AND gate is connected with the address encoder.
Optionally, the fourth trigger module includes a fifth trigger, an exclusive-or gate, a tenth and an eleventh and gate, where the fifth trigger is an asynchronous set trigger triggered by a falling edge;
the clock signal end of the fifth trigger is connected with the clock line interface end;
the first input end of the exclusive-or gate is connected with the output end of the first trigger, and the second input end of the exclusive-or gate is connected with the input end of the first trigger; the first input end of the tenth AND gate is connected with the output end of the fifth trigger, the second input end of the tenth AND gate is connected with the output end of the exclusive-OR gate, and the output end of the tenth AND gate is connected with the input end of the fifth trigger; the first input end of the eleventh AND gate is connected with the output end of the fifth trigger, the second input end of the eleventh AND gate is connected with the output end of the exclusive-or gate, and the output end of the eleventh AND gate is connected with the address encoder.
Optionally, the device further comprises a fifth trigger module, wherein the fifth trigger module is used for generating a fourth address signal according to the first signal, the second signal and the trigger signal; the address encoder is configured to generate an address code from the first address signal, the second address signal, the third address signal, and the fourth address signal.
Optionally, when the fourth trigger module includes a fourth trigger, a third inverter, a seventh and gate, and a ninth and gate, the fifth trigger module includes a fifth trigger, an exclusive-or gate, a tenth and gate, and an eleventh and gate, where the fifth trigger is an asynchronous set trigger triggered by a falling edge;
the clock signal end of the fifth trigger is connected with the clock line interface end;
the first input end of the exclusive-or gate is connected with the output end of the first trigger, and the second input end of the exclusive-or gate is connected with the input end of the first trigger; the first input end of the tenth AND gate is connected with the output end of the fifth trigger, the second input end of the tenth AND gate is connected with the output end of the exclusive-OR gate, and the output end of the tenth AND gate is connected with the input end of the fifth trigger; the first input end of the eleventh AND gate is connected with the output end of the fifth trigger, the second input end of the eleventh AND gate is connected with the output end of the exclusive-or gate, and the output end of the eleventh AND gate is connected with the address encoder.
Optionally, when the fourth trigger module includes a fifth trigger, an exclusive-or gate, a tenth and an eleventh and gate, the fifth trigger module includes a fourth trigger, a third inverter, a seventh and gate to a ninth and gate, and the fourth trigger is an asynchronous setting trigger triggered by a falling edge;
the clock signal end of the fourth trigger is connected with the clock line interface end;
the input end of the third inverter is connected with the output end of the first trigger, and the output end of the third inverter is connected with the first input end of the seventh AND gate; the second input end of the seventh AND gate is connected with the input end of the first trigger; the first input end of the eighth AND gate is connected with the output end of the fourth trigger, the second input end of the eighth AND gate is connected with the output end of the seventh AND gate, and the output end of the eighth AND gate is connected with the input end of the fourth trigger; the first input end of the ninth AND gate is connected with the output end of the fourth trigger, the second input end of the ninth AND gate is connected with the output end of the seventh AND gate, and the output end of the ninth AND gate is connected with the address encoder.
Optionally, the device further comprises a reset module, wherein the reset module outputs a reset signal to the reset end or the set end of all the triggers so as to reset or set the triggers.
Optionally, a first input end of the reset module is connected with the data line interface end, and a second input end of the reset module is connected with the clock line interface end;
the reset module obtains a start signal of data transmission according to the data signal output by the data line interface end and the clock signal output by the clock line interface end, and obtains the reset signal according to the start signal.
An I2C communication interface chip comprising an address expansion circuit as claimed in any one of the preceding claims.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
when the address end is respectively connected with the power end, the grounding end, the data line interface end and the clock line interface end, the address codes generated by the address expansion circuit according to the address signals of the address end are different, that is, the address expansion circuit can generate four different addresses, so that the expansion of the chip address can be realized without adding ports.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an I2C communication system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an address expansion circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a specific structure of the address expanding circuit shown in FIG. 2;
FIG. 4 is a schematic diagram showing another specific structure of the address expanding circuit shown in FIG. 2;
FIG. 5 is a schematic diagram of an address expansion circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram showing a specific structure of the address expanding circuit shown in FIG. 5;
FIG. 7 is a timing diagram of the address expansion circuit when the address terminal ADDR is connected to the power terminal VDD;
FIG. 8 is a timing diagram of the address expansion circuit when the address terminal ADDR is connected to the ground terminal GND;
FIG. 9 is a timing diagram of the address expansion circuit when the address terminal ADDR is connected to the clock line interface terminal SCL;
Fig. 10 is a timing diagram of the address expansion circuit when the address terminal ADDR is connected to the data line interface terminal SDA.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides an address expansion circuit which is applied to an I2C communication interface chip. As shown in fig. 1, the I2C communication interface chip includes at least one address terminal ADDR, a power terminal VDD, a ground terminal GND, a data line interface terminal SDA, and a clock line interface terminal SCL, where the data line interface terminal SDA is connected to a serial data line in the I2C bus, and the clock line interface terminal SCL is connected to a serial clock line in the I2C bus.
That is, the data line interface SDA of the I2C communication interface chip is connected to the data line interface SDA of the host through the serial data line in the I2C bus, and the clock line interface SCL of the I2C communication interface chip is connected to the clock line interface SCL of the host through the serial clock line in the I2C bus, so as to realize data transmission between the host and the slave, i.e., the I2C communication interface chip.
Before starting data transmission, the master sends a start signal start to the slave, and then sends a command byte, where the command byte is composed of a 7-bit address of the slave that needs to transmit data and a 1-bit read-write control bit R/W, and typically, the lowest bit is R/W, and a 0 indicates that the master writes data to the slave, and a 1 indicates that the master reads data from the slave. After receiving the command byte, the slave compares the address in the command with the address of the slave, the slave feeds back a response signal to the host, the host and the slave start to output transmission, the slave does not respond, and the host does not transmit data to the slave.
In the invention, the address of the I2C communication interface chip is expanded through the address expansion circuit to realize 4 addresses through one address end ADDR, and the generated address is transmitted to the processing module of the I2C communication interface chip, so that the processing module compares the address with the address generated by the host. The address extension circuit may be a circuit inside the I2C communication interface chip, or may be a peripheral circuit of the I2C communication interface chip.
In one embodiment, as shown in fig. 2, the address expansion circuit includes at least one trigger group including first through fourth trigger modules 21 through 24 and an address encoder 20. In the embodiment of the present invention, only one address terminal ADDR and one flip-flop group are taken as examples, but the present invention is not limited thereto.
The first trigger module 21 is configured to generate a trigger signal according to a first signal and a second signal, where the first signal is a delayed address signal output by the delay circuit 10 connected to the corresponding address terminal ADDR, and the second signal is a clock signal output by the clock line interface terminal SCL of the I2C communication interface chip; the second trigger module 22 is configured to generate a first address signal according to the first signal, the second signal and the trigger signal; the third trigger module 23 is configured to generate a second address signal according to the first signal, the second signal, and the trigger signal; the fourth trigger module 24 is configured to generate a third address signal according to the first signal, the second signal, and the trigger signal; the address encoder 20 is configured to generate address codes according to the first address signal, the second address signal, and the third address signal, and when the address terminal ADDR of the I2C communication interface chip is connected to the power terminal VDD, the ground terminal GND, the data line interface terminal SDA, and the clock line interface terminal SCL of the I2C communication interface chip, respectively, the address codes generated by the address encoder 20 are different.
Based on the above, the address expansion circuit provided by the embodiment of the invention can generate four different addresses, so that the expansion of the chip address can be realized without adding ports. It should be noted that, in the embodiment of the present invention, each trigger set is correspondingly connected to one address terminal ADDR, and all trigger sets are connected to the address encoder 20. The address encoder 20 generates an address code from the first address signal, the second address signal, and the third address signal output from all the flip-flop groups. That is, when the chip includes N address terminals ADDR, the address expansion circuit includes N flip-flop groups, generating 4 N Each of which is a different address.
On the basis of the above embodiment, as shown in fig. 3 and 4, the address expansion circuit further includes a reset module 11, and the reset module 11 outputs a reset signal to the reset terminal R or the set terminal S of all the flip-flops to reset or set the flip-flops. The first input end of the reset module 11 is connected to the data line interface end SDA, and the second input end of the reset module 11 is connected to the clock line interface end SCL.
The reset module 11 obtains a start signal start of data transmission according to a data signal output by the data line interface end SDA and a clock signal output by the clock line interface end SCL, and obtains a reset signal after inverting the start signal start. That is, the reset module 11 detects a start signal start transmitted from the master to the slave through the I2C bus, and obtains a reset signal according to the start signal start. In order to prevent the address expansion circuit from being abnormally locked before the I2C bus transmits the valid data, the falling edge of the start pulse signal has a delay of T time relative to the first falling edge of the SCL clock signal, T is less than T/2, and T is a period of one clock signal.
In one embodiment, as shown in fig. 3, the first trigger module 21 includes a first trigger 210; the second trigger module 22 includes a second trigger 220, a first and gate 221 to a third and gate 223; the third trigger module 23 includes a third trigger 230, a first inverter 231, a second inverter 232, a fourth and gate 233 to a sixth and gate 235; the fourth trigger module 24 includes a fourth trigger 240, a third inverter 241, seventh to ninth and gates 242 to 244; the first flip-flop 210 is a rising edge triggered asynchronous reset flip-flop, and the second, third and fourth flip-flops 220, 230 and 240 are falling edge triggered asynchronous set flip-flops.
An input terminal D1 of the first flip-flop 210 is connected to the address terminal ADDR through the delay circuit 10, and clock signal terminals CLK of the first flip-flop 210, the second flip-flop 220, the third flip-flop 230, and the fourth flip-flop 240 are all connected to the clock line interface terminal SCL;
a first input of the first and gate 221 is connected to an output of the first flip-flop 210, and a second input of the first and gate 221 is connected to an input of the first flip-flop 210; the first input end of the second and gate 222 is connected to the output end of the second trigger 220, the second input end of the second and gate 222 is connected to the output end of the first and gate 221, and the output end of the second and gate 222 is connected to the input end of the second trigger 220; a first input of the third and gate 223 is connected to an output of the second flip-flop 220, a second input of the third and gate 223 is connected to an output of the first and gate 221, and an output of the third and gate 223 is connected to the address encoder 20;
an input terminal of the first inverter 231 is connected to an output terminal of the first flip-flop 210, an input terminal of the second inverter 232 is connected to an input terminal of the first flip-flop 210, a first input terminal of the fourth and gate 233 is connected to an output terminal of the first inverter 210, and a second input terminal of the fourth and gate 233 is connected to an output terminal of the second inverter 232; a first input of the fifth and gate 234 is connected to an output of the third flip-flop 230, a second input of the fifth and gate 234 is connected to an output of the fourth and gate 233, and an output of the fifth and gate 234 is connected to an input of the third flip-flop 230; a first input of the sixth and gate 235 is connected to an output of the third flip-flop 230, a second input of the sixth and gate 235 is connected to an output of the fourth and gate 233, and an output of the sixth and gate 235 is connected to the address encoder 20.
An input terminal of the third inverter 241 is connected to the output terminal of the first flip-flop 210, and an output terminal of the third inverter 241 is connected to a first input terminal of the seventh and gate 242; a second input of the seventh and gate 242 is connected to an input of the first flip-flop 210; a first input of the eighth and gate 243 is connected to the output of the fourth flip-flop 240, a second input of the eighth and gate 243 is connected to the output of the seventh and gate 242, and an output of the eighth and gate 243 is connected to the input of the fourth flip-flop 240; a first input of the ninth and gate 244 is connected to the output of the fourth flip-flop 240, a second input of the ninth and gate 244 is connected to the output of the seventh and gate 242, and an output of the ninth and gate 244 is connected to the address encoder 20.
The operation of the address expansion circuit shown in fig. 3 will be described below.
First, the host transmits a start signal start, and the reset module 11 outputs a reset signal to reset or set the first, second, third and fourth flip-flops 210, 220, 230 and 240. Since the first flip-flop 210 is an asynchronous reset flip-flop triggered by a rising edge, the second flip-flop 220, the third flip-flop 230, and the fourth flip-flop 240 are asynchronous set flip-flops triggered by a falling edge, the potential of the output terminal Q1 of the first flip-flop 210 after reset is low level 0, and the potential of the second flip-flop 220, the third flip-flop 230, and the fourth flip-flop 240 after set is high level 1.
When the address terminal ADDR is connected to the power supply terminal VDD, the first signal is always at a high level 1, and referring to fig. 3 and 7, the input terminal D1 of the first flip-flop 210 is inputted with a high level 1, and since the first flip-flop 210 is an asynchronous reset flip-flop triggered by a rising edge, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, is changed from a low level to a high level, i.e., from 0 to 1, the input terminal of the first flip-flop 210 is at a high level 1, and the output terminal Q1 outputs a high level 1;
when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from high to low, i.e., from 1 to 0, since the input terminal of the first flip-flop 210 is high 1 and the output terminal Q1 is high 1, the first and gate 221 outputs high 1, and the first input terminal of the second and gate 222 and the output terminal Q2 of the second flip-flop 220 have the same potential, i.e., high 1, so that the second and gate 222 outputs high 1, so that the output terminal Q2 of the second flip-flop 220 outputs high 1, and the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1;
also, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the first inverter 231 outputs low 0, the second inverter 232 outputs low 0, and the fourth and gate 233, the fifth and gate 234, the third inverter 230, and the sixth and gate 235 output low 0, i.e., the second address signal ID [2] =0;
Also, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the third inverter 241 outputs low 0, so that the seventh and gate 242, the eighth and gate 243, the fourth flip-flop 240, and the ninth and gate 244 output low 0, i.e., the third address signal ID [3] =0.
When the address terminal ADDR is connected to the ground terminal GND, the first signal is always at a low level 0, referring to fig. 3 and 8, the output terminal Q1 of the first flip-flop 210 outputs a low level 0, the third and gate 223 outputs a low level 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs a high level 1, i.e., the second address signal ID [2] =1, and the ninth and gate 244 outputs a low level 0, i.e., the third address signal ID [3] =0.
When the address terminal ADDR is connected to the clock line interface terminal SCL, referring to fig. 3 and 9, the first signal is identical to the clock signal input by the clock line interface terminal SCL, but since the first signal is delayed from the clock signal, the input terminal D1 of the first flip-flop 210 is always low 0 when the clock signal of the clock line interface terminal SCL, i.e., the second signal, is changed from low level to high level, i.e., from 0 to 1, and therefore, the output terminal Q1 of the first flip-flop 210 outputs low level 0. When the clock signal of the clock line interface SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is high 1, the output terminal Q1 outputs low 0, so that the third and gate 223 outputs low 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e., the second address signal ID [2] =0, and the ninth and gate 244 outputs high 1, i.e., the third address signal ID [3] =1.
When the address terminal ADDR is connected to the data line interface terminal SDA, referring to fig. 3 and 10, the first signal is identical to the data signal inputted from the data line interface terminal SDA, and both the rising edge and the falling edge of the flip-flop will be sampled to the same value according to the I2C timing. As shown in fig. 10, at the first timing, when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from low to high, i.e., from 0 to 1, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed to high 1, so that the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1, and the sixth and gate 235 outputs low 0, i.e., the second address signal ID [2] =0, and the ninth and gate 244 outputs low 0, i.e., the third address signal ID [3] =0. Since the outputs of the third flip-flop 230 and the fourth flip-flop 240 are both 0, the result will be locked until the next arrival of the reset signal by the fifth and gate 234 and the eighth and gate 243. However, since id=100 at this time is the same as the ID when the address terminal ADDR is connected to the power source terminal VDD, this ID is not used. In the first 7 timings, the input terminal D1 of the first flip-flop 210 may be also low 0, the output terminal Q1 is low 0, so that the third and gate 223 outputs low 0, i.e. the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e. the second address signal ID [2] =0, and the ninth and gate 244 outputs low 0, i.e. the third address signal ID [3] =0.
That is, when the address terminal ADDR is connected to the power supply terminal VDD, the address id=100 outputted from the address expansion circuit; when the address terminal ADDR is connected to the ground terminal GND, the address id=010 outputted from the address expansion circuit; when the address terminal ADDR is connected to the clock line interface terminal SCL, the address id=001 outputted from the address expansion circuit; when the address terminal ADDR is connected to the data line interface terminal SDA, the address id=000 outputted from the address expansion circuit. The address encoder 20 then generates a 7-bit address based on the corresponding address ID so that the processing module compares the address with the address at which the host occurred.
In another embodiment, as shown in fig. 4, unlike the address expansion circuit shown in fig. 3, in the address expansion circuit shown in fig. 4, the fourth trigger module 24 includes a fifth trigger 250, an exclusive-or gate 251, a tenth and an eleventh and gates 252 and 253, and the fifth trigger 250 is an asynchronous set trigger triggered by a falling edge.
The clock signal terminal CLK5 of the fifth flip-flop 250 is connected to the clock line interface terminal SCL. A first input terminal of the exclusive-or gate 251 is connected to the output terminal of the first flip-flop 210, and a second input terminal of the exclusive-or gate 251 is connected to the input terminal of the first flip-flop 210; a first input terminal of the tenth and gate 252 is connected to an output terminal of the fifth flip-flop 250, a second input terminal of the tenth and gate 252 is connected to an output terminal of the exclusive-or gate 251, and an output terminal of the tenth and gate 252 is connected to an input terminal of the fifth flip-flop 250; a first input of the eleventh and gate 253 is connected to the output of the fifth flip-flop 250, a second input of the eleventh and gate 253 is connected to the output of the exclusive-or gate 251, and an output of the eleventh and gate 253 is connected to the address encoder 20.
The operation of the address expansion circuit shown in fig. 4 will be described below.
Also, the host first sends a start signal start, and the reset module 11 outputs a reset signal to reset or set the first, second, third and fifth flip-flops 210, 220, 230 and 250. Since the first flip-flop 210 is an asynchronous reset flip-flop triggered by a rising edge, the second flip-flop 220, the third flip-flop 230, and the fifth flip-flop 250 are asynchronous set flip-flops triggered by a falling edge, the potential of the output terminal Q1 of the first flip-flop 210 after reset is low level 0, and the potential of the second flip-flop 220, the third flip-flop 230, and the fifth flip-flop 250 after set is high level 1.
When the address terminal ADDR is connected to the power terminal VDD, the first signal is always at a high level 1, and referring to fig. 4 and 7, the input terminal D1 of the first flip-flop 210 is inputted with a high level 1, and since the first flip-flop 210 is an asynchronous reset flip-flop triggered by a rising edge, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, is changed from a low level to a high level, i.e., from 0 to 1, the input terminal of the first flip-flop 210 is latched at a high level 1, and the output terminal Q1 outputs a high level 1. Since the input terminal of the first flip-flop 210 is at the high level 1 and the output terminal Q1 is at the high level 1, the first and gate 221 outputs the high level 1, and the first input terminal of the second and gate 222 and the output terminal Q2 of the second flip-flop 220 have the same potential, i.e., the high level 1, so that the second and gate 222 outputs the high level 1. When the clock signal of the clock line interface SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the output terminal Q2 of the second flip-flop 220 outputs high 1, so that the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1. Meanwhile, the sixth and gate 235 outputs a low level 0, i.e., the second address signal ID [2] =0, and the eleventh and gate 253 outputs a high level 1, i.e., the third address signal ID [3] =1.
When the address terminal ADDR is connected to the ground terminal GND, the first signal is always at a low level 0, and referring to fig. 4 and 8, the output terminal Q1 of the first flip-flop 210 outputs a low level 0, the third and gate 223 outputs a low level 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs a high level 1, i.e., the second address signal ID [2] =1, and the eleventh and gate 253 outputs a high level 1, i.e., the third address signal ID [3] =1.
When the address terminal ADDR is connected to the clock line interface terminal SCL, referring to fig. 4 and 9, the first signal is identical to the clock signal input by the clock line interface terminal SCL, but since the first signal is delayed from the clock signal, the input terminal D1 of the first flip-flop 210 is always low 0 when the clock signal of the clock line interface terminal SCL, i.e., the second signal, is changed from low level to high level, i.e., from 0 to 1, and thus the output terminal Q1 of the first flip-flop 210 outputs low level 0. When the clock signal of the clock line interface SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is high 1, the output terminal Q1 outputs low 0, so that the third and gate 223 outputs low 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e., the second address signal ID [2] =0, and the eleventh and gate 253 outputs low 0, i.e., the third address signal ID [3] =0.
When the address terminal ADDR is connected to the data line interface terminal SDA, referring to fig. 4 and 10, the first signal is identical to the data signal inputted from the data line interface terminal SDA, and both the rising edge and the falling edge of the flip-flop will be sampled to the same value according to the I2C timing. As shown in fig. 10, at the first timing, when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from low to high, i.e., from 0 to 1, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed to high 1, and when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed to high 1, so that the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1. Since the output of the third flip-flop 230 is 0, i.e. the second address signal ID 2=0, the result will be locked until the next arrival of the reset signal. With the fifth flip-flop 250, since the values of the input terminal D1 and the output terminal Q1 of the first flip-flop 210 are the same, the eleventh and gate 253 outputs the high level 1, that is, the third address signal ID [3] =1. However, since id=101 at this time is the same as the ID when the address terminal ADDR is connected to the power source terminal VDD, this ID is not used any more. In the first 7 timings, the input terminal D1 of the first flip-flop 210 may be also low 0, the output terminal Q1 is low 0, so that the third and gate 223 outputs low 0, i.e. the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e. the second address signal ID [2] =0, and the eleventh and gate 253 outputs high 1, i.e. the third address signal ID [3] =1.
That is, when the address terminal ADDR is connected to the power supply terminal VDD, the address id=101 outputted from the address expansion circuit; when the address terminal ADDR is connected to the ground terminal GND, the address id=011 outputted by the address expansion circuit; when the address terminal ADDR is connected to the clock line interface terminal SCL, the address id=000 outputted from the address expansion circuit; when the address terminal ADDR is connected to the data line interface terminal SDA, the address id=001 outputted from the address expansion circuit.
In another embodiment, as shown in fig. 5, the apparatus further includes a fifth trigger module 25, where the fifth trigger module 25 is configured to generate a fourth address signal according to the first signal, the second signal, and the trigger signal; the address encoder 20 is configured to generate address codes based on the first address signal, the second address signal, the third address signal, and the fourth address signal, and the address codes generated by the address encoder 20 are different when the address terminal ADDR is connected to the power terminal VDD, the ground terminal GND, the data line interface terminal SDA, and the clock line interface terminal SCL, respectively.
As shown in fig. 6, when the fourth trigger module 24 includes the fourth trigger 240, the third inverter 241, the seventh and gate 242 to the ninth and gate 244, the fifth trigger module 25 includes the fifth trigger 250, the exclusive-or gate 251, the tenth and gate 252, and the eleventh and gate 253. Alternatively, when the fourth trigger module 24 includes the fifth trigger 250, the exclusive-or gate 251, the tenth and gate 252, and the eleventh and gate 253, the fifth trigger module 25 includes the fourth trigger 240, the third inverter 241, the seventh and gate 242 to the ninth and gate 244.
The operation of the address expansion circuit shown in fig. 6 will be described below.
Similarly, the host first sends a start signal start, and the reset module 11 outputs a reset signal to reset or set the first flip-flop 210, the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240, and the fifth flip-flop 250. Since the first flip-flop 210 is an asynchronous reset flip-flop triggered by a rising edge, the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240, and the fifth flip-flop 250 are asynchronous set flip-flops triggered by a falling edge, the potential of the output terminal Q1 of the first flip-flop 210 after reset is low level 0, and the potential of the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240, and the fifth flip-flop 250 after set is high level 1.
When the address terminal ADDR is connected to the power terminal VDD, referring to fig. 6 and 7, the first signal is always at the high level 1, the input terminal D1 of the first flip-flop 210 is inputted with the high level 1, and since the first flip-flop 210 is an asynchronous reset flip-flop triggered by the rising edge, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, is changed from the low level to the high level, i.e., from 0 to 1, the input terminal of the first flip-flop 210 is latched at the high level 1, and the output terminal Q1 outputs the high level 1. Since the input terminal of the first flip-flop 210 is at the high level 1 and the output terminal Q1 is at the high level 1, the first and gate 221 outputs the high level 1, and the first input terminal of the second and gate 222 and the output terminal Q2 of the second flip-flop 220 have the same potential, i.e., the high level 1, so that the second and gate 222 outputs the high level 1. When the clock signal of the clock line interface SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the output terminal Q2 of the second flip-flop 220 outputs high 1, so that the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1. Meanwhile, the sixth and gate 235 outputs a low level 0, i.e., the second address signal ID [2] =0, the ninth and gate 244 outputs a low level 0, i.e., the third address signal ID [3] =0, and the eleventh and gate 253 outputs a high level 1, i.e., the fourth address signal ID [4] =1.
When the address terminal ADDR is connected to the ground terminal GND, the first signal is always at a low level 0, referring to fig. 6 and 8, the output terminal Q1 of the first flip-flop 210 outputs a low level 0, the third and gate 223 outputs a low level 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs a high level 1, i.e., the second address signal ID [2] =1, the ninth and gate 244 outputs a low level 0, i.e., the third address signal ID [3] =0, and the eleventh and gate 253 outputs a high level 1, i.e., the fourth address signal ID [4] =1.
When the address terminal ADDR is connected to the clock line interface terminal SCL, referring to fig. 6 and 9, the first signal is identical to the clock signal input by the clock line interface terminal SCL, but since the first signal has a certain delay from the clock signal, when the clock signal of the clock line interface terminal SCL, i.e., the second signal, changes from low level to high level, i.e., from 0 to 1, the input terminal D1 of the first flip-flop 210 is always low level 0, and therefore, the output terminal Q1 of the first flip-flop 210 outputs low level 0. When the clock signal of the clock line interface SCL, i.e., the second signal, changes from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is high 1, the output terminal Q1 outputs low 0, so that the third and gate 223 outputs low 0, i.e., the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e., the second address signal ID [2] =0, the ninth and gate 244 outputs high 1, i.e., the third address signal ID [3] =1, and the eleventh and gate 253 outputs low 0, i.e., the fourth address signal ID [4] =0.
When the address terminal ADDR is connected to the data line interface terminal SDA, referring to fig. 6 and 10, the first signal is identical to the data signal inputted from the data line interface terminal SDA, and both the rising edge and the falling edge of the flip-flop will be sampled to the same value according to the I2C timing. As shown in fig. 10, at the first timing, when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from low to high, i.e., from 0 to 1, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed to high 1, and when the clock signal of the clock line interface SCL, i.e., the second signal, is changed from high to low, i.e., from 1 to 0, the input terminal D1 of the first flip-flop 210 is changed to high 1, the output terminal Q1 is changed to high 1, so that the third and gate 223 outputs high 1, i.e., the first address signal ID [1] =1. Since the outputs of the third flip-flop 230 and the fourth flip-flop 240 are both 0, i.e. the second address signal ID [2] =0 and the third address signal ID [3] =0, the result will be locked until the next arrival of the reset signal. With the fifth flip-flop 250, since the values of the input terminal D1 and the output terminal Q1 of the first flip-flop 210 are the same, the eleventh and gate 253 outputs the high level 1, that is, the fourth address signal ID [4] =1. However, since id=1001 at this time is the same as the ID when the address terminal ADDR is connected to the power source terminal VDD, this ID is not used any more. In the first 7 timings, the input terminal D1 of the first flip-flop 210 may be also low 0, the output terminal Q1 is low 0, so that the third and gate 223 outputs low 0, i.e. the first address signal ID [1] =0, the sixth and gate 235 outputs low 0, i.e. the second address signal ID [2] =0, the ninth and gate 244 outputs low 0, i.e. the third address signal ID [3] =0, and the eleventh and gate 253 outputs high 1, i.e. the fourth address signal ID [4] =1.
That is, when the address terminal ADDR is connected to the power supply terminal VDD, the address id=1001 outputted by the address expansion circuit; when the address terminal ADDR is connected to the ground terminal GND, the address id=0101 outputted from the address expansion circuit; when the address terminal ADDR is connected to the clock line interface terminal SCL, the address id=0010 output by the address expansion circuit; when the address terminal ADDR is connected to the data line interface terminal SDA, the address id=0001 outputted from the address expansion circuit.
It should be noted that, since the output terminals of the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240 and the fifth flip-flop 250 are all connected to the input terminals thereof through an and gate, when the output terminals of the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240 and the fifth flip-flop 250 are 0, the output terminals of the second flip-flop 220, the third flip-flop 230, the fourth flip-flop 240 and the fifth flip-flop 250 are locked in the state of outputting 0, thereby enhancing the anti-interference performance of the address expansion circuit.
The embodiment of the invention also provides an I2C communication interface chip, which comprises the address expansion circuit provided by any embodiment.
When the address end is respectively connected with the power end, the grounding end, the data line interface end and the clock line interface end, the address codes generated by the address expansion circuit are different, that is, the address expansion circuit can generate four different addresses, so that the expansion of the chip address can be realized under the condition of not increasing ports. The address expansion circuit has the advantages of less logic, simple structure, strong circuit anti-interference capability and the like.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An address expansion circuit is applied to a chip with an I2C communication interface, the chip comprises at least one address end, a power end, a grounding end, a data line interface end and a clock line interface end, the data line interface end is connected with a serial data line in an I2C bus, and the clock line interface end is connected with a serial clock line in the I2C bus, and the address expansion circuit is characterized by comprising at least one trigger group and an address encoder, wherein the trigger group comprises a first trigger module, a second trigger module, a third trigger module and a fourth trigger module;
The first trigger module is used for generating a trigger signal according to a first signal and a second signal, wherein the first signal is a delayed address signal output by a delay circuit connected with the corresponding address terminal, and the second signal is a clock signal output by the clock line interface terminal;
the second trigger module is used for generating a first address signal according to the first signal, the second signal and the trigger signal; the third trigger module is used for generating a second address signal according to the first signal, the second signal and the trigger signal; the fourth trigger module is used for generating a third address signal according to the first signal, the second signal and the trigger signal;
the address encoder is used for generating address codes according to the first address signal, the second address signal and the third address signal, and when the address end is respectively connected with the power end, the grounding end, the data line interface end and the clock line interface end, the address codes generated by the address encoder are different;
the first trigger module comprises a first trigger; the second trigger module comprises a second trigger, a first AND gate, a second AND gate and a third AND gate; the first trigger is an asynchronous reset trigger triggered by a rising edge, and the second trigger is an asynchronous set trigger triggered by a falling edge;
The input end of the first trigger is connected with the address end through the delay circuit, and the clock signal ends of the first trigger and the second trigger are connected with the clock line interface end;
the first input end of the first AND gate is connected with the output end of the first trigger, and the second input end of the first AND gate is connected with the input end of the first trigger; the first input end of the second AND gate is connected with the output end of the second trigger, the second input end of the second AND gate is connected with the output end of the first AND gate, and the output end of the second AND gate is connected with the input end of the second trigger; the first input end of the third AND gate is connected with the output end of the second trigger, the second input end of the third AND gate is connected with the output end of the first AND gate, and the output end of the third AND gate is connected with the address encoder.
2. The address expansion circuit of claim 1, wherein the third trigger module comprises a third trigger, a first inverter, a second inverter, a fourth and gate, a fifth and sixth and gate; the first trigger is an asynchronous reset trigger triggered by a rising edge, and the second trigger to the third trigger are asynchronous set triggers triggered by a falling edge;
The clock signal ends of the first trigger, the second trigger and the third trigger are all connected with the clock line interface end;
the input end of the first inverter is connected with the output end of the first trigger, the input end of the second inverter is connected with the input end of the first trigger, the first input end of the fourth AND gate is connected with the output end of the first inverter, and the second input end of the fourth AND gate is connected with the output end of the second inverter; the first input end of the fifth AND gate is connected with the output end of the third trigger, the second input end of the fifth AND gate is connected with the output end of the fourth AND gate, and the output end of the fifth AND gate is connected with the input end of the third trigger; the first input end of the sixth AND gate is connected with the output end of the third trigger, the second input end of the sixth AND gate is connected with the output end of the fourth AND gate, and the output end of the sixth AND gate is connected with the address encoder.
3. The address expansion circuit of claim 2, wherein the fourth flip-flop comprises a fourth flip-flop, a third inverter, a seventh and gate, an eighth and gate, and a ninth and gate, the fourth flip-flop being a falling edge triggered asynchronous set flip-flop;
The clock signal end of the fourth trigger is connected with the clock line interface end;
the input end of the third inverter is connected with the output end of the first trigger, and the output end of the third inverter is connected with the first input end of the seventh AND gate; the second input end of the seventh AND gate is connected with the input end of the first trigger; the first input end of the eighth AND gate is connected with the output end of the fourth trigger, the second input end of the eighth AND gate is connected with the output end of the seventh AND gate, and the output end of the eighth AND gate is connected with the input end of the fourth trigger; the first input end of the ninth AND gate is connected with the output end of the fourth trigger, the second input end of the ninth AND gate is connected with the output end of the seventh AND gate, and the output end of the ninth AND gate is connected with the address encoder.
4. The address expansion circuit of claim 2, wherein the fourth flip-flop module comprises a fifth flip-flop, an exclusive nor gate, a tenth and an eleventh and gate, the fifth flip-flop being a falling edge triggered asynchronous set flip-flop;
the clock signal end of the fifth trigger is connected with the clock line interface end;
The first input end of the exclusive-or gate is connected with the output end of the first trigger, and the second input end of the exclusive-or gate is connected with the input end of the first trigger; the first input end of the tenth AND gate is connected with the output end of the fifth trigger, the second input end of the tenth AND gate is connected with the output end of the exclusive-OR gate, and the output end of the tenth AND gate is connected with the input end of the fifth trigger; the first input end of the eleventh AND gate is connected with the output end of the fifth trigger, the second input end of the eleventh AND gate is connected with the output end of the exclusive-or gate, and the output end of the eleventh AND gate is connected with the address encoder.
5. The address expansion circuit of any one of claims 1 to 4, further comprising a fifth trigger module for generating a fourth address signal based on the first signal, the second signal, and the trigger signal; the address encoder is configured to generate an address code from the first address signal, the second address signal, the third address signal, and the fourth address signal.
6. The address expansion circuit of claim 5, wherein when the fourth trigger module comprises a fourth trigger, a third inverter, a seventh and gate, an eighth and gate, and a ninth and gate, the fifth trigger module comprises a fifth trigger, an exclusive or gate, a tenth and gate, and an eleventh and gate, the fifth trigger is a falling edge triggered asynchronous set trigger;
The clock signal end of the fifth trigger is connected with the clock line interface end;
the first input end of the exclusive-or gate is connected with the output end of the first trigger, and the second input end of the exclusive-or gate is connected with the input end of the first trigger; the first input end of the tenth AND gate is connected with the output end of the fifth trigger, the second input end of the tenth AND gate is connected with the output end of the exclusive-OR gate, and the output end of the tenth AND gate is connected with the input end of the fifth trigger; the first input end of the eleventh AND gate is connected with the output end of the fifth trigger, the second input end of the eleventh AND gate is connected with the output end of the exclusive-or gate, and the output end of the eleventh AND gate is connected with the address encoder.
7. The address expansion circuit of claim 5, wherein when the fourth trigger module comprises a fifth trigger, an exclusive-or gate, a tenth and an eleventh and gate, the fifth trigger module comprises a fourth trigger, a third inverter, a seventh and gate, an eighth and a ninth and gate, the fourth trigger is a falling edge triggered asynchronous set trigger;
The clock signal end of the fourth trigger is connected with the clock line interface end;
the input end of the third inverter is connected with the output end of the first trigger, and the output end of the third inverter is connected with the first input end of the seventh AND gate; the second input end of the seventh AND gate is connected with the input end of the first trigger; the first input end of the eighth AND gate is connected with the output end of the fourth trigger, the second input end of the eighth AND gate is connected with the output end of the seventh AND gate, and the output end of the eighth AND gate is connected with the input end of the fourth trigger; the first input end of the ninth AND gate is connected with the output end of the fourth trigger, the second input end of the ninth AND gate is connected with the output end of the seventh AND gate, and the output end of the ninth AND gate is connected with the address encoder.
8. The address extension circuit of claim 1, further comprising a reset module that outputs a reset signal to a reset or set terminal of all flip-flops to reset or set the flip-flops.
9. The address expansion circuit of claim 8, wherein a first input of the reset module is coupled to the data line interface and a second input of the reset module is coupled to the clock line interface;
The reset module obtains a start signal of data transmission according to the data signal output by the data line interface end and the clock signal output by the clock line interface end, and obtains the reset signal according to the start signal.
10. An I2C communication interface chip comprising the address expansion circuit of any one of claims 1 to 9.
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