CN109089029A

CN109089029A - A kind of Gige Vision interface image Transmission system and method based on FPGA

Info

Publication number: CN109089029A
Application number: CN201811029173.0A
Authority: CN
Inventors: 易清明; 陈若峰; 石敏
Original assignee: Jinan University
Current assignee: Jinan University
Priority date: 2018-09-05
Filing date: 2018-09-05
Publication date: 2018-12-25
Anticipated expiration: 2038-09-05
Also published as: CN109089029B

Abstract

The invention discloses an FPGA-based Gige Vision interface image transmission system and method, including an image sensor, a host computer, a local Gigabit Ethernet network, and an embedded image acquisition device based on the Gige interface, wherein the embedded image The acquisition device is the core device of the system, including the FPGA chip and the PHY chip; the FPGA signal input terminal is connected to the image sensor output signal terminal; the FPGA and the PHY chip are connected to each other; the PHY chip is connected to the RJ45 interface, and the RJ45 interface is connected to the PC through a network cable. The upper computer is connected. The image acquisition embedded system based on the FPGA and Gige interface realized by the present invention has high transmission efficiency and long transmission distance, and compared with similar IP cores in the industry, it has the advantages of occupying less logic resources and lower hardware requirements.

Description

A kind of Gige Vision interface image Transmission system and method based on FPGA

Technical field

The present invention relates to digital image processing techniques field, in particular to a kind of Gige Vision interface based on FPGA Image delivering system and method.

Background technique

With the continuous development of computer network communication and multimedia technology, the progress of image processing techniques and mature, In the fields such as medical treatment, living things feature recognition, machine vision, military affairs, remote sensing monitoring, the application of image processing system is more and more wider It is general, regardless of the data transmission research in image processing system is always one of the key point of research in which field.Comparison Traditional transmission technology is played, such as 100 m ethernet technology, RS232 interface are intended to transmit the interface of simple information, existing height Quick access vocal imitation skill is as USB interface, Camera Link interface, IEEE 1394, GigE gigabit ethernet interface etc. can be provided Bandwidth is bigger, and big data demand needed for being more able to satisfy high Qinghua and big data.Compared to other interfaces, gigabit Ethernet is connect Mouth have on image transmitting with roomy, long transmission distance, can seamless upgrade to ten thousand mbit ethernets advantage.And FPGA is powerful The inborn characteristics such as parallel data processing capacity, online programmable and dynamical system reconstruct static programmable pass it in image Defeated field has a wide range of applications.

Summary of the invention

The shortcomings that it is a primary object of the present invention to overcome the prior art and deficiency, provide a kind of Gige based on FPGA Vision interface image Transmission system can in conjunction with gigabit Ethernet and FPGA, and using Gige Vision as transport protocol It is effectively improved traditional embedded image at present and transmits the problem that existing hardware cost is high, transmission range is shorter, operation power consumption is big.

Another object of the present invention is to provide a kind of Gige Vision interface image transmission method based on FPGA.

The purpose of the present invention is realized by the following technical solution:

A kind of Gige Vision interface image Transmission system based on FPGA, comprising: imaging sensor, host computer, local Gigabit Ethernet network, the built-in image collection equipment based on Gige interface, wherein the embedded image based on Gige interface is adopted Integrate equipment as the core equipment of system, including fpga chip, PHY chip；Wherein fpga chip signal input part and image sensing The connection of device output signal end；Fpga chip mutually connects with signal with PHY chip；PHY chip is connected with host computer；

Fpga chip includes: image capture module (1), picture format processing module (2), GVCP control module (3), ether FidonetFido stack module (4) and ethernet control module (5)；

The course of work of system includes:

1) camera, built-in image collection equipment and host computer are connected in the same local area network, and system electrification is initial Change, host computer reads equipment state, configuration device parameter, issues discovery instruction and open command, system starts automatically；

2) camera obtains image data, is transmitted to built-in image collection equipment, is correspondingly embedded in formula image capture device According to data packet is obtained, encapsulated by parsing and pre-processing laggard row format, after the completion of host computer and the Signalling exchange of equipment, Data and parameter are uploaded to host computer；

3) camera image and image parameter selected by host computer real-time display.

Preferably, built-in image collection equipment is connected by image capture module (1) with imaging sensor, and responsible pair Cmos image sensor carries out device configuration and image data acquiring；

Picture format processing module (2), pre-processes imaging sensor acquired image, realizes that function includes pair Input image data carries out cutting packet, format encapsulation, it is made to meet the transmission standard of GVSP Apple talk Data Stream Protocol Apple Ta；

GVCP control module (3), the GVCP control protocol for being responsible for sending with host computer interact；

Ethernet protocol stack module (4) is responsible for the data sended over to up-stream module and carries out ethernet format encapsulation, makes It obtains it and meets gigabit Ethernet transformat requirement, which has ARP, ICMP agreement automatic answer function, can parse The ARP request datagram that position machine is sent, and send corresponding ARP, ICMP reply data packet automatically and carry out response, and by input Host computer MAC Address and IP address are cached into static cache list block；

Ethernet control module (5) realizes control and signal interaction to PHY chip, including lead code and cyclic redundancy check Addition so that data meet physical layer transmission requirement.

Specifically, image capture module (1) include camera parameter list module (1.1), camera configuration module (1.2), Utilizing camera interface module (1.3), image capture interface module (1.4)；

Picture format processing module (2) is single module；

GVCP control module (3) includes equipment discovery configuration module (3.1), device register module for reading and writing (3.2), equipment Memory read-write module (3.3), GVCP message convergence module (3.4)；

Ethernet protocol stack module (4) includes that ARP_IP summarizes parsing module (4.1), ARP parsing module (4.2), ARP hair Send module (4.3), static list cache module (4.4), IP parsing module (4.5), ICMP parsing module (4.6), UDP parsing mould Block (4.7), ICMP sending module (4.8), message convergence module (4.9), UDP sending module (4.10), UDP cut packet module (4.11)；

Ethernet control module (5) includes MAC control module (5.1), MAC interface module (5.2), MAC configuration module (5.3), PLL module (5.4).

Preferably, host computer includes to read XML file, parsing to the real-time processing under built-in image collection equipment XML file, discovering device generate configuration interface, Signalling exchange, image buffer storage and display.

A kind of Gige Vision interface image transmission method based on FPGA, comprising the following steps:

A) camera, built-in image collection equipment and host computer are connected in the same local area network, and system electrification is initial Change；

B) host computer sends signaling message GVCP, carries out information exchange by gigabit ethernet interface and FPGA, negotiates simultaneously Configure the universal guiding register and user register in equipment；

C) after host computer completes basic equipment read-write register operation, equipment XML is read by signaling message form and is retouched State file；

D) upper computer software automatically parses XML file, carries out if successfully resolved in next step, otherwise software reports an error and returns To step c)；

E) host computer generates configuration interface and transmission channel；

F) vision facilities acquisition is enabled according to the customized register of user, opens Image Acquisition operation；

G) format encapsulation is carried out to the image of acquisition to transmit with Ethernet；

H) it shuts down and completes to operate.

Preferably, host computer and the signaling message stream interaction flow of built-in image collection equipment include:

The reception of signaling message: host computer PC sends signaling message, is connected through cable with PHY chip；Gigabit Ethernet GVCP signaling message is transmitted to ethernet control module (5) by PHY chip, and ethernet control module removes lead code to message, And after carrying out CRC check, it is transferred to ethernet protocol stack module (4)；In ethernet protocol stack module, data are first transmitted to The total parsing module of ARP_IP (4.1) carries out MAC Address verification to the data of input, after removing MAC header format, according in data IP type section, GVCP signaling message is sent to IP traffic, IP parsing module (4.5) are reached；IP parsing module (4.5) meeting pair The data flow of input carries out IP Address Velocity and stem error detection code check, and IP address information progress is extracted from data segment It caches, after the IP stem for removing signaling message, according to data stream type, signaling message data is transmitted to UDP parsing module (4.7) it is parsed；UDP parsing module can carry out verification and calculation processing to the data of input, filter out the report of checksum error Text, and remove and remaining data is sent to GVCP control module (3) behind the head UDP；GVCP control module signaling report based on the received Text is read out, verifies, protocol processes operate, and generates built-in command according to signaling message and operate equipment；

The transmission of signaling message: GVCP control module sends response message after receiving signaling message and being disposed Reply host computer.GVCP first generates corresponding response message according to different signaling types, and response message first passes through GVCP message Convergence module (3.4) is scheduled, and is sent to UDP later and is cut packet module (4.11), decides whether to need depending on sending message length demand Cut packet and cutting length.

Specifically, data are sent to UDP sending module (4.10) after cutting packet module, MAC header is carried out to the data of input Encapsulation, IP encapsulation and according to data portion and header format part calculate UDP verification and after, carry out the encapsulation of the head UDP, Partial data is sent to message convergence module (4.9) later and carries out FIFO caching；Ethernet control module (5) can converge according to message The sky of storing data FIFO expires state and is read out data in poly- module, will reply after message adds upper lead code and CRC check, PC host computer is sent to eventually by network twisted-pair cable to interact.

Specifically, it is as follows to cut packet modular structure: data input pin need to input information include data portion, data end to end Indication signal sop and eop, data valid signal vld and the purpose IP address for needing to be sent to, purpose physical address, destination Mouth, source port；Wherein port information is sent to corresponding fifo module caching with address information respectively；And data portion, it is slow in FIFO Two counter cnt_1472 are added before depositing, counter cnt_18, FIFO output end is also all double counters logic, be cnt_1 with cnt_2；Cnt_1472 just calculates input data when there is data input, and adding a condition is din_vld signal, and cnt_ 18 be only more than that 1454 bytes just start counting at the end of i.e. cnt_1472 is counted, and grow counting in input data length In degree deposit information FIFO；And in FIFO output end, cnt_2 is responsible for counting stage number, if data length is too long, a point both ends are passed Defeated, cnt_1 is responsible for counting actual output word joint number.

Preferably, after host computer and built-in image collection equipment complete the interaction of signaling message, host computer can be automatic It sends and opens acquisition image command unlatching Image Acquisition, wherein the transmission flow of image data stream GVSP are as follows: image capture module (1) image data is acquired according to imaging sensor Image Acquisition timing requirements, and is transmitted to picture format processing module (2)；Figure As data are after picture format processing module cut packet and encapsulation, it is sent to the message convergence module of ethernet protocol stack module (4.9) it dispatches and transmits for ethernet control module；After adding lead code, CRC check in ethernet control module, pass through PHY chip is sent to host computer imaging.

Specifically, the form that picture format processing module is packaged into MAC+IP+UDP+GVSP+ data to input data carries out It sends.

Specifically, picture format processing module also needs the size according to acquisition image, adjustment length input is to a frame figure It is sent as data cut wrapping, length set by SCPS register when length length is host computer Signalling exchange.

Compared with the prior art, the invention has the following advantages and beneficial effects:

(1) the present invention is based on fpga chips, and by (including in fpga chip interior design each section logic module Image capture module, picture format processing module, GVCP control module, ethernet protocol stack module, ethernet control module five A big module, each module are divided into multiple little modules composition again) logic module structure and data flow that realize Image Acquisition, by On the one hand this effectively reduces hardware cost, reduces operation power consumption, reduces volume, on the other hand increase effectively at data Reason amount improves data-handling efficiency, improves Energy Efficiency Ratio.It the composite can be widely applied to the industry spot based on machine vision Monitoring.

(2) present invention includes to support ICMP, ARP, UDP, association IP agreement parsing and sent in the upper inside of scheme realization View stack and protocol stack itself have high-performance and cut packet module, to compared with same type protocol stack, can improve gigabit Ethernet bandwidth benefit It is user-friendly with rate and the encapsulation of protocol stack.

Detailed description of the invention

Fig. 1 is embodiment overall operation flow chart.

Fig. 2 is embodiment Signalling exchange flow chart.

Fig. 3 is that UDP cuts packet function structure chart.

Fig. 4 is picture format processing module structure chart.

Fig. 5 is picture format process module state transition diagram.

Fig. 6 is the system module block diagram of embodiment.

Specific embodiment

Present invention will now be described in further detail with reference to the embodiments and the accompanying drawings, but embodiments of the present invention are unlimited In this.

Embodiment 1

It is in order to improve the disadvantages of logical resource consumption present in traditional Gige IP kernel is big, hardware cost is higher, originally Invention simplifies agreement according to Gige Vision protocol contents and the requirement of Ethernet transformat to design and support control Message protocol (Internet Control Message Protocol, ICMP) processed, address resolution protocol (Address Resolution Protocol, ARP), User Datagram Protocol (User Datagram Protocol, UDP), gigabit ether Net visual spatial attention agreement (GigE Vision Control Protocol, GVCP), gigabit Ethernet vision data stream protocol The IP kernel of (GigE Vision Stream Protocol, GVSP) package and parsing, and utilize the parallel processing of FPGA, root Image data is transferred to host computer real-time display according to Gige Vision protocol requirement.

A kind of Gige Vision interface image Transmission system based on FPGA, including cmos image sensor, PC are upper Machine, local gigabit Ethernet network, the built-in image collection equipment based on Gige interface, wherein based on the embedded of Gige interface Image capture device is the core equipment of system, including fpga chip, PHY chip, RJ45 interface.The wherein FPGA signal Input terminal is connect with cmos image sensor output signal end；The FPGA mutually connects with signal with PHY chip；Described PHY chip and the RJ45 interface interconnect, and RJ45 interface is connected by cable with PC host computer.Inside fpga chip Design each section logic module, comprising: image capture module (1), picture format processing module (2), GVCP control module (3), Ethernet protocol stack module (4) and ethernet control module (5), the part are realized using hardware description language Verilog, full Sufficient Gige Vision transport protocol and the requirement of Ethernet transmission format protocol, it then follows gmii interface specification.

Wherein:

S1, image capture module (1) include camera parameter list module (1.1), camera configuration module (1.2), take the photograph As head interface module (1.3), image capture interface module (1.4)；

S2, picture format processing module (2) are single module；

S3, GVCP control module (3) include equipment discovery configuration module (3.1), device register module for reading and writing (3.2), device memory module for reading and writing (3.3), GVCP message convergence module (3.4)；

S4, ethernet protocol stack module (4) include ARP_IP summarize parsing module (4.1), ARP parsing module (4.2), ARP sending module (4.3), static list cache module (4.4), IP parsing module (4.5), ICMP parsing module (4.6), UDP Parsing module (4.7), ICMP sending module (4.8), message convergence module (4.9), UDP sending module (4.10), UDP Qie Baomo Block (4.11)；

S5, ethernet control module (5) include MAC control module (5.1), MAC interface module (5.2), MAC configuration module (5.3), PLL module (5.4).

Embedded acquisition equipment is connected by image capture module (1) with imaging sensor, is responsible for sensing cmos image Device carries out device configuration and image data acquiring.

Picture format processing module (2) is responsible for pre-processing imaging sensor acquired image, in logic module Realize have the function of to carry out cutting packet, format encapsulation etc. to input image data, it is made to meet GVSP number in realization using single module According to the transmission standard of stream protocol.

GVCP control module (3), the module are divided in logical construction division in order to which three sub-modules are realized, include to set Standby discovery module, device register module for reading and writing, device memory module for reading and writing, the control module are responsible for and host computer transmission GVCP control protocol interacts.

Ethernet protocol stack module (4) is divided in order to which multiple modules are realized in logical construction, is mainly responsible for upper The data that trip module sends over carry out ethernet format encapsulation, so that it meets gigabit Ethernet transformat requirement, the mould Block has ARP, ICMP agreement automatic answer function, can parse the ARP request datagram of host computer transmission, and sends phase automatically ARP, ICMP reply data packet answered carry out response, and the host computer MAC Address and IP address of input are cached to static cache In list block.

Ethernet control module (5) divides in order to which four modules are realized in logical construction, includes to PHY core The control and signal interaction of piece, lead code and the addition of cyclic redundancy check etc., so that data meet physical layer transmission requirement.

Real-time processing of the computer as host computer to embedded acquisition equipment slave computer, includes to read XML file, solution It analyses XML file, discovering device, generate configuration interface, Signalling exchange, image buffer storage and display.The course of work of system are as follows:

1) camera, built-in image collection equipment and computer are connected in the same local area network, and system electrification is initial Change, host computer reads equipment state, configuration device parameter, issues discovery instruction and open command, system starts automatically；

FPGA in built-in image collection equipment selects the CYCLONE IV serial model No. of Altera to be EP4CE15F17C8。

Ethernet PHY in built-in image collection equipment selects the RTL8211EG of Realtek company.

Host computer shows that software is the Halcon of MVtec company in embedded imaging system.

Embodiment 2

Referring to Fig.1, a kind of Gige Vision interface image transmission realizing method based on FPGA, overall operation process are as follows:

A) camera, built-in image collection equipment and computer are connected in the same local area network, and system electrification is initial Change；

E) host computer generates configuration interface and transmission channel；

H) it shuts down and completes to operate.

With reference to Fig. 2, the signaling message stream interaction flow of host computer and built-in image collection equipment:

The reception of signaling message: host computer PC sends signaling message, is connected through cable with PHY chip；Gigabit Ethernet GVCP signaling message is transmitted to ethernet control module (5) by PHY chip, and ethernet control module removes lead code to message, And after carrying out CRC check, it is transferred to ethernet protocol stack module (4)；In ethernet protocol stack module, data are first transmitted to The total parsing module of ARP_IP (4.1) carries out MAC Address verification to the data of input, after removing MAC header format, according in data IP type section, GVCP signaling message is sent to IP traffic, IP parsing module (4.5) are reached；IP parsing module (4.5) meeting pair The data flow of input carries out IP Address Velocity and stem error detection code check, and IP address information progress is extracted from data segment It caches, after the IP stem for removing signaling message, according to data stream type, signaling message data is transmitted to UDP parsing module (4.7) it is parsed；UDP parsing module can carry out verification and calculation processing to the data of input, filter out the report of checksum error Text, and remove and remaining data is sent to GVCP control module (3) behind the head UDP；GVCP control module signaling report based on the received Text is read out, verifies, protocol processes operate, and generates built-in command according to signaling message and operate equipment.

UDP message cuts packet function structure chart with reference to Fig. 3, and packet module is different from traditional cutting, which can It reduces and there is the case where a large amount of short Bao Erxu zero paddings in gigabit Ethernet network, to improve network bandwidth utilization factor.The module knot Structure is as follows: data input pin is respectively necessary for the sop of indication signal end to end and eop, data valid signal of input data part, data The information such as purpose IP address, purpose physical address, destination port, the source port that vld and needs are sent to.Wherein port information It is sent to corresponding fifo module caching respectively with address information；And data portion, in order to reduce, incoming message is too small and needs to mend 0 Two counter cnt_1472 are added before FIFO is cached in situation, counter cnt_18, FIFO output end is also all that double counters are patrolled Volume, it is cnt_1 and cnt_2；Cnt_1472 just calculates input data when there is data input, and adding a condition is din_ Vld signal, and cnt_18 is only more than 1454 bytes in input data length, i.e. at the end of cnt_1472 is counted, just starts It counts, and in counting step deposit information FIFO.And in FIFO output end, cnt_2 is responsible for counting stage number, if data length Too long, then a point both ends are transmitted, and cnt_1 is responsible for counting actual output word joint number.

Data are sent to UDP sending module (4.10) after cutting packet module, carry out MAC header encapsulation, IP to the data of input Encapsulate and according to data portion and header format part calculate UDP verification and after, carry out the encapsulation of the head UDP, later will be complete Entire data is sent to convergence module (4.9) and carries out FIFO caching；Ethernet control module (5) can be according to storing data in convergence module The sky of FIFO expires state and is read out data, after replying the upper lead code of message addition and CRC check, eventually by network multiple twin Line is sent to PC host computer and interacts.

The PHY management interface signal of the ethernet control module is MDC and MDIO signal.

The GMII interactive signal of the ethernet control module is 125M work clock.

After host computer and built-in image collection equipment complete the interaction of signaling message, PC upper computer software can be sent out automatically Unlatching acquisition image command is sent to open Image Acquisition, wherein the transmission flow of image data stream GVSP are as follows: image capture module (1) Image data is acquired according to imaging sensor Image Acquisition timing requirements, and is transmitted to picture format processing module (2).

The structure chart of picture format processing module refers to Fig. 4.MAC+IP+UDP+GVSP+ data are packaged into input data Form sent, wherein UDP encapsulate when verified and calculated, and GVSP encapsulate using Image format, shape State convert reference Fig. 5.

Picture format processing module also need according to acquisition image size, adjustment length input to a frame image data into Row is cut packet and is sent, and SCPS (Stream Channel Packet Size) is deposited when length length is host computer Signalling exchange Length set by device.

Image data is sent to the report of ethernet protocol stack module after picture format processing module carries out cutting packet and encapsulation Literary convergence module (4.9) is dispatched and is transmitted for ethernet control module；Lead code, the school CRC are added in ethernet control module After testing, host computer imaging is sent to by PHY chip and RJ45.

After host computer receives Ethernet transmission data, Halcon software can carry out imaging to the data of acquisition and show.

The above embodiment is a preferred embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment Limitation, other any changes, modifications, substitutions, combinations, simplifications made without departing from the spirit and principles of the present invention, It should be equivalent substitute mode, be included within the scope of the present invention.

Claims

1. a Gige Vision interface image transmission system based on FPGA, is characterized in that, comprises: image sensor, host computer, local Gigabit Ethernet, embedded image acquisition equipment based on Gige interface, wherein based on the embedded image acquisition device of Gige interface The image acquisition device is the core device of the system, including the FPGA chip and the PHY chip; the signal input terminal of the FPGA chip is connected to the output signal terminal of the image sensor; the FPGA chip and the PHY chip are connected to each other; the PHY chip is connected to the host computer;

The FPGA chip includes: an image acquisition module (1), an image format processing module (2), a GVCP control module (3), an Ethernet protocol stack module (4) and an Ethernet control module (5);

The working process of the system includes:

1) The camera, embedded image acquisition device and host computer are connected to the same local area network, the system is powered on and initialized, the host computer reads the device status, configures device parameters, automatically sends out discovery commands and start commands, and the system starts to work;

2) The camera acquires image data and transmits it to the embedded image acquisition device. The corresponding embedded image acquisition device performs format encapsulation after parsing and preprocessing according to the acquired data packet. After the signaling interaction between the host computer and the device is completed, the data and parameters are uploaded to the host computer;

3) The upper computer displays the selected camera image and image parameters in real time.

2. the Gige Vision interface image transmission system based on FPGA according to claim 1, is characterized in that, image acquisition module (1), is connected with embedded image acquisition device and image sensor, is responsible for carrying out device configuration to CMOS image sensor and image data collection;

The image format processing module (2) preprocesses the image collected by the image sensor, and its realization functions include packet cutting and format encapsulation of the input image data, so that it meets the transmission standard of the GVSP data stream protocol;

The GVCP control module (3) is responsible for interacting with the GVCP control protocol sent by the host computer;

The Ethernet protocol stack module (4) is responsible for encapsulating the data sent by the upstream module in Ethernet format so that it meets the transmission format requirements of Gigabit Ethernet. This module has the automatic response function of ARP and ICMP protocols, and can analyze ARP request datagrams, and automatically send corresponding ARP, ICMP response packets to respond, and cache the input host computer MAC address and IP address to the static cache list module;

The Ethernet control module (5) realizes the control and signal interaction of the PHY chip, including the addition of preamble and CRC check code, so that the data meets the requirements of physical layer transmission.

3. the Gige Vision interface image transmission system based on FPGA according to claim 2, is characterized in that, image acquisition module (1) comprises camera parameter table module (1.1), camera configuration module (1.2), camera interface module (1.3 ), image acquisition interface module (1.4);

The image format processing module (2) is a single module;

The GVCP control module (3) includes a device discovery configuration module (3.1), a device register read-write module (3.2), a device memory read-write module (3.3), and a GVCP message aggregation module (3.4);

Ethernet protocol stack module (4) comprises ARP_IP summary analysis module (4.1), ARP analysis module (4.2), ARP transmission module (4.3), static list cache module (4.4), IP analysis module (4.5), ICMP analysis module ( 4.6), UDP parsing module (4.7), ICMP sending module (4.8), message aggregation module (4.9), UDP sending module (4.10), UDP packet cutting module (4.11);

The Ethernet control module (5) includes a MAC control module (5.1), a MAC interface module (5.2), a MAC configuration module (5.3), and a PLL module (5.4).

4. the FPGA-based Gige Vision interface image transmission system according to claim 1, is characterized in that, the real-time processing of host computer under embedded image acquisition equipment includes reading XML file, parsing XML file, discovery equipment, Generate configuration interface, signaling interaction, image cache and display.

5. a Gige Vision interface image transmission method based on system described in claim 3, is characterized in that, comprises the following steps:

a) The camera, embedded image acquisition device and host computer are connected to the same local area network, and the system is powered on and initialized;

b) The upper computer sends the signaling message GVCP, and performs information interaction with the FPGA through the Gigabit Ethernet interface, and negotiates and configures the general boot register and user register in the device;

c) After the upper computer completes the basic device read and write register operations, it reads the device XML description file in the form of a signaling message;

d) The host computer software automatically parses the XML file, if the parsing is successful, proceed to the next step, otherwise the software reports an error and returns to step c);

e) The upper computer generates configuration interfaces and transmission channels;

f) enable image acquisition according to the user-defined register, and start the image acquisition operation;

g) Carry out format encapsulation and Ethernet transmission to the collected images;

h) Shut down and complete the operation.

6. the Gige Vision interface image transmission method according to claim 5, is characterized in that, the signaling message flow interaction process of upper computer and embedded image acquisition equipment comprises:

Reception of signaling messages: the upper computer PC sends signaling messages, and is connected to the PHY chip via a network cable; the Gigabit Ethernet PHY chip transmits the GVCP signaling messages to the Ethernet control module (5), and the Ethernet control module Message is removed preamble, and after carrying out CRC check, transmit to Ethernet protocol stack module (4); In Ethernet protocol stack module, data is first transmitted to ARP_IP total analysis module (4.1), the data of input is carried out MAC address verification, after removing the MAC header format, according to the IP type segment in the data, the GVCP signaling message is sent to the IP data flow, and passed to the IP analysis module (4.5); the IP analysis module (4.5) will input the The data stream performs IP address verification and header error detection code verification, extracts the IP address information from the data segment for caching, removes the IP header of the signaling message, and transmits the signaling message data according to the data stream type To UDP parsing module (4.7) to analyze; UDP parsing module will carry out checksum calculation processing to the data of input, filter out the message of checksum error, and send remaining data to GVCP control module ( 3); the GVCP control module reads, checks, and performs protocol processing operations according to the received signaling message, and generates internal instructions to operate the device according to the signaling message;

Sending of signaling message: After receiving and processing the signaling message, the GVCP control module sends a response message to reply to the host computer; first, GVCP generates corresponding response messages according to different signaling types, and the response message first passes through GVCP The message aggregation module (3.4) performs scheduling, and then sends it to the UDP packet cutting module (4.11), and determines whether to cut the packet and the length of the packet depending on the length of the sent message.

7. the Gige Vision interface image transmission method according to claim 6, is characterized in that, data is sent to UDP transmission module (4.10) after the packet cutting module, carries out MAC header encapsulation, IP encapsulation to the data of input, and according to data After the UDP checksum is calculated by the part and the header format part, the UDP header is encapsulated, and then the complete data is sent to the message aggregation module (4.9) for FIFO buffering; the Ethernet control module (5) will according to the message aggregation module Read the data in the empty and full state of the data FIFO stored in the middle, add the preamble and CRC to the reply message, and finally send it to the PC host computer through the network twisted pair for interaction.

8. The Gige Vision interface image transmission method according to claim 7, characterized in that the structure of the packet cutting module is as follows: the data input terminal needs to input information including the data part, the head and tail indication signals sop and eop of the data, and the valid data signal vld , and the destination IP address, destination physical address, destination port, and source port that need to be sent; the port information and address information are respectively sent to the corresponding FIFO module cache; and the data part, add two counters cnt_1472 and counter cnt_18 before the FIFO cache, The FIFO output is also double-counter logic, which is cnt_1 and cnt_2; cnt_1472 calculates the input data when there is data input, and the plus condition is the din_vld signal, while cnt_18 is only when the input data length exceeds 1454 bytes, that is, cnt_1472 When the counting ends, the counting starts, and the counting length is stored in the information FIFO; at the output end of the FIFO, cnt_2 is responsible for counting the number of stages, if the data length is too long, it is transmitted at both ends, and cnt_1 is responsible for counting the actual output bytes number.

9. the Gige Vision interface image transmission method according to claim 5, is characterized in that, after upper computer and embedded image acquisition equipment complete the interaction of signaling message, upper computer automatically sends and starts the acquisition image command and starts image acquisition, The sending process of the image data stream GVSP is as follows: the image acquisition module (1) collects image data according to the image sensor image acquisition timing requirements, and transmits it to the image format processing module (2); the image data is cut and packaged by the image format processing module After that, it is sent to the message aggregation module (4.9) of the Ethernet protocol stack module for scheduling and transmission of the Ethernet control module; after adding the preamble and CRC check in the Ethernet control module, it is sent to the host computer for imaging through the PHY chip .

10. The Gige Vision interface image transmission method according to claim 5, wherein the image format processing module sends the input data in the form of MAC+IP+UDP+GVSP+data; the image format processing module also needs to collect The size of the image, adjust the length input to cut and send a frame of image data, and its length is the length set by the SCPS register when the host computer interacts with signaling.