CN109039046B

CN109039046B - Buffer circuit of modular multilevel converter half-full-bridge submodule

Info

Publication number: CN109039046B
Application number: CN201810806248.5A
Authority: CN
Inventors: 林磊; 徐晨; 胡凯; 周雪妮
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2018-07-20
Filing date: 2018-07-20
Publication date: 2020-02-14
Anticipated expiration: 2038-07-20
Also published as: CN109039046A

Abstract

The invention discloses a buffer circuit of a half-full-bridge submodule of a modular multilevel converter, wherein the half-full-bridge submodule comprises a left half-bridge module, a right half-bridge module and a connecting circuit; still contain three groups RCD buffer circuit, every group RCD buffer circuit includes: a resistor and a diode are connected in parallel and then are connected in series with a capacitor, and the cathode of the diode is connected with the anode of the capacitor. The invention provides a buffer structure of 3 groups of RCD buffer circuits, wherein the IGBT turn-off voltage peak of a left half-bridge module is restrained by the first group of RCD buffer circuits, the IGBT turn-off voltage peak of a right half-bridge module is restrained by the second group of RCD buffer circuits, and the IGBT turn-off voltage peak of a connecting circuit is restrained by the third group of RCD buffer circuits, so that the buffer circuit of a half-full-bridge sub-module is simplified, and the IGBT turn-off voltage can be restrained well while the cost of the buffer circuit is lowered; the invention provides the parameter design of the RCD buffer circuit, which can reduce the system cost and ensure that the turn-off overvoltage of the IGBT does not overshoot.

Description

Buffer circuit of modular multilevel converter half-full-bridge submodule

Technical Field

The invention belongs to the field of IGBT buffer circuit research, and particularly relates to a buffer circuit of a half-full-bridge submodule of a modular multilevel converter.

Background

Modular Multilevel Converters (MMC) have the advantages of easy packaging and expansion of Modular structures, small stress of switching devices, low output voltage harmonic waves and the like, and have been applied to practical engineering, such as the Transbay engineering in the united states and the flexible direct-current transmission engineering at five ends in the navigations and mountains in china.

According to different sub-module topological structures, the modular multilevel converter is generally divided into a half-bridge type, a full-bridge type and a clamping double type. The Semi-Full Bridge Sub-module (SFB-SM) is a clamping dual-type Sub-module, which is composed of 7 IGBT anti-parallel diodes and has four levels of +2Uc, + Uc, 0 and-Uc output capability. The SFB-SM reduces the number of power electronics compared to a full bridge sub-module that can actively block dc fault currents. Meanwhile, the two capacitors of the SFB-SM are charged and discharged simultaneously, so that the voltages of the two capacitors are always balanced.

Due to the existence of parasitic inductance of the main circuit, a large turn-off voltage peak is generated in the turn-off process of a Silicon insulated gate Bipolar Transistor (Si IGBT), the IGBT is damaged by the excessively high turn-off voltage peak, and meanwhile, the IGBT may be turned on by mistake, so that a buffer circuit needs to be arranged in an actual application circuit of the IGBT to suppress the turn-off voltage peak. At present, the design method of the buffer circuit of the half-bridge sub-module mainly includes:

1) a group of Resistance Capacitance Diode (RCD) buffer circuits are connected in parallel beside each switching device. As shown in fig. 1(a), the voltage at both ends rises during the turn-off process of the IGBT, so that the diode leads to the capacitor for charging, thereby suppressing the turn-off voltage spike of the IGBT and reducing the turn-off loss of the IGBT. The method is simple and reliable in design, but a large number of RCD buffer circuits are used, so that the buffer circuit is complex in structure.

2) And a group of RCD buffer circuits are connected in parallel at two ends of the capacitor. As shown in fig. 1(b), since the two IGBT switching signals of the half-bridge sub-module are complementary, and one switching tube is turned off, the other switching tube is necessarily turned on, so that the buffer circuit of the half-bridge sub-module can be simplified.

In summary, since the half-full-bridge sub-module includes a large number of IGBTs, the conventional buffer circuit design method is complicated and the cost is high. Therefore, a simplified RCD buffer circuit of a half-full-bridge sub-module is needed.

Disclosure of Invention

Aiming at the defects of the prior art, the invention aims to solve the technical problems of complex design and high cost caused by the fact that a large number of IGBTs are needed in a half-full-bridge submodule in the prior art.

In order to achieve the purpose, the invention provides a buffer circuit of a half-full-bridge submodule of a modular multilevel converter, wherein the half-full-bridge submodule comprises a left half-bridge module, a right half-bridge module and a connecting circuit; wherein the left half-bridge module comprises: after the first switch tube T1 and the second switch tube T2 are connected in series, the first switch tube T1 and the second switch tube T2 are connected in parallel with the first capacitor C1 at a connection point P1 and a connection point N1; the right half-bridge module comprises: after the third switching tube T3 and the fourth switching tube T4 are connected in series, the third switching tube T3 and the fourth switching tube T4 are connected in parallel with the second capacitor C2 at a connection point P2 and a connection point N2; the connection circuit comprises a fifth switch tube T5, a sixth switch tube T6 and a seventh switch tube T7, the sixth switch tube T6 is bridged between a connection point P1 and a connection point P2 of the left and right half-bridge modules, the seventh switch tube T7 is bridged between a connection point N1 and a connection point N2 of the left and right half-bridge modules, the fifth switch tube T5 is connected between the sixth switch tube T6 and the seventh switch tube T7,

still contain three groups RCD buffer circuit, every group RCD buffer circuit includes: a resistor and a diode are connected in parallel and then connected in series with a capacitor, the cathode of the diode is connected with the anode of the capacitor, the anode of the diode is marked as a connection point A, and the cathode of the capacitor is marked as a connection point B;

the first group of RCD buffer circuit connection points A are connected with a half-full-bridge submodule connection point P1, and the connection point B is connected with a half-full-bridge submodule connection point N1;

the second group of RCD buffer circuit connection points A are connected with a half-full-bridge submodule connection point P2, and the connection point B is connected with a half-full-bridge submodule connection point N2;

the third set of RCD snubber circuit connection points a is connected to half-full-bridge submodule connection point P1 and connection point B is connected to half-full-bridge submodule connection point N2.

Specifically, each switching tube in T1-T7 is composed of 1 IGBT in anti-parallel connection with 1 diode.

Specifically, the specific connection mode of the half-full-bridge submodule is as follows:

the emitter of the first switch tube T1 is connected with the collector of the second switch tube T2; the collector of the first switch tube T1, the emitter of the sixth switch tube T6 and the anode of the first capacitor C1 are connected; the emitter of the second switch tube T2, the emitter of the fifth switch tube T5, the collector of the seventh switch tube T7 and the cathode of the first capacitor C1 are connected; the collector of the fifth switching tube T5, the collector of the sixth switching tube T6, the collector of the third switching tube T3 and the anode of the second capacitor C2 are connected; the emitter of the seventh switch tube T7, the emitter of the fourth switch tube T4 and the cathode of the second capacitor C2 are connected; the emitter of the third switching tube T3 is connected to the collector of the fourth switching tube T4.

Specifically, the left half-bridge module further comprises an eighth switch M1 connected in series with the first capacitor C1 at a connection point P1 and a connection point N1; the right half-bridge module further comprises a ninth switch tube M2 connected in series with the first capacitor C2 at the connection point P2 and the connection point N2.

the emitter of the first switch tube T1 is connected with the collector of the second switch tube T2; the collector of the first switch tube T1, the emitter of the sixth switch tube T6 and the source of the eighth switch tube M1 are connected; the drain electrode of the eighth switching tube M1 is connected with the anode of the first capacitor C1; the emitter of the second switch tube T2, the emitter of the fifth switch tube T5, the collector of the seventh switch tube T7 and the cathode of the first capacitor C1 are connected; the collector electrode of the fifth switching tube T5, the collector electrode of the sixth switching tube T6, the collector electrode of the third switching tube T3 and the source electrode of the ninth switching tube M2 are connected; the drain of the ninth switching tube M2 is connected with the anode of the second capacitor C2; the emitter of the seventh switch tube T7, the emitter of the fourth switch tube T4 and the cathode of the second capacitor C2 are connected; the emitter of the third switching tube T3 is connected to the collector of the fourth switching tube T4.

Specifically, each of the switching tubes M1 to M2 is composed of 1 SiC MOSFET connected in anti-parallel with 1 diode.

Specifically, the calculation formula of the capacitor C in the RCD buffer circuit is:

wherein, I_pIs the peak value of IGBT collector current, U_CBuffering the RCDRated operating voltage, t, of a capacitor in a circuit_fThe voltage rise time of two ends of a capacitor in the RCD buffer circuit is obtained;

the calculation formula of the resistor R in the RCD buffer circuit is as follows:

3RC=t_on(min)(2)

wherein ton (min) is the minimum IGBT conducting time, and C is the capacitance in the RCD buffer circuit;

and the minimum withstand voltage value of the diode in the RCD buffer circuit is selected from the rated voltage value of the IGBT.

Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

(1) compared with the prior art, the buffer structure of the 3 groups of RCD buffer circuits is provided, the IGBT turn-off voltage peak of the left half-bridge module is restrained through the first group of RCD buffer circuits, the IGBT turn-off voltage peak of the right half-bridge module is restrained through the second group of RCD buffer circuits, the IGBT turn-off voltage peak of the connecting circuit is restrained through the third group of RCD buffer circuits, the buffer circuit of the half-full-bridge sub-module is simplified, and the IGBT turn-off voltage can be restrained well while the cost of the buffer circuit is lowered.

(2) Compared with the prior art, the invention provides the parameter design of the RCD buffer circuit, the capacitor is designed according to the energy consumed by the discharge resistor, the charge on the capacitor C is released to the design resistor with the charge of less than 5%, the minimum withstand voltage value of the diode is selected as the rated voltage value of the IGBT in the main loop to design the diode, the proper RCD parameter can reduce the system cost, and the IGBT turn-off overvoltage is ensured not to overshoot.

Drawings

Fig. 1(a) is a schematic diagram of a buffer circuit 1 of a half-bridge submodule in the prior art;

fig. 1(b) is a schematic diagram of a buffer circuit 2 of a half-bridge submodule in the prior art.

Fig. 2 is a schematic diagram of a modular multilevel converter MMC topology structure according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a half-full-bridge sub-module topology according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a half-full-bridge sub-module buffer circuit topology according to an embodiment of the present invention.

FIG. 5 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd + U_CA simulation result diagram with the current direction as positive;

FIG. 6 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd + U_CA simulation result graph when the current direction is negative;

FIG. 7 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of + U_CAnd 0, a simulation result graph with the current direction as positive;

FIG. 8 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of + U_CAnd 0, a simulation result graph when the current direction is negative;

FIG. 9 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd 0, a simulation result graph with the current direction as positive;

FIG. 10 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd 0, a simulation result graph when the current direction is negative;

FIG. 11 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of-U_CAnd 0, a simulation result graph with the current direction as positive;

FIG. 12 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of-U_CAnd 0, a simulation result graph when the current direction is negative;

in fig. 5-12, (a) is an output voltage waveform; (b) is an output current waveform; (c) the voltage waveform at two ends of a switch tube which does not comprise a buffer circuit; (d) the voltage waveform across the switch tube containing the buffer circuit.

Fig. 13 is a schematic diagram of a topology structure of a capacitor switch type half-full bridge sub-module buffer circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The invention describes a simplified buffer circuit design scheme by taking a modular multilevel converter MMC half full bridge submodule as an example. Fig. 2 is a schematic diagram of a modular multilevel converter MMC topology structure according to an embodiment of the present invention. As shown in fig. 2, the three-phase voltage converter comprises A, B, C three phases, each phase comprises an upper bridge arm and a lower bridge arm, and each bridge arm is formed by cascading N half full-bridge submodules in series with a bridge arm inductor.

Fig. 3 is a schematic diagram of a half-full-bridge sub-module topology according to an embodiment of the present invention. As shown in fig. 3, the half-full-bridge sub-module includes a left half-bridge module, a right half-bridge module and a connection circuit; wherein,

the left half-bridge module includes: the first switch tube T1 and the second switch tube T2 are connected in series and then are connected in parallel with the first capacitor C1; the right half-bridge module comprises: the third switching tube T3 and the fourth switching tube T4 are connected in series and then are connected in parallel with the second capacitor C2; the connecting circuit comprises a fifth switching tube T5, a sixth switching tube T6 and a seventh switching tube T7, the sixth switching tube T6 and the seventh switching tube T7 are respectively bridged between the left half-bridge module and the right half-bridge module, and the fifth switching tube T5 is connected between the sixth switching tube T6 and the seventh switching tube T7; each switch tube in T1-T7 is composed of 1 IGBT antiparallel 1 diode.

Fig. 4 is a schematic diagram of a half-full-bridge sub-module buffer circuit topology according to an embodiment of the present invention. As shown in fig. 4, in order to simplify the buffer circuit, the present invention employs a half-full-bridge sub-module and three sets of RCD buffer circuits.

The specific connection mode of the half-full-bridge submodule is as follows: the emitter of the first switch tube T1 is connected with the collector of the second switch tube T2, and the connection point is marked as a connection point P; the collector of the first switch tube T1, the emitter of the sixth switch tube T6 and the anode of the first capacitor C1 are connected, and the connection point is marked as a connection point P1; the emitter of the second switch tube T2, the emitter of the fifth switch tube T5, the collector of the seventh switch tube T7 and the negative electrode of the first capacitor C1 are connected, and the connection point is marked as a connection point N1; the collector of the fifth switching tube T5, the collector of the sixth switching tube T6, the collector of the third switching tube T3 and the anode of the second capacitor C2 are connected, and the connection point is marked as a connection point P2; the emitter of the seventh switch tube T7, the emitter of the fourth switch tube T4 and the cathode of the second capacitor C2 are connected, and the connection point is marked as a connection point N2; the emitter of the third switching tube T3 is connected to the collector of the fourth switching tube T4, and the connection point thereof is denoted as connection point N.

The RCD buffer circuit is composed of a resistor, a diode and a capacitor. The RCD buffer circuit is connected in a mode that a resistor is connected with a diode in parallel, and the cathode of the diode is connected with the anode of a capacitor. Preferably, the anode of the diode is marked as a connection point A, and the cathode of the capacitor is marked as a connection point B.

The working principle of the RCD buffer circuit is as follows: when the switch tube is turned off, the voltage at the two ends rises, so that the parallel diodes are conducted. The capacitor charging limits the voltage rising speed at two ends of the IGBT and reduces voltage spikes. Meanwhile, due to the fact that voltage spikes are reduced, overlapping of rising voltage and falling current is reduced, and therefore turn-off loss of the IGBT is reduced. Similarly, the IGBT is quickly switched on due to the discharge of the capacitor, the current rising rate is increased, the switching-on time is shortened, the overlapping of voltage and current is reduced, and the switching-on loss is reduced.

The specific connection mode of the three groups of RCD buffer circuits is as follows: the first group of RCD buffer circuit connection points A are connected with a half-full-bridge submodule connection point P1, and the connection point B is connected with a half-full-bridge submodule connection point N1; the second group of RCD buffer circuit connection points A are connected with a half-full-bridge submodule connection point P2, and the connection point B is connected with a half-full-bridge submodule connection point N2; the third set of RCD snubber circuit connection points a is connected to half-full-bridge submodule connection point P1 and connection point B is connected to half-full-bridge submodule connection point N2.

The working principle of the simplified buffer circuit is as follows: the IGBT turn-off voltage spike of the left half-bridge module is restrained through the first group of RCD buffer circuits, the IGBT turn-off voltage spike of the right half-bridge module is restrained through the second group of RCD buffer circuits, and the IGBT turn-off voltage spike of the connecting circuit is restrained through the third group of RCD buffer circuits.

The RCD buffer circuit parameter design steps are as follows:

1) design of capacitance parameters

Since the size of the capacitor is proportional to the energy consumed by the resistor, the effect of the buffer circuit is affected. Therefore, assuming that the current flowing through the capacitor is half of the peak current, there are:

in the formula I_pIs the peak collector current, U_CRated operating voltage for the capacitor, t_fThe rise time of the voltage across the capacitor.

The minimum voltage withstanding value of the absorption capacitor in the buffer circuit is the rated voltage value of the IGBT in the main circuit, and potential safety hazards are brought to the safety of the main circuit when the voltage withstanding value is too small. Meanwhile, the absorption capacitance of the buffer circuit needs to be selected as a non-inductive capacitance.

2) Resistance parameter design

The snubber circuit requires that the capacitor must fully discharge the charge before each IGBT turn off. Therefore, the resistor R must be selected to ensure that after the IGBT is turned on, the charge on the capacitor is released to less than 5% of the charged charge, i.e.:

3RC=t_on(min)(2)

in the formula, t_on(min)C is the capacitance size for the minimum on time.

3) Diode parameter design

The diode used by the buffer loop is selected from a fast recovery diode MUR860 with the rated voltage of 600V.

In this embodiment, the collector current peak value I_p12A, capacitance voltage rating U_C100V, the rise time t of the voltage across the capacitor_fThe voltage is 3 mus, 0.09 muF is calculated through the formula (1), the capacitance C is 0.1 muF, and the rated voltage of the actual capacitance device is twice of the rated working voltage of the capacitance, namely 200V. In this embodiment, the minimum on-time t_on(min)20 mus, 0.1 muF capacitance C, 66.7 omega resistance R calculated by formula (2), 60 omega resistance R.

The feasibility of the half-full-bridge submodule buffer circuit is verified through PSpice simulation software. The simulation parameters are shown in table 1. The simulation results are shown in fig. 5 to 12, with the current direction shown in fig. 4 being the positive direction.

TABLE 1

FIG. 5 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd + U_CAnd taking a simulation result chart with the current direction as positive, wherein the parasitic inductance on each line is taken to be 2 muH. Fig. 5(a) shows an output voltage waveform. As shown in fig. 5(a), within 0-50 μ s, the switching tubes T1, T4, T6 and T7 are turned on to output one-time rated operating voltage of 100V; within 50-53 mu s, the switch tube T5 is switched on, and the switch tubes T6 and T7 are switched off; within 53-100 mu s, the switching tubes T1, T4 and T5 are conducted, and double rated working voltage of 200V is output; within 100-103 mu s, the switching tubes T6 and T7 are switched on, and T5 is switched off; within 103-150 mu s, the switch tubes T1, T4, T6 and T7 are conducted to output one-time rated working voltage of 100V. Fig. 5(b) shows an output current waveform. The output current is greater than 0. Fig. 5(c) shows voltage waveforms across the switching tubes T5, T6, and T7 that do not include the snubber circuit, and fig. 5(d) shows voltage waveforms across the switching tubes T5, T6, and T7 that include the snubber circuit. The result shows that the T5 tube turn-off voltage spike is 141.3V when the buffer circuit is not included, the T5 tube turn-off voltage spike is 101.1V when the buffer circuit is included, and the turn-off voltage spike is well inhibited. The off-voltage spikes of the T6 and T7 tubes are not large in both cases.

FIG. 6 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd + U_CAnd (4) taking a simulation result chart when the current direction is negative, wherein the parasitic inductance on each line is taken to be 2 muH. Fig. 6(a) shows an output voltage waveform. As shown in fig. 6(a), the switching tube operation timing is the same as the current direction timing. Fig. 6(b) shows an output current waveform, and the output current is less than 0. Fig. 6(c) shows waveforms of voltages across the switching tubes T5, T6, and T7 without the snubber circuit. Fig. 6(d) shows voltage waveforms across the switching tubes T5, T6, and T7 including the snubber circuit. The results show that no buffering is involvedThe off-state voltage spike of the T5 tube is 513.1V when the circuit is flushed, the off-state voltage spike of the T5 tube is 164.7V when the buffer circuit is included, and the off-state voltage spike is greatly inhibited. The off-voltage spikes of the T6 and T7 tubes are not large in both cases.

FIG. 7 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of + U_CAnd 0, a simulation result chart with the current direction as positive, wherein the parasitic inductance on each line is taken as 20 muH. Fig. 7(a) shows an output voltage waveform. As shown in fig. 7(a), within 0-50 μ s, the switching tubes T1, T4, T6 and T7 are turned on to output one-time rated operating voltage of 100V; within 50-53 mu s, the switch tube T3 is switched on, and the switch tubes T4 and T7 are switched off; within 53-100 mu s, the switching tubes T1, T4 and T6 are conducted, and the output voltage is 0; within 100-103 mu s, the switching tubes T4 and T7 are switched on, and T3 is switched off; within 103-150 mu s, the switch tubes T1, T4, T6 and T7 are conducted to output one-time rated working voltage of 100V. Fig. 7(b) shows an output current waveform, where the output current is greater than 0. FIG. 7(c) shows voltage waveforms across the switching tubes T3 and T4 without the snubber circuit. FIG. 7(d) shows the voltage waveforms across the switching tubes T3, T4 including the snubber circuit. The result shows that the turn-off voltage spike of the T3 tube is 431.0V when the buffer circuit is not included, the turn-off voltage spike of the T3 tube is 166.9V when the buffer circuit is included, and the turn-off voltage spike is well restrained. The off-state voltage spike of the T4 tube is 235.3V when the buffer circuit is not included, the off-state voltage spike of the T4 tube is 100.8V when the buffer circuit is included, and the off-state voltage spike is well restrained.

FIG. 8 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of + U_CAnd 0, a graph of simulation results when the current direction is negative, taking the parasitic inductance on each line to be 20 muH. In fig. 8(a), the output voltage waveform is shown, and the switching tube operation timing is the same as the positive timing of the current direction. Fig. 8(b) shows an output current waveform, and the output current is less than 0. Fig. 8(c) shows voltage waveforms across the switching tubes T3 and T4 without the snubber circuit. FIG. 8(d) shows the voltage waveforms across the switching tubes T3, T4 including the snubber circuit. The result shows that the turn-off voltage peak of the T4 tube is 213.4V when the buffer circuit is not included, the turn-off voltage peak of the T4 tube is 118.1V when the buffer circuit is included, and the turn-off voltage peak is well obtainedInhibition of (3). The off-voltage spike of the T3 tube was not large in both cases.

FIG. 9 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd 0, a simulation result chart with the current direction as positive, wherein the parasitic inductance on each line is taken as 2 muH. Fig. 9(a) shows an output voltage waveform. As shown in fig. 9(a), within 0-50 μ s, the switching tubes T1, T4, and T5 are turned on to output twice the rated voltage 200V; within 50-53 mu s, the switching tubes T3 and T6 are switched on, and the switching tubes T4 and T5 are switched off; within 53-100 mu s, the switching tubes T1, T3 and T6 are conducted, and the output voltage is 0; within 100-103 mu s, the switching tubes T4 and T5 are switched on, and the switching tubes T3 and T6 are switched off; within 103-150 mu s, the switch tubes T1, T4 and T5 are conducted to output two times of rated voltage 200V. Fig. 9(b) shows an output current waveform, where the output current is greater than 0. Fig. 9(c) shows voltage waveforms across the switching tubes T3, T4, T5, and T6 without the snubber circuit. FIG. 9(d) shows waveforms of voltages across the switching tubes T3, T4, T5 and T6 including the snubber circuit. The result shows that the turn-off voltage spike of the T6 tube is 202.0V when the buffer circuit is not included, the turn-off voltage spike of the T6 tube is 123.3V when the buffer circuit is included, and the turn-off voltage spike is well suppressed. The turn-off voltage spikes of the switching tubes T3, T4, T5 are not large in both cases.

FIG. 10 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of +2U_CAnd 0, a simulation result graph when the current direction is negative, and the parasitic inductance on each line is taken to be 2 muH. In fig. 10(a), the output voltage waveform is shown, and the switching tube operation timing is the same as the positive timing of the current direction. Fig. 10(b) shows an output current waveform, where the output current is greater than 0. Fig. 10(c) shows voltage waveforms across the switching tubes T3, T4, T5, and T6 without the snubber circuit. FIG. 10(d) shows waveforms of voltages across the switching tubes T3, T4, T5 and T6 including the snubber circuit. The result shows that the turn-off voltage spike of the T4 tube is 376.4V when the buffer circuit is not included, the turn-off voltage spike of the T4 tube is 115.3V when the buffer circuit is included, and the turn-off voltage spike is well restrained. The T5 tube turn-off voltage spike is 450.9V when the buffer circuit is not included, the T4 tube turn-off voltage spike is 111.3V when the buffer circuit is included, and the turn-off voltage spike is well restrained. Opening deviceThe turn-off voltage spikes of the shut-off tubes T3, T4, T5 were not large in both cases.

FIG. 11 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of-U_CAnd 0, a simulation result chart with the current direction as positive, wherein the parasitic inductance on each line is taken as 2 muH. Fig. 11(a) shows an output voltage waveform. As shown in fig. 11(a), within 0-50 μ s, the switching tubes T2, T3, T6 and T7 are turned on to output a double reverse rated voltage of-100V; within 50-53 mu s, the switch tube T5 is switched on, and the switch tubes T6 and T7 are switched off; within 53-100 mu s, the switching tubes T2, T3 and T5 are conducted, and the output voltage is 0; within 100-103 mu s, the switching tubes T6 and T7 are switched on, and T5 is switched off; within 103-150 mu s, the switch tubes T2, T3, T6 and T7 are conducted to output one time reverse rated voltage of-100V. Fig. 11(b) shows an output current waveform, where the output current is greater than 0. Fig. 11(c) shows waveforms of voltages across the switching tubes T5, T6, and T7 without the snubber circuit. FIG. 11(d) shows voltage waveforms across the switching tubes T5, T6, and T7 including the snubber circuit. The result shows that the turn-off voltage spike of the T5 tube is 158.8V when the buffer circuit is not included, the turn-off voltage spike of the T5 tube is 134.4V when the buffer circuit is included, and the turn-off voltage spike is well suppressed. The turn-off voltage spikes of the switching tubes T6, T7 are not large in both cases.

FIG. 12 shows a half-full-bridge sub-module according to an embodiment of the present invention with an output level of-U_CAnd 0, a simulation result graph when the current direction is negative, and the parasitic inductance on each line is taken to be 2 muH. In fig. 12(a), the output voltage waveform is shown, and the switching tube operation timing is the same as the positive timing of the current direction. Fig. 12(b) shows an output current waveform, where the output current is greater than 0. Fig. 12(c) shows waveforms of voltages across the switching tubes T5, T6, and T7 without the snubber circuit. Fig. 12(d) shows voltage waveforms across the switching tubes T5, T6, and T7 including the snubber circuit. The result shows that the turn-off voltage spike of the T5 tube is 288.6V when the buffer circuit is not included, the turn-off voltage spike of the T5 tube is 180.7V when the buffer circuit is included, and the turn-off voltage spike is well restrained. The turn-off voltage spikes of the switching tubes T6, T7 are not large in both cases.

The half-full-bridge sub-module topology structure has an active inputGo out +2U_C、+U_C、0、-U_CWith the capacity of four levels, the MMC system based on the topological structure can realize direct-current fault ride-through and voltage-boosting operation.

In summary, under the condition of considering different current directions, in the conversion process between different levels, the IGBT of the half-full-bridge sub-module without the snubber circuit generates a large turn-off overvoltage in the turn-off process, and even reaches more than five times the rated working voltage of the capacitor. After the simplified buffer circuit is added, the turn-off overvoltage of all IGBTs of the half-full-bridge submodule in the turn-off process can be well inhibited, when the parasitic inductance parameter is not particularly large, the turn-off overvoltage can be guaranteed not to exceed 130V (1.3 times of the rated working voltage of the capacitor), even if the parasitic inductance parameter is large, the turn-off overvoltage does not exceed 170V (1.7 times of the rated working voltage of the capacitor), the rated voltage of a general switching tube is selected to be more than twice of the rated working voltage, and therefore the half-full-bridge submodule buffer circuit can meet the normal work of the half-full-bridge submodule.

Fig. 13 is a schematic diagram of a topology structure of a capacitor switch type half-full bridge sub-module buffer circuit according to an embodiment of the present invention. Compared with the structure shown in fig. 4, the structure is additionally provided with an eighth switching tube M1 and a ninth switching tube M2, wherein each of the switching tubes M1-M2 is formed by 1 SiCSMOSFET in anti-parallel connection with 1 diode. The specific connection mode is as follows:

the emitter of the first switch tube T1 is connected with the collector of the second switch tube T2, and the connection point is marked as a connection point P; the collector of the first switch tube T1, the emitter of the sixth switch tube T6 and the source of the eighth switch tube M1 are connected, and the connection point is marked as a connection point P1; the drain electrode of the eighth switching tube M1 is connected with the anode of the first capacitor C1; the emitter of the second switch tube T2, the emitter of the fifth switch tube T5, the collector of the seventh switch tube T7 and the negative electrode of the first capacitor C1 are connected, and the connection point is marked as a connection point N1; the collector of the fifth switching tube T5, the collector of the sixth switching tube T6, the collector of the third switching tube T3 and the source of the ninth switching tube M2 are connected, and the connection point is marked as a connection point P2; the drain of the ninth switching tube M2 is connected with the anode of the second capacitor C2; the emitter of the seventh switch tube T7, the emitter of the fourth switch tube T4 and the cathode of the second capacitor C2 are connected, and the connection point is marked as a connection point N2; the emitter of the third switching tube T3 is connected to the collector of the fourth switching tube T4, and the connection point thereof is denoted as connection point N.

Compared with Si IGBT, SiC MOSFET has the advantages of low on-resistance, fast switching speed, and excellent high-temperature characteristics. The sub-module topology combined with the Si IGBT and the SiC MOSFET can greatly reduce the system loss, and meanwhile, the system cost cannot be excessively increased.

The working principle of the buffer circuit in the capacitance switch type half-full-bridge submodule is as follows: the first group of RCD buffer circuits is used for restraining SiIGBT and SiC MOSFET turn-off voltage spikes of a left half-bridge module (comprising T1, T2 and M1), the second group of RCD buffer circuits is used for restraining SiIGBT and SiC MOSFET turn-off voltage spikes of a right half-bridge module (comprising T3, T4 and M2), and the third group of RCD buffer circuits is used for restraining IGBT turn-off voltage spikes of a connecting circuit (comprising T5, T6 and M7).

It will be understood by those skilled in the art that the foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included within the scope of the present invention.

Claims

1. A snubber circuit for a modular multilevel converter half-full-bridge sub-module, the half-full-bridge sub-module comprising: the device comprises a left half-bridge module, a right half-bridge module and a connecting circuit; wherein the left half-bridge module comprises: after the first switch tube T1 and the second switch tube T2 are connected in series, the first switch tube T1 and the second switch tube T2 are connected in parallel with the first capacitor C1 at a connection point P1 and a connection point N1; the right half-bridge module comprises: after the third switching tube T3 and the fourth switching tube T4 are connected in series, the third switching tube T3 and the fourth switching tube T4 are connected in parallel with the second capacitor C2 at a connection point P2 and a connection point N2; the connection circuit comprises a fifth switch tube T5, a sixth switch tube T6 and a seventh switch tube T7, the sixth switch tube T6 is bridged between a connection point P1 and a connection point P2 of the left and right half-bridge modules, the seventh switch tube T7 is bridged between a connection point N1 and a connection point N2 of the left and right half-bridge modules, the fifth switch tube T5 is connected between the sixth switch tube T6 and the seventh switch tube T7, and the characteristics are that,

the third group of RCD buffer circuit connection point A is connected with a half-full-bridge submodule connection point P1, and the connection point B is connected with a half-full-bridge submodule connection point N2;

when the fifth switching tube T5 is turned off and the sixth switching tube T6 and the seventh switching tube T7 are closed, two ends of the T5 are simultaneously connected in parallel to the first group of RCD buffer circuits, the second group of RCD buffer circuits and the third group of RCD buffer circuits;

when the fifth switching tube T5 is closed and the sixth switching tube T6 and the seventh switching tube T7 are turned off, two ends of the T6 are connected with the first group of RCD buffer circuits in parallel, two ends of the T7 are connected with the second group of RCD buffer circuits in parallel, and the T6 and the T7 are connected in series and then connected with the third group of RCD buffer circuits in parallel;

the left half-bridge module further comprises an eighth switch tube M1 connected in series with the first capacitor C1 at a connection point P1 and a connection point N1; the right half-bridge module further comprises a ninth switching tube M2 connected in series with the first capacitor C2 at a connection point P2 and a connection point N2; each of the switching tubes M1-M2 is composed of 1 SiC MOSFET and 1 diode connected in anti-parallel.

2. The snubber circuit of claim 1, wherein each switch transistor of T1-T7 is formed by 1 IGBT connected in anti-parallel with 1 diode.

3. The snubber circuit of claim 2, wherein the half-full-bridge submodules are specifically connected in a manner of:

4. The snubber circuit of claim 2 or 3, wherein the capacitance C in the RCD snubber circuit is calculated by the formula:

wherein, I_pIs the peak value of IGBT collector current, U_CIs the rated working voltage, t, of the capacitor in the RCD buffer circuit_fThe voltage rise time of two ends of a capacitor in the RCD buffer circuit is obtained;

3RC＝t_on(min)

wherein, t_on(min)The minimum on-time of the IGBT is obtained, and C is the size of a capacitor in the RCD buffer circuit;