CN109037067A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109037067A CN109037067A CN201810881618.1A CN201810881618A CN109037067A CN 109037067 A CN109037067 A CN 109037067A CN 201810881618 A CN201810881618 A CN 201810881618A CN 109037067 A CN109037067 A CN 109037067A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 230000009467 reduction Effects 0.000 claims abstract description 6
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims abstract description 4
- 102000013275 Somatomedins Human genes 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 32
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910002601 GaN Inorganic materials 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- IWBUYGUPYWKAMK-UHFFFAOYSA-N [AlH3].[N] Chemical compound [AlH3].[N] IWBUYGUPYWKAMK-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application proposes a kind of semiconductor devices and its manufacturing method, comprising: successively grown buffer layer and barrier layer on the first substrate；First grid is grown on the barrier layer, forms first structure；The somatomedin layer in the first structure；By the dielectric layer and the second substrate bonding, and first substrate is removed, forms the second structure；Second structure is inverted, and reduction processing is carried out to the buffer layer；Source electrode, drain electrode and second grid are grown on the buffer layer after being thinned.The semiconductor devices and its manufacturing method that the application is proposed, reduce contact resistance, reduce the distance between backgate and two-dimensional electron gas, enhance the control ability to channel.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor devices and its manufacturing method.
Background technique
There are many excellent characteristics with GaAs (GaAs), the compound semiconductor materials that gallium nitride (GaN) is representative,
Such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas and good high temperature operation capability.Based on chemical combination
The devices such as the high electron mobility transistor (HEMT) of object semiconductor, hetero-structure field effect transistor (HFET) have been obtained
It is widely applied, especially needs high-power and high-frequency field to have a clear superiority in radio frequency, microwave etc..
The compound semiconductor of back grid structure is being led on the basis of traditional source, leakage, three pole compound semiconductor of grid
The back side of electric channel increases a grid, this grid is commonly known as backgate.Under being controlled while two grids, conducting channel
It can be controlled well, to reduce electric leakage or increase the modulation capability to channel current.But in compound semiconductor
Field, never suitable technique realizes the back grid structure only academic documents report using anisotropic deep silicon
Etching locally removes substrate, but this method is suitable only for the gallium nitride device of silicon substrate, and the back grid structure that manufactures away from
It is too far from conducting channel, it is weaker to the control action of channel.
On the other hand, in traditional gallium nitride HEMT technique, source, drain electrode are typically fabricated in potential barrier layer surface.But by
It is usually to be made of the bigger alloy crystal of forbidden bandwidth in barrier layer, so to form the source of low ohm contact resistance, leakage
Electrode is relatively difficult, this is also always to restrict one of the difficult point that HEMT performance improves.
Summary of the invention
Based on this, the present invention provides a kind of new semiconductor power device structure and its manufacturing method.
The application proposes a kind of method, semi-conductor device manufacturing method, comprising:
Successively grown buffer layer and barrier layer on the first substrate；
First grid is grown on the barrier layer, forms first structure；
The somatomedin layer in the first structure；
By the dielectric layer and the second substrate bonding, and first substrate is removed, forms the second structure；
Second structure is inverted, and reduction processing is carried out to the buffer layer；
Source electrode, drain electrode and second grid are grown on the buffer layer after being thinned.
In one embodiment, before growing second grid, dielectric layer is grown on the buffer layer after described be thinned.
In one embodiment, the dielectric layer with a thickness of 1nm-10nm.
In one embodiment, by before the dielectric layer and the second substrate bonding, bonding is formed on the dielectric layer
Layer.
In one embodiment, buffer layer thickness is greater than 1um before being thinned, and buffer layer is 20nm-100nm after being thinned.
In one embodiment, the second grid is aligned with the first grid.
Correspondingly, the application also proposes a kind of semiconductor devices, using semiconductor making method described in above-mentioned Arbitrary Term
It is prepared.
The semiconductor devices and its manufacturing method that the application is proposed, reduce contact resistance, reduce bigrid and two
The distance between dimensional electron gas enhances the control ability to channel；And can will be inexpensive, the transfer of the epitaxial film of high quality
To meet requirement of the power device to heat dissipation on to high-termal conductivity substrate；Or by epitaxial film from being difficult to do back via process
Substrate is transferred on the substrate for being easy to do the technique, meets requirement of the microwave device to ground connection.
Detailed description of the invention
Fig. 1 is the flow chart of semiconductor making method proposed by the invention；
Fig. 2-Fig. 7 indicates to prepare the schematic diagram of semiconductor devices according to some embodiments of the present invention；
Fig. 8 is the structure chart of semiconductor devices proposed by the invention.
Specific embodiment
Semiconductor devices proposed by the present invention and its manufacturing method are made below in conjunction with the drawings and specific embodiments further
It is described in detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing
It is all made of very simplified form and uses non-accurate ratio, only to convenient, lucidly the aid illustration present invention is implemented
The purpose of example.
Fig. 1-Fig. 7 is please referred to, the present embodiment proposes a kind of method, semi-conductor device manufacturing method, comprising:
Successively grown buffer layer 2 and barrier layer 3 on S10: the first substrate 1.
Wherein, 1 material of the first substrate can be silicon carbide, sapphire, silicon etc., and the thickness of first substrate 1 exists
300um or more.The buffer layer 2 forms two-dimensional electron gas (2DEG) close to the surface of described 3 one end of barrier layer, the 2DEG tool
There are high electron density and high electron mobility, to form conducting channel.It is brilliant that the buffer layer 2 can be gallium nitride high quality
Body, the barrier layer 3 can be the iii v compound semiconductors alloys such as aluminum gallium nitride, indium aluminium nitrogen.The thickness of the buffer layer 2 is big
In 1um, the barrier layer 3 with a thickness of 10nm-50nm.The structure that first substrate 1, buffer layer 2 and barrier layer 3 are formed is such as
Shown in Fig. 2.
S20: first grid 6 is grown on the barrier layer 3.
The first grid 6 is grown in the non-ohmic contact area on the barrier layer 3, forms Xiao Te with the barrier layer 3
Base contact, forms structure as shown in Figure 3.Growing first grid 6 includes the works such as photoetching, metal evaporation, cleaning and short annealing
Skill.It is to be appreciated that above-mentioned technique is the common knowledge of this field, no longer specifically illustrated herein.Stating first grid 6 can
Think the metal laminated of the compositions such as nickel, gold, platinum.The buffer layer 2, barrier layer 3 and first grid 6 form first structure.
S30: the somatomedin layer 7 in the first structure.
Wherein, it after the source electrode 4, drain electrode 5 and first grid 6 complete, needs to be used in one layer of dielectric layer 7 of covering
Guard electrode, the dielectric layer 7 cover the surface of first structure, i.e., source electrode 4, drain electrode 5, first grid 6 and barrier layer 3 is complete
Portion's covering.After the completion of covering, technique is polished directly to 7 surface of dielectric layer, makes 7 surface planarisation of dielectric layer, formed
Structure as shown in Figure 4.The dielectric layer 7 can be the insulating materials such as silicon nitride or silica.
S40: the dielectric layer 7 is bonded with the second substrate 8, and removes first substrate 1.
After the dielectric layer 7 is formed, choose other one piece of substrate wafer, i.e. the second substrate 8, will second substrate 8 and
The dielectric layer 7 is bonded.The material of second substrate 8 can be material identical with the first substrate 1, can also be with the second lining
Bottom 8 is different, such as aluminium nitride, silicon carbide, ceramics, quartz, metal substrate etc..The method of bonding can there are many, such as model moral
Magnificent power bonding, organic film bonding, alloy bonding, metal heat pressing bonding etc. are specifically chosen which kind of bonding method is needed according to tool
Depending on the physical characteristic especially operating temperature of thermal expansion character and device of 8 material of the second substrate of body.In order to more
It is bonded the second substrate 8 with dielectric layer 7, one layer of bonded layer can be initially formed between the second substrate 8 and first structure, thus
Second substrate 8 is combined together with dielectric layer 7.The bonding layer material can be silica, aluminium oxide, polytetrafluoroethyl-ne
Any one in the materials such as alkene, epoxy resin, benzocyclobutene, base resin high polymer, gold, copper, silver, tin, silicon or indium.
After second substrate 8 is bonded with the dielectric layer 7, first substrate 1 is removed.For different substrate materials
Material, the removal technique used are also very different.Such as sapphire wafer, laser scanning stripping is can be used in Sapphire Substrate
From technology.For the wafer of silicon substrate, silicon substrate adds dry etching removal after grinding can be used again.The knot formed after removal substrate
Structure is as shown in Figure 5.The first substrate is removed on the basis of the first structure and the second substrate of bonding is formed by structure and is known as
Second structure.
S50: second structure is inverted, and carries out reduction processing to the buffer layer 2.
The second original structure is that buffer layer 2 is located at bottom end, and the second substrate 8 is located at top.It is after inversion the result is that buffering
Layer 2 is located at top, and the second substrate 8 is located at bottom end.After above-mentioned second substrate 7 bonding, the removal of the first substrate 1 and it is inverted the
After two structures, original epitaxial structure and the electrode made have been transferred on new wafer, and the second substrate 8 is as support lining
Bottom, first grid 6 become backgate, can continue subsequent manufacturing process on this basis.After the buffer layer 2 is located at top,
It needs to carry out reduction processing to the buffer layer 2.Reduction processing can be needed using the techniques such as etching, grinding, concrete technology condition
It to be selected according to the material of the buffer layer 2.Buffer layer 2 after being thinned with a thickness of 20nm-100nm, formed as shown in FIG. 6
Structure.
S60: source electrode 4, drain electrode 5 and second grid 9 are grown on the buffer layer 2 after being thinned.
After buffer layer is thinned, source electrode 4, drain electrode 5 and second grid 9, the growth institute are grown respectively on the buffer layer 2
The technique for stating source electrode 4, drain electrode 5 and second grid 9 includes photoetching, vapor deposition, cleaning.5 difference position of the source electrode 4 and drain electrode
In the two sides of the second grid.The source electrode 4 and drain electrode 5 can be a variety of compositions any in the materials such as titanium, aluminium, nickel, gold, tungsten
Alloy.The second grid 9 can be the metal laminated of the compositions such as nickel, gold, platinum.On the other hand, according to gallium nitride material
Feature, the gallium nitride surface that source, drain electrode are located is usually nitrogen face polar.Different from gallium face polarity, chemistry with higher is living
Jump property.Before source, drain metal are formed, low contact electricity can be obtained by being surface-treated the method such as wet chemical process
The electrode of resistance.In order to enable first grid 6 and second grid 9 to control the conducting or truncation of channel, the second gate simultaneously
Pole 9 needs to be aligned with first grid 6, common lithography alignment technology very thin since later buffer layer, barrier layer thickness is thinned
Alignment can be carried out to the metal layer of second grid, ultimately form structure as shown in Figure 7 with perspective material.In addition, in other realities
It applies in example, before second grid growth, dielectric layer can be grown on the buffer layer after being thinned, to reduce the leakage of second grid
Electric current.The dielectric layer with a thickness of 1-10nm, material can be silicon nitride or silica.
It is lower to be moved on to forbidden bandwidth by method, semi-conductor device manufacturing method provided herein for the production in source, drain electrode
On nitride buffer layer, it is relatively easy to production Ohmic contact.Simultaneously as later nitride buffer layer surface, which is thinned, is
Nitrogen face polar can effectively reduce ohmic contact resistance using additional surface treatment method.And two grids and device
The distance between two-dimensional electron gas very little in part channel, compared to traditional coplanar single gridistor, which increase to conduction
The control ability of channel.If two grids simply apply same control signal, compared to traditional single gridistor,
Channel can be truncated from two surface synchronizations, therefore electric leakage can be reduced, improve transistor shut-off feature.Two grids can be with
Apply different control signals, such as a grid does direct current biasing, applies pulse control signal on another grid, it is straight in this way
Then stream biasing can be opened with pre-cut channel by pulse signal, to realize enhanced HEMT device, widen significantly
Application of the compound semiconductor device in power device field.
Furthermore the advantages of the application uses wafer bond techniques material for transfer, can make full use of two kinds of substrate materials, from
And improve the performance of device.For example, gallium nitride material usually can with epitaxial growth in sapphire, silicon or silicon carbide substrates,
And respectively there are advantage and disadvantage.Using method of the invention, can will be inexpensive, the substrate of epitaxial film from the poor heat conductivity of high quality is such as blue
Jewel is transferred to requirement of for example thermally conductive aluminum-nitride-based on piece of high-termal conductivity substrate to meet power device to heat dissipation；Or by extension
Film is transferred on the substrate such as silicon wafer for being easy to do the technique from the substrate such as sapphire for being difficult to do back via process, meets microwave
Requirement of the device to ground connection.Also, method provided herein is used, is conducive to the device of different function being integrated in one
It rises, improves the integrated level of system to realize system on chip (SOC).For example, the structure of gallium nitride microwave power amplifier is contained together
There is the silicon substrate large scale integrated circuit of digital predistortion circuit (DPD) to combine, to realize mixed signal (Mix Signal)
The single-chip integration of radio-frequency front-end.
Correspondingly, the application also proposes a kind of semiconductor structure, the semiconductor system proposed using any of the above-described embodiment
The method of making is prepared.
Referring to FIG. 8, the semiconductor structure includes: substrate 8 (i.e. the second substrate), dielectric layer 7, barrier layer 3, buffer layer
2, source electrode 4, drain electrode 5, first grid 6 and second grid 9.The dielectric layer 7 is located on the substrate 8, and the barrier layer 3 is located at
On the dielectric layer.The first grid 6 (i.e. backgate) is located in the groove of the dielectric layer 7, is connected with the barrier layer 3
It connects.The buffer layer 2 is located on the barrier layer 3.The source electrode 4, drain electrode 5 and second grid 9 are located on buffer layer 3, with institute
State the alignment of first grid 6.The two sides for being located at the second grid 9 of the source electrode 4 and drain electrode 5.
8 material of substrate can be described for sapphire, silicon, aluminium nitride, silicon carbide, ceramics, quartz, metal substrate etc.
The thickness of substrate 8 is in 300um or more.The buffer layer 2 forms two-dimensional electron gas close to the surface of described 3 one end of barrier layer
(2DEG), the 2DEG have high electron density and high electron mobility.It is brilliant that the buffer layer 2 can be gallium nitride high quality
Body, the barrier layer 3 can be the iii v compound semiconductors alloys such as aluminum gallium nitride, indium aluminium nitrogen.The buffer layer 2 with a thickness of
20nm-100nm, the barrier layer 3 with a thickness of 10nm-50nm.
The first grid 6 and second grid 9 can be the metal laminated of the compositions such as nickel, gold, platinum, the source electrode 4 and leakage
Pole 5 can be the alloy of any a variety of compositions in the metals such as titanium, aluminium, nickel, gold.
The dielectric layer 7 can be the insulating materials such as silicon nitride or silica.
In the present embodiment, it is additionally provided with dielectric layer 10 between the second grid 9 and shown buffer layer 2, to reduce second
The leakage current of grid.The dielectric layer 10 with a thickness of 1-10nm, material can be silicon nitride or silica.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (7)
1. a kind of method, semi-conductor device manufacturing method characterized by comprising
Successively grown buffer layer and barrier layer on the first substrate；
First grid is grown on the barrier layer, forms first structure；
The somatomedin layer in the first structure；
By the dielectric layer and the second substrate bonding, and first substrate is removed, forms the second structure；
Second structure is inverted, and reduction processing is carried out to the buffer layer；
Source electrode, drain electrode and second grid are grown on the buffer layer after being thinned.
2. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that before growing second grid,
It is described be thinned after buffer layer on grow dielectric layer.
3. method, semi-conductor device manufacturing method according to claim 2, which is characterized in that the dielectric layer with a thickness of 1nm-
10nm。
4. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that by the dielectric layer and the second substrate
Before bonding, bonded layer is formed on the dielectric layer.
5. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that buffer layer thickness is greater than before being thinned
1um, buffer layer is 20nm-100nm after being thinned.
6. method, semi-conductor device manufacturing method according to claim 1, which is characterized in that the second grid and described first
Gate alignment.
7. a kind of semiconductor devices, which is characterized in that using the semiconductor making method system as described in claim 1-6 Arbitrary Term
It is standby to form.
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Address after: 215000 west side of b0-1f, Zhongyuan industrial building, No. 259, Changyang street, Suzhou Industrial Park, Suzhou area, China (Jiangsu) pilot Free Trade Zone, Suzhou City, Jiangsu Province Applicant after: Suzhou Han Hua Semiconductor Co.,Ltd. Address before: Room 303, building 11, Northwest District, Suzhou nano City, 99 Jinjihu Avenue, Suzhou Industrial Park, 215000, Jiangsu Province Applicant before: Suzhou Han Hua Semiconductor Co.,Ltd. |
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Application publication date: 20181218 |