CN108986866B - Read high voltage transmission circuit - Google Patents
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- CN108986866B CN108986866B CN201810800624.XA CN201810800624A CN108986866B CN 108986866 B CN108986866 B CN 108986866B CN 201810800624 A CN201810800624 A CN 201810800624A CN 108986866 B CN108986866 B CN 108986866B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The invention discloses a read high voltage transmission circuit, comprising: a logic circuit for converting the ERASE permission signal ERASE, the program permission signal PROG into a high voltage permission signal EPEN and a read permission signal EN; the control circuit is used for converting the high-voltage enabling signal EPEN and the reading enabling signal EN into a high-voltage transmission control signal Vgate; the transmission circuit is used for transmitting the read high voltage VD25 to the high voltage ZDDL node during reading under the control of the high voltage transmission control signal Vgate, and disconnecting the read high voltage VD25 from the output high voltage ZDDL node during erasing and programming.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a read high-voltage transmission circuit.
Background
In general, the split gate flash applies a high voltage of 2.5V to the word line during a read operation; 1.5V voltage is added to a word line during programming; when erasing, 12V high voltage is added on the word line, in the high-speed design process, 5V is introduced to accelerate the reading speed, and when reading operation is carried out, the word line voltage establishment speed influences the final reading speed.
Fig. 1 is a circuit configuration diagram of a conventional read high voltage transmission circuit. As shown in fig. 1, a source and a substrate of a PMOS transistor P1 are connected with a read high voltage VD25, a drain of a PMOS transistor P1 is connected with a source of a PMOS transistor P2, a drain and a substrate of a PMOS transistor P2 are connected with a high voltage ZVDDL, a gate of a PMOS transistor P1 is connected with a first enable signal EN1, a gate of a PMOS transistor P2 is connected with a second enable signal EN2, and the read high voltage transmission circuit is connected in series through two PMOS transistors P1 and P2 to avoid the influence of a body effect. In particular, the amount of the solvent to be used,
during a read operation, the first enable signal EN1 and the second enable signal EN2 are 0, the PMOS transistors P1 and P2 are both turned on, and ZVDDL is VD 25; in a program or erase operation, the first enable signal EN1 is 2.5V, the second enable signal EN2 is ZVDDL, and the PMOS transistors P1 and P2 are both turned off, so that the path can be turned off.
However, in the prior art, because two MOS transistors are connected in series, the parasitic resistance-capacitance RC is large, and the transmission speed is slow.
Disclosure of Invention
To overcome the above-mentioned deficiencies of the prior art, the present invention provides a high voltage reading transmission circuit to reduce the voltage drop, increase the high voltage transmission speed, and finally increase the word line voltage establishment speed, and prevent the over-charging of ZVDDL to VD25 during the erase operation, so as to protect the same.
To achieve the above and other objects, the present invention provides a read high voltage transmission circuit, including:
a logic circuit for converting the ERASE permission signal ERASE, the program permission signal PROG into a high voltage permission signal EPEN and a read permission signal EN;
the control circuit is used for converting the high-voltage enabling signal EPEN and the reading enabling signal EN into a high-voltage transmission control signal Vgate;
and the transmission circuit is used for transmitting the read high voltage VD25 to the high voltage ZDDL node during reading under the control of the high voltage transmission control signal Vgate, and disconnecting the read high voltage VD25 from the output high voltage ZDDL node during erasing and programming.
Preferably, the transmission circuit utilizes an NMOS transistor for transmission, and utilizes a high voltage transmission control signal Vgate to control the transmission of the high voltage of the word line during the read operation.
Preferably, the logic circuit includes a nor gate, a first level shifter and a second level shifter, the ERASE permission signal ERASE and the program permission signal PROG are connected to both input terminals of the nor gate, an output terminal of the nor gate is connected to a permission input terminal EN1 of the first level shifter, a high voltage ZVDD is connected to a high voltage input terminal HVIN of the first level shifter, an output of the first level shifter, i.e., a high voltage permission signal EPEN, is connected to the control circuit, the ERASE permission signal ERASE is connected to a permission input terminal EN2 of the second level shifter, a read high voltage VD25 is connected to a high voltage input terminal HVIN of the second level shifter, and an output of the second level shifter, i.e., a read permission signal EN, is connected to the control circuit.
Preferably, the control circuit comprises a first PMOS transistor P1, a first NMOS transistor N1, a second PMOS transistor P2 and a second NMOS transistor N2, the high-voltage enable signal EPEN is connected to the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1, and the read enable signal EN is connected to the gate of the second PMOS transistor P2 and the gate of the second NMOS transistor N2; the read high voltage VD25 is connected to the source electrode of a second PMOS tube P2, the source electrode of a second NMOS tube N2 is grounded, the drain electrode of the second PMOS tube P2 is connected with the drain electrode of a second NMOS tube N2 and the source electrode of a first NMOS tube N1 to form a read voltage Vs node, the high voltage ZVDD is connected to the source electrode of a first PMOS tube P1, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1 and the transmission circuit to form a high voltage transmission control signal Vgate node.
Preferably, the transmission circuit comprises an NMOS transistor N0, and the drain of the first PMOS transistor P1 is connected to the drain of a first NMOS transistor N1 and the gate of the NMOS transistor N0 to form the high voltage transmission control signal Vgate node; the read high voltage VD25 is connected to the drain of the NMOS transistor N0, and the source of the NMOS transistor N0 is connected to the output high voltage ZDDL node.
Preferably, the transmission circuit uses a high voltage transmission control signal Vgate to control the transmission of the word line high voltage in the read operation, and the high voltage transmission control signal Vgate is greater than or equal to VD25+ Vth in the read operation.
Preferably, during a read operation, the read enable signal EN output by the second level shifter turns on the second NMOS transistor N2, and at the same time, the high-voltage enable signal EPEN output by the first level shifter turns on the first PMOS transistor P1, and the high-voltage transmission control signal Vgate ═ ZVDD turns on the NMOS transistor N0, and the internal high voltage ZVDD ≧ VD25+ Vth.
Preferably, during programming, the second NMOS transistor N2 is turned on by the read permission signal output by the second level shifter, the first NMOS transistor N1 is turned on by the high voltage permission signal EPEN output by the first level shifter, and the NMOS transistor N0 is turned off by the high voltage transmission control signal Vgate ═ Vs ═ 0.
Preferably, during erasing, the read enable signal EN output by the second level shifter turns on the second PMOS transistor P2, and at the same time, the high-voltage enable signal EPEN output by the first level shifter turns on the first NMOS transistor N1, and the high-voltage transmission control signal Vgate ═ Vs ═ VD25 turns off the NMOS transistor N0.
Preferably, at the end of the erase operation, the high voltage ZVDD is discharged to Vgate for the read operation, where Vgate is greater than or equal to VD25+ Vth, and the output high voltage ZVDDL is ZVDD; when the standby mode is entered, the NMOS tube N0 is conducted, and due to the loss of threshold voltage of the NMOS, the reading high voltage VD25 is limited to the voltage value Vgate-Vth, so that the coupling effect of the output high voltage ZDDL on the reading high voltage VD25 is eliminated, and the reading high voltage VD25 is protected from being coupled to the high voltage.
Compared with the prior art, the read high-voltage transmission circuit controls the transmission of the high voltage of the word line during the read operation by using the NMOS tube for transmission and using the high-voltage transmission control signal Vgate (the Vgate is more than or equal to VD25+ Vth, 5V is selected in the invention) so as to achieve the purposes of reducing the voltage drop, accelerating the high-voltage transmission speed and finally accelerating the establishment speed of the word line voltage, and meanwhile, the read high-voltage VD25 can be prevented from being overcharged by ZDDL during the erase operation, thereby playing a role in protection.
Drawings
FIG. 1 is a circuit diagram of a conventional read high voltage transmission circuit;
FIG. 2 is a schematic diagram of a read high voltage transmission circuit according to the present invention;
FIG. 3 is a comparison graph of simulation results when the read high voltage transmission circuit of the prior art and the read high voltage transmission circuit of the present invention read.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a schematic structural diagram of a read high voltage transmission circuit according to the present invention. As shown in fig. 2, the read high voltage transmission circuit of the present invention includes: a logic circuit 10, a control circuit 20 and a transmission circuit 30.
Wherein the logic circuit 10 is composed of a NOR gate NOR1, a first level shifter LS1 and a second level shifter LS2, and converts the ERASE permission signal ERASE, the program permission signal PROG into a high voltage permission signal EPEN and a read permission signal EN; the control circuit 20 is composed of a PMOS transistor P1, an NMOS transistor N1, a PMOS transistor P2 and an NMOS transistor N2, and is configured to convert the high-voltage enable signal EPEN and the read enable signal EN into a high-voltage transmission control signal Vgate; the transmission circuit 30 is composed of an NMOS transistor N0, and is used for transmitting the read high voltage VD25 to the high voltage ZVDDL node during reading under the control of the high voltage transmission control signal Vgate, and disconnecting the read high voltage VD25 from the output high voltage ZVDDL node during erasing and programming.
The ERASE permission signal ERASE and the program permission signal PROG are connected to two input terminals of the NOR gate NOR1, an output terminal of the NOR gate NOR1 is connected to a permission input terminal EN1 of the first level shifter LS1, the high voltage ZVDD is connected to a high voltage input terminal HVIN of the first level shifter LS1, and an output of the first level shifter LS1, that is, the high voltage permission signal EPEN, is connected to a gate of the PMOS transistor P1 and a gate of the NMOS transistor N1; the ERASE permission signal ERASE is further connected to a permission input terminal EN2 of a second level shifter LS2, the read high voltage VD25 is connected to a high voltage input terminal HVIN of the second level shifter LS2, and an output of the second level shifter LS2, that is, the read permission signal EN, is connected to a gate of the PMOS transistor P2 and a gate of the NMOS transistor N2; the read high voltage VD25 is connected to the source electrode of a PMOS tube P2, the source electrode of an NMOS tube N2 is grounded, the drain electrode of the PMOS tube P2 is connected with the drain electrode of an NMOS tube N2 and the source electrode of an NMOS tube N1 to form a read voltage Vs node, the high voltage ZVDD is connected to the source electrode of a PMOS tube P1, and the drain electrode of the PMOS tube P1 is connected with the drain electrode of an NMOS tube N1 and the gate electrode of an NMOS tube N0 to form a high voltage transmission control signal Vgate node; the read high voltage VD25 is connected to the drain of NMOS transistor N0, and the source of NMOS transistor N0 is connected to the output high voltage ZDDL node.
The working process of the present invention will be described below with reference to table 1: in the embodiment of the present invention, the present invention is transmitted by an NMOS transistor, and the transmission of the word line high voltage during the read operation is controlled by a high voltage transmission control signal Vgate, and the working voltmeter is shown in table 1:
TABLE 1
| Operation | VD25 | ZVDD | Vs | EPEN | Vgate | ZVDDL |
| Read | 2.5V | 5V | 0V | 0V | 5V | 2.5V |
| Program | 2.5V | 8V | 0V | 8V | 0V | 1.5V |
| Erase | 2.5V | 12V | 2.5V | 12V | 2.5V | 12V |
During the read operation, the read high voltage VD25 is 2.5V, the internal high voltage ZVDD is 5V, the read permission signal EN output by the second level shifter LS2 is VD25 is 2.5V, the NMOS transistor N2 is turned on, the read voltage Vs is 0V, meanwhile, the high voltage permission signal EPEN output by the first level shifter LS1 is 0V, the PMOS transistor P1 is turned on, the high voltage transmission control signal Vgate is ZVDD (the internal high voltage ZVDD is equal to or greater than 25+ Vth, where Vth is the threshold of the NMOS transistor N0, and preferably, in the embodiment of the present invention, ZVDD is 5V), the NMOS transistor N0 is turned on, and the output high voltage zl is VD25 vdd2 is 2.5V.
During programming, the read high voltage VD25 is 2.5V, the internal high voltage ZVDD is 8V, the read permission signal EN output by the second level shifter LS2 is 2.5V, the NMOS transistor N2 is turned on, the read voltage Vs is 0V, the high voltage permission signal EPEN output by the first level shifter LS1 is 8V, the NMOS transistor N1 is turned on, the high voltage transmission control signal Vgate is Vs is 0V, the NMOS transistor N0 is turned off, and the output high voltage ZVDDL is 1.5V.
When erasing, the read high voltage VD25 is 2.5V, the internal high voltage ZVDD is 12V, the read permission signal EN output by the second level shifter LS2 is 0V, the PMOS transistor P2 is turned on, the read voltage Vs is VD25 is 2.5V, the high voltage permission signal EPEN output by the first level shifter LS1 is 12V, the NMOS transistor N1 is turned on, the high voltage transmission control signal Vgate is Vs 2.5V, the NMOS transistor N0 is turned off, the output high voltage ZVDDL is 12V, and the high voltage transmission control signal Vgate is 2.5V for reducing GIDL (gate-induced Drain Leakage) effect of the NMOS transistor N0.
When the erasing operation is finished, the high voltage ZVDD is discharged to Vgate during the reading operation, namely Vgate is more than or equal to VD25+ Vth, and the output high voltage ZVDDL is equal to ZVDD; when entering a standby (standby) mode, the NMOS tube N0 is conducted, and due to the loss of threshold voltage of the NMOS, the reading high voltage VD25 is limited to the voltage value Vgate-Vth, so that the coupling effect of the output high voltage ZDDL on the reading high voltage VD25 is eliminated, and the reading high voltage VD25 is protected from being coupled to the high voltage.
The high-voltage reading transmission is carried out by using an NMOS tube N0, a high-voltage transmission control signal Vgate is more than or equal to VD25+ Vth during reading, the Vth is the threshold value of the NMOS tube N0, preferably, the Vgate is 5V, the loss of the threshold voltage is considered, and the Vgate-Vth is less than or equal to VD25, so that a protection effect is achieved.
FIG. 3 is a comparison graph of simulation results when the read high voltage transmission circuit of the prior art and the read high voltage transmission circuit of the present invention read. As shown in figure 3 of the drawings,
in the SS corner (SS corner, Slow NMOS Slow PMOS), the read high voltage VD25 is 2.4V;
the instantaneous voltage drop of the output high voltage ZVDDL at the time of inversion is reduced from 0.808V (2.4-1.592) to 0.29V (2.4-2.11), as shown in table 2, ZVDDL _ post is a true value of the output high voltage ZVDDL of the present invention, and ZVDDL _ pre is a true value of the output high voltage ZVDDL of the prior art;
TABLE 2
| VD25 | ZVDDL_post | ZVDDL_pre | |
| 2.4 | 2.11 | 1.592 | |
| Delta | -0.29 | -0.808 |
The ramp rate is reduced from 4.367nS to 3.8nS (13%), as shown in FIG. 3, V (zvdd) ss01.tr0 is the high voltage input of the present invention (voltage at cursor is 4.99V), V (zvdd) ss00.tr0 is the prior art high voltage input (voltage at dashed line 4.979V), both are substantially overlapped, the intermediate node V (zvdd2) ss01.tr0 of the present invention is substantially matched with the prior art intermediate node V (zvdd2) ss00.tr0, the output high voltage V (zvdd1) ss01.tr0(2.175) of the present invention is significantly higher at dashed line (output high voltage flip instant) than the prior art output high voltage V (zvdd1) ss00.tr0(1.592), V (wl [0]) ss01.tr0 is the output high voltage ramp of the present invention [0] when the word line is selected for reading, the output high voltage ramp up curve of the present invention [0] when V (zvdd [ 0.tr0 ] is selected for reading, the word line voltage ramp up of the present invention is significantly higher than when the word line is selected (zwl [0] 3.8) when the word line is selected for reading the prior art word line (selected).
Therefore, the read high-voltage transmission circuit controls the transmission of the high voltage of the word line during the read operation by using the NMOS tube for transmission and using the high-voltage transmission control signal Vgate (the Vgate is more than or equal to VD25+ Vth, and 5V is selected in the invention) so as to achieve the purposes of reducing the voltage drop, accelerating the high-voltage transmission speed and finally accelerating the establishment speed of the word line voltage, and meanwhile, the read high-voltage VD25 can be prevented from being overcharged by ZDDL during the erase operation, thereby playing a role in protection.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A read high voltage transmission circuit comprising:
a logic circuit for converting the ERASE permission signal ERASE and the program permission signal PROG into a high voltage permission signal EPEN and converting the ERASE permission signal ERASE into a read permission signal EN;
a control circuit for converting the high voltage enable signal EPEN and the read enable signal EN into a high voltage transmission control signal Vgate;
and the transmission circuit is used for transmitting the read high voltage VD25 to the output high voltage ZDDL node during reading under the control of the high voltage transmission control signal Vgate, and disconnecting the read high voltage VD25 from the output high voltage ZDDL node during erasing and programming.
2. The read high voltage transmission circuit of claim 1, wherein: the logic circuit includes a nor gate, a first level shifter and a second level shifter, the ERASE permission signal ERASE and the program permission signal PROG are connected to both input terminals of the nor gate, an output terminal of the nor gate is connected to a permission input terminal EN1 of the first level shifter, an internal high voltage ZVDD is connected to a high voltage input terminal HVIN of the first level shifter, an output of the first level shifter, i.e., a high voltage permission signal EPEN, is connected to the control circuit, the ERASE permission signal ERASE is connected to a permission input terminal EN2 of the second level shifter, a read high voltage VD25 is connected to a high voltage input terminal HVIN of the second level shifter, and an output of the second level shifter, i.e., a read permission signal EN, is connected to the control circuit.
3. The read high voltage transmission circuit of claim 2, wherein: the control circuit comprises a first PMOS tube P1, a first NMOS tube N1, a second PMOS tube P2 and a second NMOS tube N2, the high-voltage enabling signal EPEN is connected to the grid electrode of the first PMOS tube P1 and the grid electrode of the first NMOS tube N1, and the reading enabling signal EN is connected to the grid electrode of the second PMOS tube P2 and the grid electrode of the second NMOS tube N2; the read high voltage VD25 is connected to the source electrode of a second PMOS tube P2, the source electrode of a second NMOS tube N2 is grounded, the drain electrode of the second PMOS tube P2 is connected with the drain electrode of a second NMOS tube N2 and the source electrode of a first NMOS tube N1 to form a read voltage Vs node, the internal high voltage ZVDD is connected to the source electrode of a first PMOS tube P1, the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the first NMOS tube N1 and the transmission circuit to form a high voltage transmission control signal Vgate node.
4. A read high voltage transfer circuit as claimed in claim 3, wherein: the transmission circuit comprises an NMOS transistor N0, and the drain electrode of the first PMOS transistor P1, the drain electrode of the first NMOS transistor N1 and the gate electrode of the NMOS transistor N0 are connected to form the high-voltage transmission control signal Vgate node; the read high voltage VD25 is connected to the drain of the NMOS transistor N0, and the source of the NMOS transistor N0 is connected to the output high voltage ZDDL node.
5. The read high voltage transmission circuit of claim 4, wherein: the transmission circuit controls the transmission of high voltage of a word line during reading operation by using a high voltage transmission control signal Vgate, wherein the high voltage transmission control signal Vgate is more than or equal to VD25+ Vth during reading operation, and the Vth is the threshold value of the NMOS tube N0.
6. The read high voltage transmission circuit of claim 4, wherein: during a read operation, the read enable signal EN output by the second level shifter turns on the second NMOS transistor N2, and at the same time, the high-voltage enable signal EPEN output by the first level shifter turns on the first PMOS transistor P1, the high-voltage transmission control signal Vgate ═ ZVDD turns on the NMOS transistor N0, the internal high voltage ZVDD is greater than or equal to VD25+ Vth, where Vth is the threshold of the NMOS transistor N0.
7. The read high voltage transmission circuit of claim 4, wherein: during programming, the read permission signal output by the second level shifter turns on the second NMOS transistor N2, and simultaneously, the high voltage permission signal EPEN output by the first level shifter turns on the first NMOS transistor N1, and the high voltage transmission control signal Vgate ═ Vs ═ 0 turns off the NMOS transistor N0.
8. The read high voltage transmission circuit of claim 4, wherein: during erasing, the read enable signal EN output by the second level shifter turns on the second PMOS transistor P2, and at the same time, the high voltage enable signal EPEN output by the first level shifter turns on the first NMOS transistor N1, and the high voltage transmission control signal Vgate ═ Vs ═ VD25 turns off the NMOS transistor N0.
9. The read high voltage transmission circuit of claim 4, wherein: when erasing, the grid voltage and the drain voltage of the NMOS transistor N0 are equal to the read high voltage VD25, and the grid-induced drain leakage current of the NMOS transistor N0 is eliminated.
10. The read high voltage transmission circuit of claim 4, wherein: when the erasing operation is finished, the internal high voltage ZVDD is discharged to Vgate during the reading operation, wherein Vgate is more than or equal to VD25+ Vth, and the output high voltage ZVDDL is equal to ZVDD; when entering the standby mode, the NMOS tube N0 is conducted, the reading high voltage VD25 is limited to the voltage value Vgate-Vth due to the loss of the threshold voltage of the NMOS, the coupling effect of the output high voltage ZDDL on the reading high voltage VD25 is eliminated, and the reading high voltage VD25 is protected from being coupled to the high voltage.
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