CN108962848B - Power device and manufacturing method thereof - Google Patents
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- CN108962848B CN108962848B CN201810782322.4A CN201810782322A CN108962848B CN 108962848 B CN108962848 B CN 108962848B CN 201810782322 A CN201810782322 A CN 201810782322A CN 108962848 B CN108962848 B CN 108962848B
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- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 106
- 239000010703 silicon Substances 0.000 claims abstract description 106
- 239000002184 metal Substances 0.000 claims abstract description 54
- 230000017525 heat dissipation Effects 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 138
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000919 ceramic Substances 0.000 claims description 16
- 239000012790 adhesive layer Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000001312 dry etching Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000003749 cleanliness Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 206010063385 Intellectualisation Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000088 plastic resin Substances 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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Abstract
本发明提供了一种功率器件及其制作方法，包括：在硅片上表面形成第一沟槽，在所述硅片下表面形成第二沟槽；在所述第一沟槽内形成源极和栅极结构；在所述第二沟槽内形成背面电极；在所述硅片上表面所述第一沟槽两侧形成第三沟槽和第四沟槽，在所述硅片下表面所述第二沟槽两侧形成第五沟槽和第六沟槽；在所述第三沟槽、所述第四沟槽、所述第五沟槽和所述第六沟槽的侧壁和底面形成介质层；在所述第三沟槽、所述第四沟槽、所述第五沟槽和所述第六沟槽内形成第一金属层；在所述正面电极的上表面和所述背面电极的下表面分别形成第一防水层和第二防水层；将所述硅片上表面连接第一散热结构，将所述硅片下表面连接第二散热结构，增加功率器件的热耗散。
The present invention provides a power device and a manufacturing method thereof, comprising: forming a first trench on the upper surface of a silicon wafer, forming a second trench on the lower surface of the silicon wafer; forming a source electrode in the first trench and gate structure; forming a back electrode in the second trench; forming a third trench and a fourth trench on both sides of the first trench on the upper surface of the silicon wafer, and forming a third trench and a fourth trench on the lower surface of the silicon wafer A fifth trench and a sixth trench are formed on both sides of the second trench; the sidewalls of the third trench, the fourth trench, the fifth trench and the sixth trench are formed A dielectric layer is formed on the bottom surface of the front electrode; a first metal layer is formed in the third trench, the fourth trench, the fifth trench and the sixth trench; The lower surface of the back electrode forms a first waterproof layer and a second waterproof layer respectively; the upper surface of the silicon wafer is connected to the first heat dissipation structure, and the lower surface of the silicon wafer is connected to the second heat dissipation structure to increase the heat dissipation of the power device. dissipation.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a power device and a manufacturing method thereof.
Background
The power electronic device is developing towards modularization and intellectualization, the integration level of the power electronic device is higher and higher due to the appearance of large-scale and ultra-large-scale integrated circuits, the volume of the power electronic module is reduced due to the fact that the assembly number and the assembly density of various chips on a substrate are larger and larger, the power density is further improved, and the power module is required to have good electric performance, thermal performance and working reliability under the condition of steady state or transient state. These result in the chips being subjected to increasingly high temperatures or temperature drifts during use. High temperatures have a great influence on the reliability and rapid aging of power electronic products, and excessive temperatures and temperature cycling often directly lead to premature failure of the products. Therefore, effective thermal management becomes a major challenge for future development of power electronics, and higher demands are made on development and progress of packaging technology and packaging materials.
The cooling packaging technology commonly used at present is in the form of a double-sided cooling device, but this still does not allow efficient heat dissipation. Therefore, a heat dissipation packaging device is needed, which can greatly improve the maximum output power of the power electronic component, reduce the working temperature of the power electronic component, thereby improving the working life of the power electronic component, ensuring uniform heat dissipation of the surface of the component, and preventing the reliability of the whole device from being reduced due to overhigh working temperature.
Disclosure of Invention
The invention provides a power device and a manufacturing method thereof based on the above problems, which can improve the working reliability of the power device while increasing the heat dissipation of the power device.
In view of this, an aspect of the embodiments of the present invention provides a power device, including:
a silicon wafer;
the first groove is formed on the upper surface of the silicon chip;
the second groove is formed on the lower surface of the silicon wafer;
a source and gate structure formed within the first trench, wherein the source and gate structure comprises a front electrode;
a back electrode formed in the second trench;
the third groove and the fourth groove are formed on the upper surface of the silicon chip and on two sides of the first groove;
a fifth groove and a sixth groove formed on the lower surface of the silicon wafer and on two sides of the second groove;
the dielectric layers are formed on the side walls and the bottom surfaces of the third groove, the fourth groove, the fifth groove and the sixth groove;
a first metal layer formed in the third trench, the fourth trench, the fifth trench, and the sixth trench;
the first waterproof layer and the second waterproof layer are respectively formed on the upper surface of the front electrode and the lower surface of the back electrode and respectively fill the first groove and the second groove;
and the first heat dissipation structure and the second heat dissipation structure are respectively connected with the upper surface of the silicon chip and the lower surface of the silicon chip.
Furthermore, the silicon wafer structure also comprises a second metal layer formed on the upper surface of the silicon wafer and the lower surface of the silicon wafer, and the first metal layer is connected with the second metal layer.
Furthermore, the upper surface of the second metal layer on the upper surface of the silicon chip is flush with the upper surface of the first waterproof layer.
Further, the first groove is arranged opposite to the second groove.
Further, the third groove, the fourth groove, the fifth groove, and the sixth groove each include two grooves parallel to each other.
Another aspect of the embodiments of the present invention provides a method for manufacturing a power device, where the method includes:
providing a silicon wafer;
forming a first groove on the upper surface of the silicon chip, and forming a second groove on the lower surface of the silicon chip;
forming a source electrode and a grid electrode structure in the first groove, wherein the source electrode and the grid electrode structure comprise front electrodes;
forming a back electrode in the second groove;
forming a third groove and a fourth groove on the upper surface of the silicon wafer and on two sides of the first groove, and forming a fifth groove and a sixth groove on the lower surface of the silicon wafer and on two sides of the second groove;
forming dielectric layers on the side walls and the bottom surfaces of the third groove, the fourth groove, the fifth groove and the sixth groove;
forming a first metal layer in the third trench, the fourth trench, the fifth trench and the sixth trench;
forming a first waterproof layer and a second waterproof layer on the upper surface of the front electrode and the lower surface of the back electrode respectively, wherein the first waterproof layer and the second waterproof layer fill the first groove and the second groove respectively;
and connecting the upper surface of the silicon wafer with a first heat dissipation structure, and connecting the lower surface of the silicon wafer with a second heat dissipation structure.
Further, the forming a first metal layer in the third trench, the fourth trench, the fifth trench, and the sixth trench specifically includes:
forming a first metal layer in the third trench, the fourth trench, the fifth trench and the sixth trench;
and forming second metal layers on the upper surface of the silicon chip and the lower surface of the silicon chip, and connecting the first metal layer with the second metal layer.
Further, a first waterproof layer and a second waterproof layer are respectively formed on the upper surface of the front electrode and the lower surface of the back electrode, and the first groove and the second groove are respectively filled with the first waterproof layer and the second waterproof layer, which specifically includes:
and leveling the upper surface of the second metal layer on the upper surface of the silicon chip with the upper surface of the first waterproof layer.
Further, the first groove is arranged opposite to the second groove.
Further, the third groove, the fourth groove, the fifth groove, and the sixth groove each include two grooves parallel to each other.
The technical scheme provided by the embodiment of the invention starts from the structure of the power device, and the structure is connected with the double-sided substrate of the chip by adding the heat dissipation structure in the chip, so that the heat dissipation of the chip of the power device is greatly increased, and the working reliability is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a power device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a power device provided by an embodiment of the invention;
fig. 3 to fig. 7 are schematic structural diagrams illustrating steps of a method for manufacturing a power device according to an embodiment of the present invention;
in the figure: 1. a silicon wafer; 2. a first trench; 3. a second trench; 4. a source and gate structure; 41. a front electrode; 5. a back electrode; 6. a third trench; 61. a third second trench; 7. a fourth trench; 71. a fourth trench; 72. a fourth second trench; 8. a fifth trench; 81. a fifth trench; 82. a fifth second trench; 9. a sixth trench; 91. a sixth trench; 92. a sixth second trench; 10. a dielectric layer; 11. a first metal layer; 12. a second metal layer; 13. a first waterproof layer; 14. a second waterproof layer; 15. a first heat dissipation structure; 151. a first heat sink; 152. a first copper-clad ceramic substrate; 16. a second heat dissipation structure; 161. a second heat sink; 162. and a second copper-clad ceramic substrate.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing methods and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The following describes a method for manufacturing a power device according to an embodiment of the present invention in detail with reference to the accompanying drawings.
A power device and a method for manufacturing the same according to an embodiment of the present invention are described in detail below with reference to fig. 1 to 7.
An embodiment of the present invention provides a method for manufacturing a power device, as shown in fig. 1 and fig. 2, the method for manufacturing the power device includes:
step S01: providing a silicon wafer 1, forming a first groove 2 on the upper surface of the silicon wafer 1, and forming a second groove 3 on the lower surface of the silicon wafer 1;
step S02: forming a source and gate structure 4 in the first trench 2, wherein the source and gate structure 4 comprises a front electrode 41, and a back electrode 5 is formed in the second trench 3;
step S03: forming a third groove 6 and a fourth groove 7 on the upper surface of the silicon chip 1 and on two sides of the first groove 2, and forming a fifth groove 8 and a sixth groove 9 on the lower surface of the silicon chip 1 and on two sides of the second groove 3;
step S04: forming dielectric layers 10 on the side walls and the bottom surfaces of the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9;
step S05: forming a first metal layer 11 in the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9;
step S06: forming a first waterproof layer 13 and a second waterproof layer 14 on the upper surface of the front electrode 41 and the lower surface of the back electrode 5, respectively, wherein the first waterproof layer 13 and the second waterproof layer 14 fill the first groove 2 and the second groove 3, respectively;
step S07: and connecting the upper surface of the silicon chip 1 with a first heat dissipation structure 15, and connecting the lower surface of the silicon chip 1 with a second heat dissipation structure 16.
Referring to fig. 3, step S01 is executed to specifically: providing a silicon wafer 1, forming a first groove 2 on the upper surface of the silicon wafer 1, and forming a second groove 3 on the lower surface of the silicon wafer 1. It should be noted that the silicon wafer 1 is a carrier in an integrated circuit, the silicon wafer 1 plays a role of supporting, and the silicon wafer 1 may also participate in the operation of the integrated circuit. Preferably, the silicon wafer 1 is a monocrystalline silicon wafer, because the monocrystalline silicon material has the characteristics of low cost, large size and conductivity, the edge effect is avoided, and the yield can be greatly improved. A first trench 2 is formed in the upper surface of the silicon wafer 1. The first groove 2 is formed by etching the upper surface of the silicon wafer 1, wherein the etching method comprises dry etching and wet etching, preferably, the used etching method is dry etching, the dry etching comprises light volatilization, gas phase etching, plasma etching and the like, the dry etching is easy to realize automation, no pollution is introduced in the processing process, and the cleanliness is high. In some embodiments of the present invention, the dry etching is specifically that a mask material is prepared on the upper surface of the silicon wafer 1, the mask material is specifically a photoresist, the photoresist forms a photoresist layer on the upper surface of the silicon wafer 1, and the first photoresist layer is removed by etching the first trench 2 formed on the upper surface of the silicon wafer 1 on the photoresist layer. The second trench 3 has the same structure and function as the first trench 2, so the first trench 2 is substantially the same as the second trench 3, and therefore, the method for forming the second trench 3 is also the same as the method for forming the first trench 2, and is also preferably dry etching, and since the above has been described in detail, the method for forming the second trench 3 is not described herein again.
Referring to fig. 4, step S02 is executed to specifically: source and gate structures 4 are formed within the first trenches 2, wherein the source and gate structures 4 comprise front electrodes 41 and back electrodes 5 are formed within the second trenches 3. In some embodiments of the present invention, source and gate structures 4 are formed at the bottom surface of the first trench 2. The source and gate structure 4 includes a source electrode and a gate electrode, which constitute the front surface electrode 41. In some embodiments of the present invention, the formed source and gate structures 4 may be formed at the bottom surface of the first trench 2 by conventional processes. There are many source and Gate structures 4 suitable for the technical solution of the embodiment of the present invention, for example, the power device structure may be a source and Gate structure in a VDMOS (vertical double-Diffused MOSFET, i.e., a vertical double-Diffused Metal Oxide Semiconductor field effect Transistor), a source and Gate structure in an LDMOS (Laterally Diffused Metal Oxide Semiconductor), or a source and Gate structure in an IGBT (Insulated Gate Bipolar Transistor), but is not limited to the above power device structures.
In some embodiments of the present invention, the lower surface of the silicon wafer 1 is covered with a metal material, so that the lower surface of the silicon wafer 1 is metallized to form a back metal layer, which forms the back electrode 5.
Referring to fig. 5, step S03 is executed to specifically: and forming a third groove 6 and a fourth groove 7 on the upper surface of the silicon chip 1 and on two sides of the first groove 2, and forming a fifth groove 8 and a sixth groove 9 on the lower surface of the silicon chip 1 and on two sides of the second groove 3. The third groove 6 and the fourth groove 7 are formed by etching the upper surface of the silicon wafer 1, and the fifth groove 8 and the sixth groove 9 are formed by etching the lower surface of the silicon wafer 1, wherein the etching method comprises dry etching and wet etching, preferably, the used etching method is dry etching, the dry etching comprises light volatilization, gas phase corrosion, plasma corrosion and the like, and the dry etching is easy to realize automation, no pollution is introduced in the processing process, and the cleanliness is high. In some embodiments of the present invention, the dry etching is specifically that a mask material is prepared on the upper surface of the silicon wafer 1, the mask material is specifically a photoresist, the photoresist forms a second photoresist layer on the upper surface of the silicon wafer 1, the third trench 6 and the fourth trench 7 extending from the upper surface of the silicon wafer 1 into the silicon wafer 1 are formed on the second photoresist layer by etching, and the second photoresist layer is removed; similarly, a mask material is prepared on the lower surface of the silicon wafer 1, the mask material is specifically photoresist, the photoresist forms a third photoresist layer on the lower surface of the silicon wafer 1, the third photoresist layer is etched to form a fifth groove 8 and a sixth groove 9 which extend from the lower surface of the silicon wafer 1 into the silicon wafer 1, and the third photoresist layer is removed. Preferably, the depth of the third trench 6 and the fourth trench 7 is greater than the depth of the first trench 2, and the depth of the fifth trench 8 and the sixth trench 9 is greater than the depth of the second trench 3, that is, the third trench 6 and the fourth trench 7 are deep trenches with respect to the first trench 2, and the fifth trench 8 and the sixth trench 9 are deep trenches with respect to the second trench 3, so that the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 are as deep as possible into the silicon wafer 1, thereby increasing the contact area with the silicon wafer 1 to the greatest extent and dissipating more heat generated or conducted in the silicon wafer 1 to the outside of the silicon wafer 1.
Referring to fig. 5, step S04 is executed to specifically: and forming a dielectric layer 10 on the side walls and the bottom surfaces of the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9. The dielectric layer 10 is made of silicon oxide, silicon nitride or silicon oxynitride, and the dielectric layer 10 may be formed by sputtering, thermal oxidation or chemical vapor deposition. Preferably, the dielectric layer 10 is a silicon oxide layer formed by thermal oxidation, and in the subsequent doping step, the silicon oxide layer serves as a protective layer and will serve as an interlayer insulating layer of the final device. In addition, the dielectric layer 10 is provided with a certain thickness, so that the dielectric layer 10 plays a role in isolating current and insulating.
Referring to fig. 5, step S05 is executed, specifically: a first metal layer 11 is formed in the third trench 6, the fourth trench 7, the fifth trench 8, and the sixth trench 9. In some embodiments of the present invention, since the sidewalls and the bottom surfaces of the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 are all formed with a dielectric layer 10, the first metal layer 11 is formed in the dielectric layer 10, and the first metal layer 11 fills the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9.
Further, the forming of the first metal layer 11 in the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 specifically includes: forming a first metal layer 11 in the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9; and forming a second metal layer 12 on the upper surface of the silicon wafer 1 and the lower surface of the silicon wafer 1, and connecting the first metal layer 11 with the second metal layer 12. In some embodiments of the present invention, the upper surface and the lower surface of the silicon wafer 1 except for the first trench 2 and the second trench 3 are covered with a layer of metal to form a second metal layer 12, and it should be noted that the first metal layer 11 is communicated with the second metal layer 12, so that the first metal layer 11 is in contact with and connected to the second metal layer 12, and thus heat generated or conducted in the silicon wafer 1 is dissipated to the outside of the silicon wafer 1.
Referring to fig. 6, step S06 is executed, specifically: a first waterproof layer 13 and a second waterproof layer 14 are respectively formed on the upper surface of the front electrode 41 and the lower surface of the back electrode 5, and the first waterproof layer 13 and the second waterproof layer 14 respectively fill the first groove 2 and the second groove 3. In some embodiments of the present invention, the first waterproof layer 13 and the second waterproof layer 14 are both waterproof layers, and it should be noted that the waterproof layers are made of plastic resin materials, and the waterproof layers are used for encapsulating the source and gate structures 4 and the drain structures formed by the back electrodes 5. The waterproof layer enables the silicon wafer 1 and the formed source electrode, grid electrode and drain electrode structures to be waterproof and anti-pollution, so that the whole device structure is passivated, and the reliability of a power device is improved.
In some embodiments of the present invention, the front electrode 41 and the back electrode 5 are covered with a waterproof layer, and most of the waterproof layer is not removed, in order to form a through hole in the waterproof layer formed on the front electrode 41 and the back electrode 5 and to lead out a connection line.
Referring to fig. 7, step S07 is executed to specifically: and connecting the upper surface of the silicon chip 1 with a first heat dissipation structure 15, and connecting the lower surface of the silicon chip 1 with a second heat dissipation structure 16. In some embodiments of the present invention, the first heat dissipation structure 15 includes a first heat dissipation fin 151 and a first copper-clad ceramic substrate 152, and the second heat dissipation structure 16 includes a second heat dissipation fin 161 and a second copper-clad ceramic substrate 162, wherein the first heat dissipation fin 151 is connected to the first copper-clad ceramic substrate 152 through a first adhesive layer (not shown), and the first copper-clad ceramic substrate 152 is connected to the second metal layer 12 and the first waterproof layer 13 on the upper surface of the silicon wafer 1 through a second adhesive layer (not shown). Correspondingly, the second heat sink 161 is connected to the second copper-clad ceramic substrate 162 through a third adhesive layer (not shown), and the second copper-clad ceramic substrate 162 is connected to the second metal layer 12 and the second waterproof layer on the lower surface of the silicon wafer 1 through the fourth adhesive layer (not shown).
Further, the forming a first waterproof layer 13 and a second waterproof layer 14 on the upper surface of the front electrode 41 and the lower surface of the back electrode 5, respectively, and the filling of the first trench 2 and the second trench 3 with the first waterproof layer 13 and the second waterproof layer 14 includes: and leveling the upper surface of the second metal layer 12 on the upper surface of the silicon wafer 1 with the upper surface of the first waterproof layer 13. In some embodiments of the present invention, since the first waterproof layer 13 and the second waterproof layer 14 completely encapsulate the source and gate structures 4 and the drain structures, no gap is left between the second metal layer 12 and the first waterproof layer 13 on the upper surface of the silicon wafer 1 and the connected and second adhesive layer, and no gap is left between the second metal layer 12 and the second waterproof layer 14 on the lower surface of the silicon wafer 1 and the connected and fourth adhesive layer.
Further, the first groove 2 is disposed opposite to the second groove 3. In some embodiments of the present invention, the first trench 2 is disposed opposite to the second trench 3, and particularly, the first trench 2 and the second trench 3 are symmetrically disposed. When the first trench 2 and the second trench 3 are oppositely arranged, the power devices formed in the first trench 2 and the second trench 3 have good structures and excellent performance.
As shown in fig. 2, an embodiment of the present invention provides a power device, including:
a silicon wafer 1;
a first trench 2 formed on the upper surface of the silicon wafer 1;
a second trench 3 formed in the lower surface of the silicon wafer 1;
a source and gate structure 4 formed within the first trench 2, wherein the source and gate structure 4 comprises a front electrode 41;
a back electrode 5 formed in the second trench 3;
a third groove 6 and a fourth groove 7 formed on the upper surface of the silicon chip 1 and on two sides of the first groove 2;
a fifth groove 8 and a sixth groove 9 formed on both sides of the second groove 3 on the lower surface of the silicon wafer 1;
a dielectric layer 10 formed on the sidewalls and the bottom surfaces of the third trench 6, the fourth trench 7, the fifth trench 8, and the sixth trench 9;
a first metal layer 11 formed in the third trench 6, the fourth trench 7, the fifth trench 8, and the sixth trench 9;
a first waterproof layer 13 and a second waterproof layer 14 respectively formed on the upper surface of the front electrode 41 and the lower surface of the back electrode 5 and respectively filling the first trench 2 and the second trench 3;
and the first heat dissipation structure 15 and the second heat dissipation structure 16 are respectively connected with the upper surface of the silicon chip 1 and the lower surface of the silicon chip 1.
Alternatively, regarding the shapes of the first trench 2 and the second trench 3, the shapes of the first sub-trench and the second sub-trench may be rectangular trenches or square trenches, and those skilled in the art may select trenches with different shapes according to the electrical performance of the device.
The openings of the third trench 6 and the fourth trench 7 face the upper surface of the silicon wafer 1, and correspondingly, the bottom surfaces of the third trench 6 and the fourth trench 7 are located below the openings of the third trench 6 and the fourth trench 7. The openings of the fifth trench 8 and the sixth trench 9 face the lower surface of the silicon wafer 1, and correspondingly, the bottom surfaces of the fifth trench 8 and the sixth trench 9 are located above the openings of the third trench 6 and the fourth trench 7.
Further, in some embodiments of the present invention, as shown in fig. 5, 6 and 7, the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 each include two trenches parallel to each other. In some embodiments of the present invention, the third trench 6 and the fourth trench 7 may be disposed in parallel or not, and correspondingly, the fifth trench 8 and the sixth trench 9 may be disposed in parallel or not, and preferably, the third trench 6 and the fourth trench 7 are disposed in parallel, the fifth trench 8 and the sixth trench 9 are disposed in parallel, and the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 each include two trenches parallel to each other, so that the formed power device structure is symmetrical, and heat dissipation is more uniform.
In some embodiments of the present invention, each of the third groove 6, the fourth groove 7, the fifth groove 8 and the sixth groove 9 includes two grooves parallel to each other, specifically, the third groove 61 and the third second groove 62 are parallel to each other, the fourth groove 71 and the fourth second groove 72 are parallel to each other, the fifth groove 81 and the fifth second groove 82 are parallel to each other, and the sixth groove 91 and the sixth groove 92 are parallel to each other.
In some embodiments of the present invention, two sides of the first trench 2 may be respectively a single trench, two trenches, or even three or more trenches, and a person skilled in the art may determine the number of trenches respectively formed on two sides of the first trench 2 according to actual situations. The number of the trenches formed on both sides of the second trench 3 may refer to the number of the trenches formed on both sides of the first trench 2, and will not be described herein again. Preferably, the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 each comprise two trenches parallel to each other, and considering that the silicon wafer 1 needs to dissipate heat as much as possible, and the best material for dissipating heat is a metal material, in the preferred embodiment of the present invention, the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 are filled with a metal layer, and the metal layer is mainly used for dissipating heat. However, considering the chip requirement that the silicon chip 1 has the lowest possible weight and the highest possible degree of integration, it is not desirable to integrate too many metal layers into the chip so as not to cause the chip to have too high weight. Therefore, in a preferred embodiment of the present invention, the third trench 6, the fourth trench 7, the fifth trench 8 and the sixth trench 9 each comprise two trenches parallel to each other.
The technical scheme of the invention is described in detail with reference to the drawings, and the invention starts from the structure of the power device, and adds the heat dissipation structure comprising the dielectric layer 10, the first metal layer 11 and the second metal layer 12 in the silicon chip 1, and the heat dissipation structure is connected with the first heat dissipation fin 151, the second heat dissipation fin 161, the first copper-clad ceramic substrate 152 and the second copper-clad ceramic substrate 162, so that heat is dissipated through the structure, the heat dissipation of the power device chip is greatly increased, and the working reliability is improved. In addition, the heat dissipation structure is distributed in the chip isolation and scribing way area, and the chip area does not need to be increased. The power device manufactured by the invention has simple manufacturing process, and the heat dissipation structure can be simultaneously formed in the conventional manufacturing process of the chip, so that the manufacturing cost is reduced. After the heat dissipation structure is added, the heat dissipation fins are connected with the inside of the chip through metal, so that the heat dissipation speed of the chip is greatly improved, the thermal resistance is reduced, and the reliability of the product is improved. It should be noted that the formed chip structure region is located in the deep trench formed by the silicon wafer 1, and the packaging resin can be directly filled after the chip structure is formed, which is suitable for wafer level packaging.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
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| JP2006303145A (en) * | 2005-04-20 | 2006-11-02 | Toyota Motor Corp | Semiconductor device |
| CN103117309A (en) * | 2013-02-22 | 2013-05-22 | 南京邮电大学 | Horizontal power device structure and preparation method thereof |
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| CN204885170U (en) * | 2015-08-21 | 2015-12-16 | 中国东方电气集团有限公司 | Field is by current control type power device with adaptive |
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| KR20150076715A (en) * | 2013-12-27 | 2015-07-07 | 삼성전기주식회사 | Power Semiconductor device |
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| JPH065620A (en) * | 1992-06-22 | 1994-01-14 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2006303145A (en) * | 2005-04-20 | 2006-11-02 | Toyota Motor Corp | Semiconductor device |
| CN103117309A (en) * | 2013-02-22 | 2013-05-22 | 南京邮电大学 | Horizontal power device structure and preparation method thereof |
| CN103811336A (en) * | 2014-02-21 | 2014-05-21 | 成都方舟微电子有限公司 | IGBT (Insulated Gate Bipolar Translator) power device applied at low power and manufacturing method thereof |
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