CN108962839B - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN108962839B CN108962839B CN201710384186.9A CN201710384186A CN108962839B CN 108962839 B CN108962839 B CN 108962839B CN 201710384186 A CN201710384186 A CN 201710384186A CN 108962839 B CN108962839 B CN 108962839B
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- layer
- package
- patterned conductive
- core structure
- metal substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a packaging structure, which comprises a metal substrate, a core structure layer and a packaging element. The core structure layer is configured on the metal substrate and is provided with an opening and a patterned conductive layer. The packaging element is configured on the metal substrate and is positioned in the opening of the core structure layer. The packaging element comprises a plurality of outer pins, and the outer pins are electrically connected with the patterned conductive layer of the core structure layer. The outer surface of each outer pin is cut to be flush with the upper surface of the patterned conductive layer.
Description
Technical Field
The present invention relates to a package structure, and more particularly, to a package structure with a buried package element.
Background
When considering the overall thickness of the electronic device or the package structure, the packaging method of the embedded device needs to be discussed. By embedding the elements, the packaging volume can be greatly reduced, and more high-functionality elements can be put in, so that the layout area of the surface of the substrate is increased, and the aim of thinning the electronic product is fulfilled. Generally, in the conventional package technology using the embedded device, a receiving groove is formed on the substrate to dispose the device in the receiving groove of the substrate. And then, filling the insulating colloid so as to embed the element in the substrate. However, the embedded device often faces the problem of poor heat dissipation, which affects the heat dissipation performance of the electronic device or the whole package structure.
Disclosure of Invention
The invention provides a packaging structure, which can embed a packaging element and has the effect of reducing the packaging height.
The invention provides a packaging structure, which comprises a metal substrate, a core structure layer and a packaging element. The core structure layer is configured on the metal substrate and is provided with an opening and a patterned conductive layer, and the packaging element is configured on the metal substrate and is positioned in the opening of the core structure layer. The package element comprises a plurality of outer pins, the outer pins are electrically connected with the patterned conductive layer of the core structure layer, and the outer surface of each outer pin is aligned with the upper surface of the patterned conductive layer.
In an embodiment of the invention, the metal substrate has a configuration surface and a groove, the core structure layer is disposed on the configuration surface, the package element is disposed in the groove, and the configuration surface and a bottom surface of the groove have a height difference.
In an embodiment of the invention, a bottom surface of the groove is a rough surface.
In an embodiment of the invention, the metal substrate has a disposition surface, and the core structure layer and the package element are disposed on the disposition surface.
In an embodiment of the invention, the core structure layer includes a dielectric layer, and the dielectric layer is located between the patterned conductive layer and the metal substrate.
In an embodiment of the invention, the package device further includes a chip and a package encapsulant. The chip is provided with a plurality of connecting pads. The encapsulant encapsulates the chip and exposes a surface of each of the pads, wherein the outer leads are disposed on the encapsulant and connected to the surface of each of the pads respectively.
In an embodiment of the invention, the package element further includes a chip pad, a chip, a molding compound, and a plurality of wires. The chip is configured on the chip seat. The packaging colloid coats the chip and the chip seat, wherein the outer pin is arranged on the packaging colloid, and the lead is electrically connected between the chip and the outer pin.
In an embodiment of the invention, the outer leads are electrically connected to the patterned conductive layer of the core structure layer through a plurality of wires.
In an embodiment of the invention, the outer lead is structurally and electrically connected to the patterned conductive layer of the core structure layer.
In an embodiment of the invention, the package structure further includes an insulating layer filled between the package element and the opening of the core structure layer.
In an embodiment of the invention, the package structure further includes an adhesive layer disposed between the core structure layer and the metal substrate.
In an embodiment of the invention, the package structure further includes a thermal adhesive layer disposed between the package element and the metal substrate.
In an embodiment of the invention, the package structure further includes a surface treatment layer disposed on the upper surface of the patterned conductive layer and the outer surface of each of the outer leads.
In an embodiment of the invention, the package structure further includes a solder mask layer disposed on the core structure layer and at least covering the patterned conductive layer and the outer leads of the package element.
In an embodiment of the invention, the package structure further includes an electronic component and a plurality of conductive vias. The electronic element is arranged on the solder mask layer. The conductive through holes penetrate through the solder mask layer and expose part of the patterned conductive layer, wherein the electronic element is electrically connected with the patterned conductive layer through the plurality of conductive through holes.
In an embodiment of the invention, the package structure further includes a solder mask layer and a surface treatment layer. The solder mask layer is arranged on the core structure layer and covers the patterned conductive layer, wherein the solder mask layer exposes a part of the upper surface of the patterned conductive layer. The surface treatment layer is configured on the upper surface of the patterned conductive layer exposed by the solder mask layer and the outer surface of each outer pin.
In view of the above, in the configuration of the package structure of the present invention, the package element is disposed on the metal substrate and located in the opening of the core structure layer. Therefore, the packaging element is embedded into the core structure layer, and the outer pin of the packaging element and the patterned conductive layer of the core structure layer are coplanar, so that the overall packaging height of the packaging structure can be reduced. In addition, the packaging element is arranged on the metal substrate, and the heat dissipation efficiency of the packaging element can be improved through the heat conduction property of the metal substrate.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
FIG. 3 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
FIG. 4 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
FIG. 5 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
FIG. 6 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
FIG. 7 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention;
fig. 8 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention.
Description of reference numerals:
100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H: packaging structure
110. 110c, 110 d: metal substrate
112: arrangement surface
114c, 114 d: groove
115c, 115 d: bottom surface
120: core structure layer
122: opening of the container
124: patterned conductive layer
126: dielectric layer
130. 230: package component
231: chip holder
132. 232: outer pin
134. 234: chip and method for manufacturing the same
1342: connecting pad
136. 236: packaging colloid
238: conducting wire
140: insulating layer
150: adhesive layer
160: heat-conducting adhesive layer
170. 170': surface treatment layer
180. 180': welding-proof layer
190: electronic component
190A: conductive vias
W: conducting wire
H: height difference
S1, S1': outer surface
S2: upper surface of
S3: surface of
G: air gap
Detailed Description
Fig. 1 is a schematic cross-sectional view illustrating a package structure according to an embodiment of the invention. Referring to fig. 1, a package structure 100A of the present embodiment includes a metal substrate 110, a core structure layer 120, and a package element 130. The core structure layer 120 is disposed on the metal substrate 110 and has an opening 122 and a patterned conductive layer 124. The package element 130 is disposed on the metal substrate 110 and located in the opening 122 of the core structure layer 110. The package device 130 includes a plurality of outer leads 132, and each outer lead 132 is electrically connected to the patterned conductive layer 124 of the core structure layer 120. Specifically, the outer surface S1 of each outer lead 132 is aligned with the upper surface S2 of the patterned conductive layer 124.
In detail, the metal substrate 110 of the present embodiment has a configuration surface 112, and the core structure layer 120 and the package element 130 are respectively disposed on the configuration surface 112. The package element 130 and the core structure layer 120 have an air gap G therebetween, that is, the package element 130 does not contact the inner wall of the opening 122 of the core structure layer 120. The core structure layer 120 further includes a dielectric layer 126, wherein the dielectric layer 126 is located between the patterned conductive layer 124 and the metal substrate 110. The package device 130 further includes a chip 134 and an encapsulant 136, wherein the chip 134 has a plurality of pads 1342, and the encapsulant 136 encapsulates the chip 134 and exposes a surface S3 of each pad 1342. Each of the outer leads 132 is disposed on the encapsulant 136 and is structurally and electrically connected to the surface S3 of each of the pads 1342, so that the chip 134 can be electrically connected to the patterned conductive layer 124 of the core structure layer 120 through the outer leads 132. As shown in fig. 1, the package device 130 of the present embodiment is embodied as a flip-chip type package device, and the outer leads 132 of the package device 130 are structurally and electrically connected to the patterned conductive layer 124 of the core structure layer 120.
Referring to fig. 1 again, in order to further fix the position of the package element 130, the package structure 100A of the present embodiment may include an insulating layer 140, wherein the insulating layer 140 is filled in the air gap G between the package element 130 and the opening 122 of the core structure layer 120, so as to position the package element 130 in the opening 122. Furthermore, the package structure 100A of the present embodiment may further include an adhesive layer 150, wherein the adhesive layer 150 is disposed between the core structure layer 120 and the metal substrate 110, and the core structure layer 120 is adhered and fixed on the metal substrate 110 through the adhesive layer 150. In addition, in order to increase the heat dissipation effect of the package element 130, the package structure 100A of the embodiment also includes a thermal conductive adhesive layer 160, wherein the thermal conductive adhesive layer 160 is disposed between the package element 130 and the metal substrate 110, the package element 130 can be adhered and fixed on the metal substrate 110 through the thermal conductive adhesive layer 160, and the package element 130 can rapidly transmit the generated heat to the outside through the thermal conductive adhesive layer 160 and the metal substrate 110 in sequence.
In short, in the configuration of the package structure 100A of the present embodiment, the package element 130 is disposed on the metal substrate 110 and located in the opening 122 of the core structure layer 120. In this way, the package element 130 is embedded in the core structure layer 120, and the outer leads 132 of the package element 130 are coplanar with the patterned conductive layer 124 of the core structure layer 120, so that the overall package height of the package structure 100A can be reduced. In addition, the package element 130 is disposed on the metal substrate 110, and the heat dissipation efficiency of the package element 130 can be improved by the heat conduction property of the metal substrate 110.
It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 2 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 1 and fig. 2, a package structure 100B of the present embodiment is similar to the package structure 100A of fig. 1, and the difference between the two structures is: the package device 230 of the present embodiment is embodied as a wire-bonding type package device. In detail, the package element 230 of the present embodiment includes a die pad 231, an outer lead 232, a die 234, a molding compound 236 and a plurality of wires 238. The chip 234 is disposed on the die pad 231, the wires 238 are electrically connected between the chip 234 and the outer leads 232, and the encapsulant 236 covers the chip 234, the die pad 231 and the wires 238 and fills the space between the outer leads 232. The outer leads 232 are disposed on the encapsulant 236, and the outer surface S1' of each outer lead 232 is aligned with the upper surface S2 of the patterned conductive layer 124.
Fig. 3 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 1 and fig. 3, a package structure 100C of the present embodiment is similar to the package structure 100A of fig. 1, and the difference between the two structures is: the metal substrate 110c of the present embodiment further has a groove 114c, wherein the package element 130 is disposed in the groove 114c, and the disposition surface 112 and the bottom surface 115c of the groove 114c have a height difference H. In detail, the groove 114c of the metal substrate 110c can be used to accommodate the package element 130 with a larger thickness, so that the package element 130 can be embedded in the opening 122 of the core structure layer 120, and the outer surface S1 of the outer lead 132 is cut to be aligned with the upper surface S2 of the patterned conductive layer 124, thereby reducing the overall package height.
Fig. 4 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 3 and fig. 4, a package structure 100D of the present embodiment is similar to the package structure 100C of fig. 3, and the difference between the two structures is: the bottom surface 115d of the groove 114d of the metal substrate 110d of the embodiment is embodied as a rough surface, wherein the rough surface is, for example, a rectangular saw-tooth structure, but the invention is not limited thereto. The bottom surface 115d of the groove 114d of the metal substrate 110d of the embodiment can increase the contact area between the insulating layer 140 and the thermal conductive adhesive layer 160 and the metal substrate 110d, so as to increase the bonding force between the insulating layer 140 and the metal substrate 110d, thereby increasing the bonding strength between the insulating layer 140, the thermal conductive adhesive layer 160 and the metal substrate 110 d.
Fig. 5 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 1 and fig. 5, a package structure 100E of the present embodiment is similar to the package structure 100A of fig. 1, and the difference between the two structures is: the package structure 100E of the present embodiment further includes a surface treatment layer 170 disposed on the upper surface S2 of the patterned conductive layer 124 and the outer surface S1 of the outer lead 132, wherein the surface treatment layer 170 is, for example, a nickel layer, a gold layer, a silver layer, a nickel-palladium-gold layer, or other suitable metals or alloys, so as to prevent the patterned conductive layer 124 and the outer lead 132 from being attacked by water and oxygen to generate oxidation.
Fig. 6 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 1 and fig. 6, a package structure 100F of the present embodiment is similar to the package structure 100A of fig. 1, and the difference between the two structures is: the package structure 100F of the present embodiment further includes a solder mask 180 disposed on the core structure layer 120 and at least covering the patterned conductive layer 124 and the outer leads 132 of the package element 130. In detail, in the present embodiment, the solder mask 180 covers the patterned conductive layer 124, the dielectric layer 126 exposed by the patterned conductive layer 124, and the outer leads 132 of the package element 130 and a portion of the encapsulant 136 located between the outer leads 132. The solder mask 180 can be used to prevent the patterned conductive layer 124 or the outer leads 132 from being abnormally electrically contacted, thereby causing electrical interference or short circuit.
Fig. 7 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 1 and fig. 7, a package structure 100G of the present embodiment is similar to the package structure 100A of fig. 1, and the difference between the two structures is: the package structure 100G of the present embodiment further includes a surface treatment layer 170 'and a solder mask layer 180'. The solder mask 180 'is disposed on the core structure layer 120 and covers the patterned conductive layer 124, wherein the solder mask 180' exposes a portion of the upper surface S2 of the patterned conductive layer 124. The surface treatment layer 170 'is disposed on the upper surface S2 of the patterned conductive layer 124 exposed by the solder mask 180' and the outer surface S1 of each outer lead 132, so as to prevent the patterned conductive layer 124 and the outer leads 132 from being attacked by water and oxygen to generate oxidation. Each outer lead 132 of the package device 130 is electrically connected to the patterned conductive layer 124 of the core structure layer 120 through a wire W. Furthermore, two ends of the wire W are electrically connected to the surface treatment layer 170' disposed on the patterned conductive layer 124 and the leads 132, respectively. In other words, the package element 130 of the present embodiment is electrically connected to the patterned conductive layer 124 of the core structure layer 120 by the wire W.
Fig. 8 is a schematic cross-sectional view illustrating a package structure according to another embodiment of the invention. Referring to fig. 6 and 8, the package structure 100H of the present embodiment is similar to the package structure 100F of fig. 6, and the difference between the two structures is: the package structure 100H of the present embodiment further includes an electronic element 190 and a plurality of conductive vias 190A. The electronic component 190 is disposed on the solder mask 180. The conductive via 190A penetrates through the solder mask layer 180 and exposes a portion of the patterned conductive layer 124, wherein the electronic component 190 is electrically connected to the patterned conductive layer 124 through the conductive via 190A. Here, the electronic component 190 is, for example, a sensor, a transmitter, a receiver, or other suitable components, but is not limited thereto.
In summary, in the configuration of the package structure of the present invention, the package element is disposed on the metal substrate and located in the opening of the core structure layer. Therefore, the packaging element is embedded into the core structure layer, and the outer pin of the packaging element and the patterned conductive layer of the core structure layer are coplanar, so that the overall packaging height of the packaging structure can be reduced. In addition, the packaging element is arranged on the metal substrate, and the heat dissipation efficiency of the packaging element can be improved through the heat conduction property of the metal substrate.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
1. A package structure, comprising:
a metal substrate;
the core structure layer is configured on the metal substrate and is provided with an opening and a patterned conductive layer;
a package element disposed on the metal substrate and located in the opening of the core structure layer, wherein the package element includes:
a chip;
the outer pins are electrically connected with the patterned conductive layer of the core structure layer, and the outer surface of each outer pin is cut to be flush with the upper surface of the patterned conductive layer; and
the packaging colloid wraps the chip, wherein the outer pins are arranged on the packaging colloid, and a gap is formed between the packaging colloid and the core structure layer; and
and the insulating layer is filled in the gap between the packaging element and the core structure layer.
2. The package structure of claim 1, wherein the metal substrate has a disposition surface and a recess, the core structure layer is disposed on the disposition surface, the package element is disposed in the recess, and the disposition surface and a bottom surface of the recess have a height difference.
3. The package structure of claim 2, wherein the bottom surface of the recess is a rough surface.
4. The package structure of claim 1, wherein the metal substrate has a disposition surface, and the core structure layer and the package element are disposed on the disposition surface.
5. The package structure of claim 1, wherein the core structure layer comprises a dielectric layer between the patterned conductive layer and the metal substrate.
6. The package structure of claim 1, wherein the chip has a plurality of pads, the encapsulant encapsulates the chip and exposes a surface of each of the pads, and the outer leads are respectively connected to the surface of each of the pads.
7. The package structure of claim 1, wherein the package element further comprises:
the chip is configured on the chip seat, and the packaging colloid coats the chip and the chip seat; and
and the leads are electrically connected between the chip and the outer pins.
8. The package structure of claim 1, wherein the outer leads of the package component are electrically connected to the patterned conductive layer of the core structure layer by wires.
9. The package structure of claim 1, wherein the plurality of outer leads of the package element are structurally and electrically connected to the patterned conductive layer of the core structure layer.
10. The package structure of claim 1, further comprising:
and the adhesion layer is arranged between the core structure layer and the metal substrate.
11. The package structure of claim 1, further comprising:
and the heat-conducting adhesive layer is configured between the packaging element and the metal substrate.
12. The package structure of claim 1, further comprising:
and the surface treatment layer is configured on the upper surface of the patterned conductive layer and the outer surface of each outer pin.
13. The package structure of claim 1, further comprising:
and the solder mask is configured on the core structure layer and at least covers the patterned conductive layer and the plurality of outer pins of the packaging element.
14. The package structure of claim 13, further comprising:
the electronic element is arranged on the solder mask layer; and
and the plurality of conductive through holes penetrate through the solder mask layer and expose part of the patterned conductive layer, and the electronic element is electrically connected with the patterned conductive layer through the plurality of conductive through holes.
15. The package structure of claim 1, further comprising:
the solder mask layer is configured on the core structure layer and covers the patterned conductive layer, wherein the solder mask layer exposes part of the upper surface of the patterned conductive layer; and
and the surface treatment layer is configured on the upper surface of the patterned conducting layer exposed by the solder mask layer and the outer surface of each outer pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710384186.9A CN108962839B (en) | 2017-05-26 | 2017-05-26 | Packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710384186.9A CN108962839B (en) | 2017-05-26 | 2017-05-26 | Packaging structure |
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| Publication Number | Publication Date |
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| CN108962839A CN108962839A (en) | 2018-12-07 |
| CN108962839B true CN108962839B (en) | 2021-02-19 |
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| CN201710384186.9A Active CN108962839B (en) | 2017-05-26 | 2017-05-26 | Packaging structure |
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| US5173844A (en) * | 1987-05-19 | 1992-12-22 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit device having a metal substrate |
| CN1395461A (en) * | 2002-07-17 | 2003-02-05 | 威盛电子股份有限公司 | Integrated module board with embedded IC chip and passive element and its production method |
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| CN103000780A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | LED (Light-Emitting Diode) chip packaging structure, manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI363585B (en) * | 2008-04-02 | 2012-05-01 | Advanced Semiconductor Eng | Method for manufacturing a substrate having embedded component therein |
| JP6133549B2 (en) * | 2012-04-26 | 2017-05-24 | 新光電気工業株式会社 | Wiring board and method of manufacturing wiring board |
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2017
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5173844A (en) * | 1987-05-19 | 1992-12-22 | Mitsubishi Denki Kabushiki Kaisha | Integrated circuit device having a metal substrate |
| CN1395461A (en) * | 2002-07-17 | 2003-02-05 | 威盛电子股份有限公司 | Integrated module board with embedded IC chip and passive element and its production method |
| TW200625575A (en) * | 2005-01-12 | 2006-07-16 | Phoenix Prec Technology Corp | Superfine-circuit semiconductor package structure |
| TW200929462A (en) * | 2007-12-19 | 2009-07-01 | Raydium Semiconductor Corp | Chip, chip manufacturing method, and chip packaging structure |
| CN101937881A (en) * | 2009-06-29 | 2011-01-05 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and packaging method thereof |
| CN102610583A (en) * | 2011-01-19 | 2012-07-25 | 旭德科技股份有限公司 | Package carrier and method for manufacturing the same |
| CN103000780A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | LED (Light-Emitting Diode) chip packaging structure, manufacturing method thereof and display device |
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|---|---|
| CN108962839A (en) | 2018-12-07 |
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