CN108962756A - A kind of preparation method of VDMOS power device - Google Patents
A kind of preparation method of VDMOS power device Download PDFInfo
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- CN108962756A CN108962756A CN201810763625.1A CN201810763625A CN108962756A CN 108962756 A CN108962756 A CN 108962756A CN 201810763625 A CN201810763625 A CN 201810763625A CN 108962756 A CN108962756 A CN 108962756A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 34
- 238000002513 implantation Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 11
- 230000007797 corrosion Effects 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims description 2
- 239000002245 particle Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of preparation methods of VDMOS power device, belong to technical field of integrated circuits.The figure of light shield is formed between the channel region of device；According to the figure injecting p-type impurity of light shield, and carry out the high temperature anneal；The implantation dosage of the p type impurity is 1E15-1E16cm‑2, energy 70-120Kev.The structure of device is changed, power VDMOSFET power device body contact structure is increased, realizes that hole is shunted by effective in ionization by collision, so that reducing chip burns probability；Processing technology is simple, and controllability is strong, has very strong operability.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of preparation method of VDMOS power device.
Background technique
It is conductive that power MOSFET only has a kind of polar carrier (more sons) to participate in conducting, is unipolar transistor.
Electrical conduction mechanism is identical as small-power metal-oxide-semiconductor, but has larger difference in structure, and small-power metal-oxide-semiconductor is lateral conduction devices, power
MOSFET mostly uses greatly vertical conduction double diffusion VDMOS(Vertical Double-diffused Metal Oxide
Semiconductor) structure substantially increases pressure resistance and the withstanding current capability of MOSFET element.Power MOSFET is polynary collection
At structure, hexagonal cells, square shaped cells, rectangular element are arranged by triangle disposition.Such device is with its unique high input
The advantages that impedance, low driving power, high switching speed, superior frequency and breakdown characteristics, thermal stability and negative temperature characteristic,
It is widely used in power supply conversion, automotive electronics, motor driving, motor control, audio amplification, high frequency oscillator, uninterrupted electricity
The various power electronic systems such as source, energy-saving lamp, inverter.
Single particle radiation effect can cause device to damage firmly, or even will cause device permanent failure.When single-particle enters
The parasitic transistor that may cause device in the source electrode active area of VDMOS device is penetrated (by source electrode active area, p-body
Area, epitaxial layer are formed) it opens, so that VDMOS device is lost grid switching function, be further likely to form positive feedback, leads to device
It burns, referred to as single event burnout (SEB) phenomenon.
Due to typically now all doing VDMOS power device, media base layer such as silicon, silicon compound etc. using silica-base material
Material can generate single event burnout effect under radiation environment, when in entire integrated circuit use a large amount of VDMOS power
Device is driven, is switched, and jumbo decline is unable to satisfy the requirement of circuit application high reliability by reliability.
Summary of the invention
The purpose of the present invention is to provide a kind of preparation methods of VDMOS power device, to solve existing VDMOS power
The problem of device is easy to produce single event burnout phenomenon under radiation environment, is unable to satisfy circuit application.
In order to solve the above technical problems, the present invention provides a kind of preparation method of VDMOS power device, comprising:
The figure of light shield is formed between the channel region of device；
According to the figure injecting p-type impurity of light shield, and carry out the high temperature anneal；The implantation dosage of the p type impurity is 1E15-
1E16cm-2, energy 70-120Kev.
Optionally, before forming the figure of light shield between the channel region in device, the preparation of the VDMOS power device
Method further include:
Silicon substrate is provided, grows silicon epitaxial layers on the silicon substrate；
According to the figure of p-well light shield, the figure of p-well needed for being formed；
According to p-well light mask image injecting p-type impurity, dosage is 5E12 ~ 5E13cm-2, energy 50-80Kev, and carry out high temperature
Annealing forms p-well；
According to the figure of N+/P+ light shield, it is respectively formed the figure of source and body contact；
According to the figure injecting p-type impurity of P+ light shield, and carries out the high temperature anneal and form P+ body contact jaw；According to N+ light shield
Figure injects N-type impurity, and carries out the high temperature anneal and form N+ source.
Optionally, the implantation dosage for being used to form the p type impurity of P+ body contact jaw is 5E14 ~ 5E15cm-2, energy 50-
100Kev；The implantation dosage for being used to form the N-type impurity of N+ source is 5E14 ~ 1E16cm-2, energy 50-80Kev.
Optionally, after carrying out the high temperature anneal, the preparation method of the VDMOS power device further include:
Carry out the deposit of grid oxygen SiO2 growth and polysilicon；
Photoetching and corrosion are carried out to grid oxygen SiO2 and polysilicon, form polysilicon gate control terminal；
Dielectric layer deposition, contact hole photoetching and corrosion are carried out, then carries out Metal deposition and lithography corrosion process, metal is formed and connects
Line；
In surface passivation protective layer, complete VDMOS power device is formed.
Optionally, the resistivity of the silicon substrate is 0.002 ~ 0.004 Ω cm.
Optionally, the resistivity of the silicon epitaxial layers is 3 ~ 24 Ω cm, with a thickness of 3um ~ 50um.
Optionally, the type of the p type impurity includes B and BF2.
Optionally, the type of the N-type impurity includes P, As and In.
The present invention also provides a kind of VDMOS power devices that the preparation method according to above-mentioned VDMOS power device is prepared
Part.
A kind of preparation method of VDMOS power device is provided in the present invention, is formed between the channel region of device
The figure of light shield；According to the figure injecting p-type impurity of light shield, and carry out the high temperature anneal；The implantation dosage of the p type impurity
For 1E15-1E16cm-2, energy 70-120Kev.The structure of device is changed, power VDMOSFET power device body contact knot is increased
Structure realizes that hole is shunted by effective in ionization by collision, so that reducing chip burns probability；Processing technology is simple,
Controllability is strong, has very strong operability.
Detailed description of the invention
Fig. 1 is the flow diagram of the preparation method of VDMOS power device provided by the invention；
Fig. 2 ~ Figure 11 is each step schematic diagram of the preparation method of VDMOS power device.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of preparation method of VDMOS power device proposed by the present invention make into
One step is described in detail.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that
Attached drawing is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly aid illustration is of the invention
The purpose of embodiment.
Embodiment one
The present invention provides a kind of preparation method of VDMOS power device, flow diagram is as shown in Figure 1.The VDMOS function
The preparation method of rate device includes:
Step S11, the figure of light shield is formed between the channel region of device；
Step S12, according to the figure injecting p-type impurity of light shield, and the high temperature anneal is carried out；The injectant of the p type impurity
Amount is 1E15-1E16cm-2, energy 70-120Kev.
Specifically, the resistivity of the silicon substrate 1 is 0.002 ~ 0.004 Ω first as shown in Fig. 2, providing silicon substrate 1
cm；And silicon epitaxial layers 2 are grown on the silicon substrate 1, the resistivity of the silicon epitaxial layers 2 is 3 ~ 24 Ω cm, with a thickness of
3um~50um；Then, according to the figure 3 of p-well light shield, the figure of required p-well is formed, as shown in Figure 3；According to the figure of p-well light shield
3 injecting p-type impurity of shape, dosage are 5E12 ~ 5E13cm-2, energy 50-80Kev, and carry out the high temperature anneal and form such as Fig. 4
Shown in p-well；The type of the p type impurity includes B and BF2；Referring to Fig. 5, the figure 4(according to N+/P+ light shield includes Fig. 5
Middle dotted line frame inner part and its two sides dash area), it is respectively formed the figure of source and body contact；According still further to P+ light shield (in Fig. 5
Dotted line frame inner part) figure injecting p-type impurity, and carry out the high temperature anneal formed P+ body contact jaw, the injection of p type impurity
Dosage is 5E14 ~ 5E15cm-2, energy 50-100Kev；It is miscellaneous according to figure (dash area in Fig. 5) the injection N-type of N+ light shield
Matter, and carry out the high temperature anneal and form N+ source, the implantation dosage of N-type impurity is 5E14 ~ 1E16cm-2, energy 50-
80Kev, as shown in Figure 6.Wherein, the type of the p type impurity includes B and BF2；The type of the N-type impurity include P, As and
In。
In order to enhance device highly resistance single event burnout ability under radiation environment, changes device architecture, increase power
Contact in MOSFET body, is conducive to that single-particle hole charge is compound, is formed between the channel region of device such as the light shield of Fig. 7
Figure 9 according to the 9 injecting p-type impurity of figure of light shield, and carries out the high temperature anneal, such as Fig. 8；The injectant of the p type impurity
Amount is 1E15-1E16cm-2, energy 70-120Kev, the type of the p type impurity includes B and BF2.
Then as shown in figure 9, carrying out the deposit of grid oxygen SiO2 5 growth and polysilicon 6；Then to grid oxygen SiO2 5 and more
Crystal silicon 6 carries out photoetching and corrosion, forms polysilicon gate control terminal, such as Figure 10；Finally carry out dielectric layer 7 deposit, contact hole photoetching and
Corrosion, then the deposit of metal 8 and lithography corrosion process are carried out, metal connecting line is formed, such a complete device basically forms；?
Surface passivation protective layer forms complete VDMOS power device, such as Figure 11.
The VDMOS power device prepared by the preparation method of above-mentioned VDMOS power device, increases VDMOS power
Device body contact structure, the number of cavities generated in ionization by collision are shunted by effective, reduce power MOSFET in list
Possibility is connected in parasitic triode under the conditions of particle irradiation, while improving EAS(energy avalanche stress, Energy
Avalanche Stress) ability, improve reliability.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (9)
1. a kind of preparation method of VDMOS power device characterized by comprising
The figure of light shield is formed between the channel region of device；
According to the figure injecting p-type impurity of light shield, and carry out the high temperature anneal；The implantation dosage of the p type impurity is 1E15-
1E16cm-2, energy 70-120Kev.
2. the preparation method of VDMOS power device as described in claim 1, which is characterized in that device channel region it
Between formed light shield figure before, the preparation method of the VDMOS power device further include:
Silicon substrate is provided, grows silicon epitaxial layers on the silicon substrate；
According to the figure of p-well light shield, the figure of p-well needed for being formed；
According to p-well light mask image injecting p-type impurity, dosage is 5E12 ~ 5E13cm-2, energy 50-80Kev, and carry out high temperature and move back
Fiery processing forms p-well；
According to the figure of N+/P+ light shield, it is respectively formed the figure of source and body contact；
According to the figure injecting p-type impurity of P+ light shield, and carries out the high temperature anneal and form P+ body contact jaw；According to N+ light shield
Figure injects N-type impurity, and carries out the high temperature anneal and form N+ source.
3. the preparation method of VDMOS power device as claimed in claim 2, which is characterized in that be used to form P+ body contact jaw
P type impurity implantation dosage be 5E14 ~ 5E15cm-2, energy 50-100Kev；It is used to form the note of the N-type impurity of N+ source
Entering dosage is 5E14 ~ 1E16cm-2, energy 50-80Kev.
4. the preparation method of VDMOS power device as described in claim 1, which is characterized in that carrying out the high temperature anneal
Afterwards, the preparation method of the VDMOS power device further include:
Carry out the deposit of grid oxygen SiO2 growth and polysilicon；
Photoetching and corrosion are carried out to grid oxygen SiO2 and polysilicon, form polysilicon gate control terminal；
Dielectric layer deposition, contact hole photoetching and corrosion are carried out, then carries out Metal deposition and lithography corrosion process, metal is formed and connects
Line；
In surface passivation protective layer, complete VDMOS power device is formed.
5. the preparation method of VDMOS power device as claimed in claim 2, which is characterized in that the resistivity of the silicon substrate
For 0.002 ~ 0.004 Ω cm.
6. the preparation method of VDMOS power device as claimed in claim 2, which is characterized in that the resistance of the silicon epitaxial layers
Rate is 3 ~ 24 Ω cm, with a thickness of 3um ~ 50um.
7. the preparation method of VDMOS power device as claimed in claim 3, which is characterized in that the type packet of the p type impurity
Include B and BF2.
8. the preparation method of VDMOS power device as claimed in claim 3, which is characterized in that the type packet of the N-type impurity
Include P, As and In.
9. a kind of VDMOS power device that the preparation method of -8 any VDMOS power devices according to claim 1 is prepared
Part.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810763625.1A CN108962756A (en) | 2018-07-12 | 2018-07-12 | A kind of preparation method of VDMOS power device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810763625.1A CN108962756A (en) | 2018-07-12 | 2018-07-12 | A kind of preparation method of VDMOS power device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235942A1 (en) * | 2002-06-14 | 2003-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
-
2018
- 2018-07-12 CN CN201810763625.1A patent/CN108962756A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030235942A1 (en) * | 2002-06-14 | 2003-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
Non-Patent Citations (1)
| Title |
|---|
| 施敏等: "《半导体器件物理与工艺 第3版》", 30 April 2014 * |
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Application publication date: 20181207 |