CN108962313A - Memory operation method and memory operation device - Google Patents

Abstract

A memory operation method and a memory operation device are provided. The memory operation method includes the following steps. A first step loop is executed and a second step loop is executed. In the first further cycle, a first control voltage applied to a first control line is increased from a first initial value to a first final value, and a second control voltage applied to a second control line is fixed at a second initial value. The first final value is higher than the first initial value. In the second step loop, the first control voltage applied to the first control line is fixed at a fixed value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value. The second final value is higher than the second starting value.

Description

Memory operating method and memory operating device

technical field

The invention relates to an operating method and an operating device, and in particular to a memory operating method and a memory operating device.

Background technique

With the development of memory technology, various memories are constantly being introduced. Resistive Random-Access Memory (ReRAM) and Phase-Change Memory (PCM) are non-volatile random-access memories. Variable resistance memory operates by changing the resistance of a dielectric solid material. The operation of the phase change memory is operated by changing the phase. In the variable resistance memory and the phase change memory, the memory cell needs good writing control ability to avoid the problem of over-writing. However, if too many operation steps are adopted, the operation speed will be affected.

Contents of the invention

The present invention relates to a memory operation method and a memory operation device, which use a method of executing a first stepping loop and a second stepping loop to speed up the operation speed.

According to an aspect of the present invention, a method for operating a memory is provided. The memory operation method includes the following steps. Execute a first stepping cycle and execute a second stepping cycle. In the first step cycle, a first control voltage applied to a first control line is increased from a first initial value to a first final value, and a second control voltage applied to a second control line is fixed at a second initial value. The first final value is higher than the first starting value. In the second step cycle, the first control voltage applied to the first control line is fixed at a fixed value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value. The second final value is higher than the second starting value.

According to another aspect of the present invention, a memory operating device is provided. The memory operating device includes a first controller, a second controller and a processor. The first controller is used for controlling a first control voltage applied to a first control line. The second controller is used for controlling a second control voltage applied to the second control line. The processor is used for executing a first stepping loop and a second stepping loop. In the first step cycle, a first control voltage applied to a first control line is increased from a first initial value to a first final value, and a second control voltage applied to a second control line is fixed at a second initial value. The first final value is higher than the first starting value. In the second step cycle, the first control voltage applied to the first control line is fixed at a fixed value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value. The second final value is higher than the second starting value.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically listed below, and the accompanying drawings are described in detail as follows:

Description of drawings

FIG. 1 is a schematic diagram of a memory operating device.

2A-2B illustrate a flow chart of a memory operating method according to an embodiment.

Figure 3 is a distribution diagram of the total number of guns.

FIG. 4 is an impedance distribution diagram according to the present embodiment.

5A-5B are flowcharts of a memory operation method according to another embodiment.

【Symbol Description】

100: memory operation device

110: First controller

120: second controller

130: Processor

200: memory

C1, C2, C3, C4, C5, C6, C7: curves

CL1: first control line

CL2: second control line

CV1: first control voltage

CV2: second control voltage

S211, S212, S221, S222, S223, S224, S225, S231, S232, S233, S234, S235, S531: steps

SL21, SL51: first step cycle

SL22, SL52: second step cycle

W1: window

Detailed ways

Please refer to FIG. 1 , which shows a schematic diagram of a memory operating device 100 . The memory operating device 100 is used for operating a memory 200 . The memory operating device 100 is, for example, a computer, a processing device, a circuit board, a circuit, a chip or a storage device storing an array of program codes. The memory 200 is, for example, a variable resistance memory (Resistive Random-Access Memory, ReRAM) and a phase-change memory (Phase-Change Memory, PCM). The memory 200 includes several first control lines CL1 and several second control lines CL2. In an embodiment, each first control line CL1 may be a bit line or a source line, and each second control line CL2 may be a word line. In another embodiment, each first control line CL1 may be a word line, and each second control line CL2 may be a bit line or a source line. The memory operating device 100 includes a first controller 110 , a second controller 120 and a processor 130 . The first controller 110 is used to control the first control line CL1, and the second controller 120 is used to control the second control line CL2.

Please refer to FIGS. 2A-2B , which illustrate a flow chart of a memory operating method according to an embodiment. The memory operation method is used to execute the operation program such as FORM, SET or RESET. For these operating procedures, the operating speed must be improved to suit various applications. In this embodiment, the operation method includes two stepping loops, such as a first stepping loop (first stepping loop) SL21 and a second stepping loop (second stepping loop) SL22.

In the first step cycle SL21, the first control voltage CV1 applied to the first control line CL1 gradually increases, and the second control voltage CV2 applied to the second control line CL2 is fixed.

In the second step cycle SL22, the first control voltage CV1 applied to the first control line CL1 is fixed, and the second control voltage CV2 applied to the second control line CL2 is gradually increased.

The second stepping loop SL22 is executed after the first stepping loop SL21. When the first stepping loop SL21 is completed, the flow enters the second stepping loop SL22 without returning to the first stepping loop SL21. By executing the first stepping cycle SL21 and the second stepping cycle SL22, the operating speed can be effectively improved.

More specifically, the memory operation method includes the following steps. In step S211 , the processor 130 loads relevant information from the memory 200 to define a first initial value of the first control voltage CV1 . In step S212 , the processor 130 loads relevant information from the memory 200 to define a second initial value of the second control voltage CV2 . The first initial value is an appropriate value at which the writing (forming) current can pass through the first control line CL1 of the memory 200 without causing over-writing. Usually, the first initial value is close to but smaller than a switchpoint of the dynamic resistance diagram of the memory 200 . For example, the first initial value is 2V. Likewise, the second initial value is an appropriate value at which the writing (forming) current can pass through the second control line CL2 of the memory 200 without causing over-writing. Typically, the second initial value is close to but smaller than the turning point of the dynamic resistance graph of the memory 200 . For example, the second initial value is 2V.

Please refer to Table 1, in the first step cycle SL21 and the second step cycle SL22, the first control voltage CV1 and the second control voltage CV2 are set according to Table 1.

Table 1

Next, in step S221 , the first controller 110 sets the first control voltage CV1 and the second controller 120 sets the second control voltage CV2 .

In step S222 , perform operations such as FORM, SET, and RESET on the memory 200 according to the first control voltage CV1 and the second control voltage CV2 .

Next, in step S223, the processor 130 determines whether the operation procedures such as FORM, RESET, and SET have been completed. If the operation procedures such as FORM, SET, and RESET have been completed, the process ends; if the operation procedures such as FORM, SET, and RESET have not been completed, then enter step S224.

In step S224, the processor 130 determines whether the first control voltage CV1 has reached the first final value. For example, the first final value may be 5V. If the first control voltage CV1 reaches the first final value, go to step S231; if the first control voltage CV1 has not yet reached the first final value, go to step S225.

In step S225, the first control voltage CV1 is increased by a predetermined value (for example, 1V). Then, the process returns to step S221 and step S222 to execute the operation program of the memory 200 again. The first stepping loop SL21 is repeatedly executed until the FORM, SET, RESET etc. procedures are completed or the first control voltage CV1 reaches the first final value.

In step S231 , the first controller 110 fixes the first control voltage CV1 applied to the first control line CL1 at a fixed value, and the second controller 120 increases the second control voltage CV2 applied to the second control line CL2 . The second control voltage CV2 starts to increase from an intermediate value. In this embodiment, the fixed value is equal to the first final value. For example, the first final value is 5V, and the fixed value is also 5V. The intermediate value is higher than the second starting value. For example, the second initial value is 2V, and the intermediate value is 3V.

In step S232, the first controller 110 sets the first control voltage CVI and the second controller 120 sets the second control voltage CV2.

In step S233 , according to the first control voltage CV1 and the second control voltage CV2 , perform operations such as FORM, SET, and RESET on the memory 200 .

Next, in step S234, the processor 130 determines whether the operation procedures such as FORM, RESET, and SET have been completed. If the FORM, SET, and RESET have been completed, then end this process; if the FORM, SET, and RESET have not been completed, then enter step S235.

In step S235, the processor 130 determines whether the second control voltage CV2 reaches the second final value. For example, the second final value may be 5V. If the second control voltage reaches the second final value, then end the process; if the second control voltage has not yet reached the second final value, return to step S231. If the process returns to step S231 and step S232, the second controller 120 increases the second control voltage CV2 again, and executes the operation program on the memory 200 again according to the second control voltage CV2.

The second step cycle SL22 is repeatedly executed until the FORM, SET, RESET, etc. operation procedures are completed, or the second control voltage CV2 reaches the second final value.

That is to say, in the first step cycle SL21, the first control voltage CV1 applied to the first control line CL1 increases from the first initial value to the first final value (greater than the first initial value); The second control voltage CV2 of line CL2 is fixed at a second initial value. In the second step cycle SL22, the first control voltage CV1 applied to the first control line CL1 is fixed at a fixed value (equal to the first final value); the second control voltage CV2 applied to the second control line CL2 changes from an intermediate value to (higher than the second starting value) to a second final value (above the intermediate value).

Please refer to Table 2, which illustrates an example of the FROM program. In this example, the memory 200 is a variable resistance memory composed of a titanium nitride layer (TiN)-tungsten oxide layer (WOx)-titanium nitride layer (TiN), and the first control line CL1 is a bit line (or source line), and the second control line CL2 is a word line. In the first step cycle SL21, the bit line voltage is gradually increased from 2V to 4V, and the word line voltage is fixed at 2V. In the second step cycle SL22, the bit line voltage is fixed at 4V, and the word line voltage is gradually increased from 3V to 4V. In this example, the total number of shots is 5. Compared to the traditional FORM program, the total number of shots is 9. Therefore, the operating speed of this example is greatly improved.

Table 2

Please refer to Table 3, which illustrates an example of the SET procedure. In this example, the memory 200 is a variable resistance memory composed of titanium nitride layer (TiN)-tungsten oxide layer (WOx)-titanium nitride layer (TiN), the first control line CL1 is a word line, and the second control line CL1 is a word line. The second control line CL2 is a bit line (or a source line). In the first step cycle SL21, the word line voltage is gradually increased from 2V to 5V, and the bit line voltage is fixed at 2V. In the second step cycle SL22, the word line voltage is fixed at 5V, and the bit line voltage is gradually increased from 3V to 5V. In this example, the total number of guns is 7. Compared to the traditional SET procedure, the total number of shots is 16. Therefore, the operating speed of this example is greatly improved.

table 3

Please refer to Table 4, which illustrates an example of the RESET procedure. In this example, the memory 200 is a variable resistance memory composed of titanium nitride layer (TiN)-tungsten oxide layer (WOx)-titanium nitride layer (TiN), the first control line CL1 is a word line, and the second control line CL1 is a word line. The second control line CL2 is a bit line (or a source line). In the first step cycle SL21, the word line voltage is gradually increased from 2V to 5V, and the bit line voltage is fixed at 2V. In the second step cycle SL22, the word line voltage is fixed at 5V, and the bit line voltage is gradually increased from 3V to 5V. In this example, the total number of guns is 7. Compared to the traditional RESET procedure, the total number of shots is 16. Therefore, the operating speed of this example is greatly improved.

Table 4

Please refer to Figure 3, which is a distribution diagram of the total number of guns. Fig. 3 shows four curves C1, C2, C3, C4. Curve C1 represents the distribution of the total number of guns of the traditional SET program, curve C2 represents the distribution of the total number of guns of the traditional RESET program, curve C3 represents the distribution of the total number of guns of the SET program of the present invention, and curve C4 represents the total number of guns of the RESET program of the present invention distribution of numbers. As shown by curve C1, some traditional SET procedures require more than 6 total shots. As shown by the curve C3, all the SET procedures of the present invention require less than 6 total shots. That is, the operating speed of the SET program of the present invention is improved.

As shown by curve C2, some traditional RESET procedures require more than 6 total shots. As shown by curve C4, all RESET procedures of the present invention require less than 6 total shots. That is, the operation speed of the RESET procedure of the present invention is improved.

Please refer to FIG. 4 , which is an impedance distribution diagram according to this embodiment. Fig. 4 draws three curves C5, C6, C7. Curve C5 represents the impedance distribution after executing the SET procedure of the present invention, curve C6 represents the impedance distribution after executing the RESET procedure of the present invention, and curve C7 represents the impedance distribution after executing the FORM procedure of the present invention. A window (window) W1 is formed between the curve C5 and the curve C6, so that the SET state and the RESET state can be clearly distinguished. That is, even though the total number of shots has been reduced, the SET procedure and the RESET procedure still have good results.

Please refer to FIGS. 5A-5B , which illustrate a flow chart of a memory operating method according to another embodiment. Please refer to Table 5, in the first step cycle SL21 and the second step cycle SL22, the first control voltage CV1 and the second control voltage CV2 are set according to Table 5.

table 5

In this embodiment, the first stepping cycle SL51 is similar to the first stepping cycle SL21, and the similarities will not be repeated. In step S531 of the second stepping loop SL52, the fixed value is smaller than the first final value. The fixed value can be calculated according to the following formula (1).

FX＝FN-Δ…………………………………(1)

FX is a fixed value, FN is a first final value, and Δ is 0 to the first final value.

Alternatively, in another embodiment, the ratio of the fixed value to the first final value may be higher than 0.8. Alternatively, in another embodiment, the difference between the fixed value and the first final value may be greater than 0.1V. For example, the first final value is 5V, and the fixed value is 4.5V.

Since the first control voltage CV1 of the second step cycle SL52 is fixed at a value lower than the first final value (ie, the fixed value is lower than the first final value), the situation of over-writing can be effectively avoided.

That is to say, in the first step cycle SL51, the first control voltage CV1 applied to the first control line CL1 increases from the first initial value to the first final value (greater than the first initial value); The second control voltage CV2 on the second control line CL2 is fixed at a second initial value. In the second step cycle SL52, the first control voltage CV1 applied to the first control line CL1 is fixed at a fixed value (less than the first final value); the second control voltage CV2 applied to the second control line CL2 changes from an intermediate value to (higher than the second starting value) to a second final value (above the intermediate value).

According to the various embodiments described above, by executing the first stepping loop SL21, SL51 and the second stepping loop SL22, SL52, the operation speed can be greatly improved.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (10)

1. a kind of memory operating method, comprising:

One first step cycle is executed, wherein being applied to one first control of one first control line in first step cycle Voltage increases to one first end value by one first initial value, which is higher than first initial value, and is applied to one One second control voltage of the second control line is fixed on one second initial value；And

One second step cycle is executed, wherein being applied to the first control electricity of first control line in second step cycle Pressing schedules a fixed value, and the second control voltage for being applied to second control line increases to one second most by intermediate value in one Final value, second end value are higher than second initial value.

2. memory operating method as described in claim 1, wherein intermediate value is higher than second initial value in this.

3. memory operating method as described in claim 1, wherein the fixed value be equal to first end value or lower than this One end value.

4. memory operating method as claimed in claim 3, wherein a ratio of the fixed value and first end value is higher than 0.8。

5. memory operating method as described in claim 1, wherein second step cycle is implemented in first step cycle Later.

6. a kind of storage operation device, comprising:

One first controller, to control the one first control voltage for being applied to one first control line；

One second controller, to control the one second control voltage for being applied to the second control line；And

One processor, to execute one first step cycle and one second step cycle, wherein

In first step cycle, the one first control voltage for being applied to one first control line is increased to by one first initial value One first end value, first end value are higher than first initial value, and are applied to one second control electricity of one second control line Pressing schedules one second initial value；And

In second step cycle, the first control voltage for being applied to first control line is fixed on a fixed value, and applies The second control voltage for being added on second control line increases to one second end value by intermediate value in one, which is higher than Second initial value.

7. storage operation device as claimed in claim 6, wherein intermediate value is higher than second initial value in this.

8. storage operation device as claimed in claim 6, wherein the fixed value be equal to first end value or lower than this One end value.

9. storage operation device as claimed in claim 8, wherein a ratio of the fixed value and first end value is higher than 0.8。

10. storage operation device as claimed in claim 6, wherein second step cycle is implemented in first step cycle Later.