CN108807407B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 63
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 98
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 150000002500 ions Chemical class 0.000 claims abstract description 37
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 230000005641 tunneling Effects 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 description 16
- 125000006850 spacer group Chemical group 0.000 description 12
- -1 arsenic ions Chemical class 0.000 description 11
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical group [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps of providing a substrate, forming a split-gate flash memory device unit and a logic device unit on the substrate, forming a first interval oxide layer on the outer side surface of a side wall of the split-gate flash memory device unit, simultaneously carrying out ion implantation on the substrate between the first interval oxide layer of the split-gate flash memory device unit and a bit line and the substrate between the side wall of the logic device unit and an isolation structure by adopting the same photomask and the same ions in the same ion implantation process, forming a heavily doped N-type drain region in the substrate between the first interval oxide layer of the split-gate flash memory device unit and the bit line, and forming a heavily doped N-type source/drain region in the substrate between the side wall of the logic device unit and the isolation structure. The invention can overcome the transverse punch-through effect, reduce the manufacturing cost and improve the production efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
Semiconductor devices, such as single chip Microcomputers (MCUs), include split gate flash memory device units and logic device units, which are individually, for example, control units, etc. Referring to fig. 1, in manufacturing a single chip, after forming a split-gate flash memory device unit 20 and a logic device unit 30 in the same substrate 10, two masks and two ions are respectively used to perform an ion implantation process to form an N-type doped drain (NGRD) region and an N-type heavily doped (NPLUS, N +) N-type source/drain region. One of the ion implantation processes is to form a heavily doped N-type drain region 28 in the split-gate flash memory device cell 20 using an NGRD mask and arsenic (As) ions, and the other is to form a heavily doped N-type source/drain region 35 in the logic device cell 30 using an NPLUS mask and phosphorus (P) ions. As the mass of arsenic ions in the NGRD is heavier than that of phosphorus ions in the NPLUS, the transverse diffusion degree of the NGRD in the split-gate flash memory device unit is relatively weak, so that the punch-through effect from a bit line to a word line channel of the split-gate flash memory device unit is controlled, and the problem of programming crosstalk failure in the split-gate flash memory device unit is solved. The manufacturing process of the semiconductor device has the disadvantages that the two ion implantation processes are adopted for forming the N-type drain region in the split-gate flash memory unit in the semiconductor device and the N-type heavily-doped N-type source/drain region in the logic device unit, and two different ions are adopted, so that the manufacturing cost is increased, and the production efficiency is reduced.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same, which overcomes the lateral punch-through effect, reduces the manufacturing cost and improves the production efficiency.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate;
respectively forming a split-gate flash memory device unit and a logic device unit on the substrate;
forming an oxide layer on the surface of the split-gate flash memory unit;
reserving an oxide layer covering the outer side face of the side wall of the split-gate flash memory device unit, and removing the oxide layer in other areas to form a first interval oxide layer on the outer side face of the side wall of the split-gate flash memory device unit, wherein a gap is reserved between the first interval oxide layer and a bit line of the split-gate flash memory device unit;
and simultaneously performing ion implantation on the substrate between the first interval oxide layer and the bit line of the split-gate flash memory unit and the substrate between the side wall of the logic device unit and the isolation structure by adopting the same photomask and the same ions in the same ion implantation process, forming a heavily doped N-type drain region in the substrate between the first interval oxide layer and the bit line of the split-gate flash memory unit, and forming a heavily doped N-type source/drain region in the substrate between the side wall of the logic device unit and the isolation structure.
Further, the method for manufacturing a semiconductor device provided by the present invention further includes forming an oxide layer on a surface of the logic device unit; reserving an oxide layer covering the outer side surface of the side wall of the logic device unit, and removing the oxide layer in other areas to form a second interval oxide layer on the outer side surface of the side wall of the logic device unit, wherein a gap is reserved between the second interval oxide layer and the isolation structure of the logic device unit; and performing ion implantation on the substrate between the second isolation oxide layer of the logic device unit and the isolation structure in the same ion implantation process, wherein a heavily doped N-type source/drain region is formed in the substrate between the second isolation oxide layer of the logic device unit and the isolation structure.
Further, the thickness of the oxide layer covered by the manufacturing method of the semiconductor device is 200 angstroms.
Further, in the manufacturing method of the semiconductor device provided by the invention, the step of removing the oxide layer in the other region is a wet etching process.
Further, in the method for manufacturing a semiconductor device according to the present invention, the ion is phosphorus.
Furthermore, in the manufacturing method of the semiconductor device provided by the invention, the split-gate flash memory device unit and the logic device unit adopt the same substrate, and the substrate is of an N type.
Further, in the manufacturing method of the semiconductor device provided by the present invention, the step of forming the split-gate flash memory device unit includes: and forming a tunneling oxide layer, a floating gate, a word line, a side wall, a source region and a source line on the substrate, and a bit line which extends upwards along the substrate and is arranged at an interval with the side wall.
Further, in the method for manufacturing a semiconductor device according to the present invention, the step of forming the logic device unit includes: the method comprises the steps of forming an insulating oxide layer and a grid structure on a substrate, forming a side wall on the outer side surface of the grid structure, and forming an isolation structure which extends downwards along the substrate and is arranged at an interval with the side wall.
Compared with the prior art, according to the manufacturing method of the semiconductor device, after the ion implantation process, the concentration of ions implanted into the substrate region below the word line of the N-type drain region is smaller than that of the ions implanted into the substrate region between the bit line and the first interval oxide layer due to the fact that the ions are blocked by the first interval oxide layer, so that the phenomenon of lateral diffusion of the ions in the substrate region below the word line is controlled, the situation that the lateral diffusion region of the ions is enlarged is avoided, the punch-through effect from the bit line to the word line channel of the split-gate flash memory device unit is overcome, and the problem of programming crosstalk failure is solved. The manufacturing method of the semiconductor device provided by the invention has the advantages that the N-type drain electrode region of the split-gate flash memory unit and the heavily doped N-type source/drain electrode region in the logic device unit are simultaneously manufactured in one ion implantation process, and the same photomask is adopted, so that the manufacturing process of the photomask in one process is reduced, the production efficiency is improved, and the manufacturing cost is reduced. In addition, the same ion is adopted in one ion implantation process, so that the manufacturing process of the process is quicker, and the production efficiency is further improved.
In order to solve the above technical problem, the present invention further provides a semiconductor device, including a split-gate flash memory device unit and a logic device unit formed on the basis of the same substrate; the split-gate flash memory unit comprises a tunneling oxide layer, a floating gate, word lines, side walls, a source region, source lines and bit lines, wherein the tunneling oxide layer, the floating gate, the word lines, the side walls, the source region and the source lines are formed on a substrate, the bit lines extend upwards along the substrate and are arranged at intervals with the side walls, a first interval oxide layer is formed on the outer side faces of the side walls of the split-gate flash memory unit, gaps are reserved between the first interval oxide layer and the bit lines, and heavily-doped N-type drain regions are formed in the substrate between the first interval; the logic device unit comprises an insulating oxide layer and a grid structure which are formed on a substrate, a side wall which is formed on the outer side face of the grid structure, and an isolation structure which extends downwards along the substrate and is arranged at an interval with the side wall on the outer side face of the grid structure, wherein a heavily doped N-type source/drain region is formed in the substrate between the side wall on the outer side face of the grid structure and the isolation structure.
Furthermore, in the semiconductor device provided by the invention, the logic device unit further comprises a second isolation oxide layer formed on the outer side surface of the side wall of the logic device unit, a gap is reserved between the second isolation oxide layer and the isolation structure, and the heavily doped N-type source/drain region is formed in the substrate between the second isolation oxide layer and the isolation structure.
Compared with the prior art, the semiconductor device provided by the invention has the advantages that the concentration of ions implanted in the substrate region below the word line of the N-type drain region is smaller than that of ions implanted in the substrate region between the bit line and the first interval oxide layer due to the fact that the ions are blocked by the first interval oxide layer, so that the phenomenon of lateral diffusion of the ions in the substrate region below the word line is controlled, the situation that the lateral diffusion region of the ions is enlarged is avoided, the punch-through effect from the bit line to the word line channel of the split-gate flash memory device unit is overcome, and the problem of programming crosstalk failure is solved.
Drawings
Fig. 1 is a schematic configuration diagram of a conventional manufacturing process of a semiconductor device;
fig. 2 is a flowchart of a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
fig. 3 is a schematic structural view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention;
fig. 4 is a flowchart of a manufacturing process of a semiconductor device of a second embodiment of the present invention;
fig. 5 to 7 are schematic structural views of a manufacturing process of a semiconductor device according to a second embodiment of the present invention;
fig. 8 is a flowchart of a manufacturing process of a semiconductor device of a third embodiment of the present invention;
fig. 9 to 11 are schematic structural views of a manufacturing process of a semiconductor device according to another embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
example one
Referring to fig. 2 and fig. 3, in an embodiment, a method for manufacturing a semiconductor device capable of reducing manufacturing cost and improving production efficiency is provided, and the embodiment is described by taking a single chip Microcomputer (MCU) as an example, and includes the following specific steps:
102, respectively forming a split-gate flash memory device unit 20 and a logic device unit 30 on the substrate 10; wherein the split gate flash memory unit 20 is a memory part of a single chip, and the logic device unit 30 is a logic control part of the single chip.
In step 103, an NPLUS photomask and phosphorus ions are used to simultaneously perform an ion implantation process on the split-gate flash memory device unit 20 and the logic device unit 30, so as to form an N-type doped drain (NGRD) 28 in the split-gate flash memory device unit 20, and an N-type heavily doped (NPLUS, N +) source/drain 35 in the logic device unit 30. That is, the present embodiment reduces the two mask processes to one mask process, and reduces the two ion sources to one, so as to achieve the purpose of reducing the cost and improving the production efficiency by one ion implantation process.
The first embodiment has the disadvantage that, as the NPLUS photomask and the phosphorus ions in the logic device unit 30 are used to perform the ion implantation process, the phosphorus ions in the NPLUS type source/drain region 35 formed meet the device requirements, and in the N-type drain region 28 formed, the lateral diffusion degree of the phosphorus ions is greater than that of the arsenic ions in the NGRD photomask process, so that the lateral diffusion degree of the phosphorus ions in the N-type drain region 28 towards the substrate region under the word line 23 is increased, for ease of understanding and description, the increased lateral diffusion region is referred to as the laterally increased diffusion region 28+, the laterally increased diffusion region enhances the lateral punch-through effect of the bit line 27 of the split-gate flash memory unit 20 towards the channel of the word line 23, and the phosphorus ions cannot control the lateral diffusion phenomenon of the N-type drain region 28 due to their own weight, thereby causing the problems of program crosstalk failure of the split-gate flash memory unit 20, the electrical performance of the split-gate flash memory unit 20 is affected and the overall performance of the semiconductor devices such as the single chip microcomputer is affected.
Example two
Referring to fig. 4 to fig. 8, the method for manufacturing a semiconductor device according to the second embodiment includes the following steps:
in step 201, a substrate 10 is provided, as shown in fig. 5.
At step 202, a split-gate flash memory device unit 20 and a logic device unit 30 are respectively formed on the substrate 10, as shown in fig. 5. The split-gate flash memory unit 20 is a memory part of the single chip, and the logic device unit 30 is a logic control part of the single chip.
Referring to fig. 5, the step of forming the split-gate flash memory device cell 20 in step 202 includes: a tunneling oxide layer 21, a floating gate 22, a word line 23, a sidewall 24, a source region 25, a source line 26, and a bit line 27 extending upward along the substrate 10 and spaced from the sidewall 24 are formed on the substrate 10. The step of forming the split-gate flash memory device unit 20 is adjusted according to the specific structure of the split-gate flash memory device unit 20, and is not limited to the specific steps.
Referring to fig. 5, the step of forming the logic device unit 30 in step 202 includes: an insulating oxide layer 31 and a gate structure 32 are formed on a substrate 10, a sidewall 33 is formed on an outer side surface of the gate structure 32, and an isolation structure 34 extends downward along the substrate 10 and is spaced from the sidewall 33. The gate structure 32 is not limited to the above specific structure, and may be a stacked structure or other structures, and the isolation structure 34 employs an isolation process such as Shallow Trench Isolation (STI). Similarly, the steps of forming the logic device unit 30 are adjusted according to the specific structure of the logic device unit 30, and are not limited to the specific steps described above.
In step 203, an oxide layer 40 is formed on the surface of each of the split-gate flash memory device unit 20 and the logic device unit 30, as shown in fig. 5.
In the manufacturing method of the semiconductor device according to the second embodiment, after the ion implantation process, the concentration of the ions implanted in the substrate region below the word line 23 of the N-type drain region 28 of the split-gate flash memory device unit 20 is smaller than the concentration of the ions implanted in the substrate region between the bit line 27 and the first spacer oxide layer 29 due to being blocked by the first spacer oxide layer 29, so that the phenomenon of lateral diffusion of the ions in the substrate region below the word line 23 is controlled, the situation that the lateral diffusion region of the ions becomes larger is avoided, and the laterally enlarged diffusion region is not generated in the first embodiment, so that the Punch-Through effect (PTC) from the bit line 27 to the word line 23 channel of the split-gate flash memory device unit is overcome, and the problem of programming crosstalk failure is solved.
In the manufacturing method of the semiconductor device provided in the second embodiment, since the N-type drain region 28 of the split-gate flash memory device unit 20 and the heavily doped N-type source/drain region 35 of the logic device unit 30 are simultaneously manufactured in one ion implantation process and the same photomask is used, a manufacturing process of a photomask is reduced, production efficiency is improved, and manufacturing cost is reduced. In addition, the same ion is adopted in one ion implantation process, so that the manufacturing process of the process is quicker, and the production efficiency is further improved.
Referring to fig. 5 to 7, in the method for manufacturing a semiconductor device according to the second embodiment, the thickness of the covering oxide layer 40 is 200 angstroms, so that the formed spacer oxide layer has a blocking effect during ion implantation.
In the manufacturing method of the semiconductor device provided in the second embodiment, the step of removing the Oxide layer in the other region is a wet etching process, such as Buffered Oxide Etch (BOE). The ion source is an ion in an ion implantation process for forming N-type source/drain regions of the logic device cell 30. I.e. the ion source is phosphorous, although other suitable ions may be selected according to the actual process requirements.
In the manufacturing method of the semiconductor device provided in the second embodiment, the split-gate flash memory device unit 20 and the logic device unit 30 use the same substrate 10, and the substrate 10 is N-type. I.e., both the split-gate flash memory device cell 20 and the logic device cell 30 are N-type devices.
EXAMPLE III
Referring to fig. 6, the third embodiment provides a semiconductor device including a split-gate flash memory device unit 20 and a logic device unit 30 formed on the same substrate 10.
The split-gate flash memory device unit 20 includes a tunneling oxide layer 21, a floating gate 22, a word line 23, a sidewall 24, a source region 25, a source line 26, and a bit line 27 extending upward along the substrate 10 and spaced from the sidewall 24, wherein a first spaced oxide layer 29 is formed on an outer side surface of the sidewall 24 of the split-gate flash memory device unit 20, a gap is left between the first spaced oxide layer 29 and the bit line 27, and a heavily doped N-type drain region 28 is formed in the substrate 10 between the first spaced oxide layer 29 and the bit line 27.
The logic device unit 30 includes an insulating oxide layer 31 and a gate structure 32 formed on a substrate 10, a sidewall 33 formed on an outer side of the gate structure 32, and an isolation structure 34 extending downward along the substrate 10 and spaced apart from the sidewall 33 on the outer side of the gate structure 32, a second insulating oxide layer 36 is formed on the outer side of the sidewall 33 of the logic device unit 30, a gap is left between the second insulating oxide layer 36 and the isolation structure 34, and a heavily doped N-type source/drain region 35 is formed in the substrate 10 between the second insulating oxide layer 36 and the isolation structure 34.
In the third embodiment, the concentration of the ions implanted in the substrate region under the word line 23 of the N-type drain region 28 of the split-gate flash memory device unit 20 is smaller than the concentration of the ions implanted in the substrate region between the bit line 27 and the first spacer oxide layer 29 because the ions are blocked by the first spacer oxide layer 29, so that the phenomenon of lateral diffusion of the ions in the substrate region under the word line 23 is controlled, the situation that the lateral diffusion region of the ions becomes large is avoided, the Punch Through disturb by Column, PTC, channel from the bit line 27 to the word line 23 of the split-gate flash memory device unit is overcome, and the problem of programming crosstalk failure is solved.
Example four
Referring to fig. 8 to 11, a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention includes:
in step 301, a substrate 10 is provided, as shown in FIG. 9.
In step 302, a split-gate flash memory device unit 20 and a logic device unit 30 are respectively formed on the substrate 10, as shown in fig. 9. The split-gate flash memory unit 20 is a memory part of the single chip, and the logic device unit 30 is a logic control part of the single chip.
Referring to fig. 9, the step of forming the split-gate flash memory device cell 20 in step 202 includes: a tunneling oxide layer 21, a floating gate 22, a word line 23, a sidewall 24, a source region 25, a source line 26, and a bit line 27 extending upward along the substrate 10 and spaced from the sidewall 24 are formed on the substrate 10. The step of forming the split-gate flash memory device unit 20 is adjusted according to the specific structure of the split-gate flash memory device unit 20, and is not limited to the specific steps.
Referring to fig. 9, the step of forming the logic device unit 30 in step 202 includes: an insulating oxide layer 31 and a gate structure 32 are formed on a substrate 10, a sidewall 33 is formed on an outer side surface of the gate structure 32, and an isolation structure 34 extends downward along the substrate 10 and is spaced from the sidewall 33. Wherein the gate structure 32 is not limited to a specific structure, the isolation structure 34 is, for example, a Shallow Trench Isolation (STI) or the like.
In step 303, an oxide layer 40 is formed on the surface of the split-gate flash memory device unit 20, as shown in fig. 9.
In the manufacturing method of the semiconductor device provided in the fourth embodiment, the steps of forming the oxide layer 40 in the logic device unit 30 and removing the oxide layer 40 to form the second isolation oxide layer 36 in the second embodiment are removed, and the heavily doped N-type source/drain regions 35 of the logic device unit 30 are formed in the substrate 10 between the sidewall spacers 33 and the isolation structures 34. The manufacturing process is simplified, so that the production efficiency is improved, the material is saved, and the manufacturing cost is reduced. The fourth embodiment does not affect the ion implantation of the N-type drain region 28, and therefore, the fourth embodiment also has the technical effects of overcoming the punch-through effect from the bit line 27 to the word line 23 channel of the split-gate flash memory cell and solving the problem of program cross-talk failure.
EXAMPLE five
Referring to fig. 10, a fifth embodiment provides a semiconductor device, which is an improvement of the semiconductor device of the third embodiment, and the device obtained by the manufacturing method corresponding to the fourth embodiment specifically includes a split-gate flash memory device unit 20 and a logic device unit 30 formed on the basis of the same substrate 10.
The split-gate flash memory device unit 20 includes a tunneling oxide layer 21, a floating gate 22, a word line 23, a sidewall 24, a source region 25, a source line 26, and a bit line 27 extending upward along the substrate 10 and spaced from the sidewall 24, wherein a first spaced oxide layer 29 is formed on an outer side surface of the sidewall 24 of the split-gate flash memory device unit 20, a gap is left between the first spaced oxide layer 29 and the bit line 27, and a heavily doped N-type drain region 28 is formed in the substrate 10 between the first spaced oxide layer 29 and the bit line 27.
The logic device unit 30 includes an insulating oxide layer 31 and a gate structure 32 formed on a substrate 10, a sidewall 33 formed on an outer side of the gate structure 32, and an isolation structure 34 extending downward along the substrate 10 and spaced apart from the sidewall 33 on the outer side of the gate structure 32, wherein a heavily doped N-type source/drain region 35 is formed in the substrate 10 between the sidewall 33 and the isolation structure 34.
The present invention is not limited to the above-described embodiments, and various changes and modifications within the scope of the present invention are within the scope of the present invention.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
respectively forming a split-gate flash memory device unit and a logic device unit on the substrate;
forming an oxide layer on the surface of the split-gate flash memory unit, and not forming an oxide layer on the surface of the logic device unit;
reserving an oxide layer covering the outer side face of the side wall of the split-gate flash memory device unit, and removing the oxide layer in other areas to form a first interval oxide layer on the outer side face of the side wall of the split-gate flash memory device unit, wherein a gap is reserved between the first interval oxide layer and a bit line of the split-gate flash memory device unit;
and simultaneously performing ion implantation on the substrate between the first interval oxide layer and the bit line of the split-gate flash memory unit and the substrate between the side wall of the logic device unit and the isolation structure by adopting the same photomask and the same ions in the same ion implantation process, forming a heavily doped N-type drain region in the substrate between the first interval oxide layer and the bit line of the split-gate flash memory unit, and forming a heavily doped N-type source/drain region in the substrate between the side wall of the logic device unit and the isolation structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the oxide layer is 200 angstroms.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the step of removing the oxide layer in the other region is a wet etching process.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the ion is phosphorus.
5. The manufacturing method of a semiconductor device according to claim 1, wherein the split-gate flash memory device unit and the logic device unit use the same substrate, and the substrate is N-type.
6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the split-gate flash memory device cell includes:
and forming a tunneling oxide layer, a floating gate, a word line, a side wall, a source region and a source line on the substrate, and a bit line which extends upwards along the substrate and is arranged at an interval with the side wall.
7. The manufacturing method of a semiconductor device according to claim 1, wherein the step of forming the logic device cell includes:
the method comprises the steps of forming an insulating oxide layer and a grid structure on a substrate, forming a side wall on the outer side surface of the grid structure, and forming an isolation structure which extends downwards along the substrate and is arranged at an interval with the side wall.
8. A semiconductor device is characterized by comprising a split-gate flash memory device unit and a logic device unit which are formed on the basis of the same substrate; the split-gate flash memory unit comprises a tunneling oxide layer, a floating gate, word lines, side walls, a source region, source lines and bit lines, wherein the tunneling oxide layer, the floating gate, the word lines, the side walls, the source region and the source lines are formed on a substrate, the bit lines extend upwards along the substrate and are arranged at intervals with the side walls, a first interval oxide layer is formed on the outer side faces of the side walls of the split-gate flash memory unit, gaps are reserved between the first interval oxide layer and the bit lines, and heavily-doped N-type drain regions are formed in the substrate between the first interval; the logic device unit comprises an insulating oxide layer and a grid structure which are formed on a substrate, a side wall which is formed on the outer side face of the grid structure and an isolation structure which extends downwards along the substrate and is arranged at intervals with the side wall on the outer side face of the grid structure, and a heavily doped N-type source/drain region is formed in the substrate between the side wall on the outer side face of the grid structure and the isolation structure; and forming no oxide layer on the surface of the logic device unit.
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