CN108806582B - Array substrate, electronic paper type display panel, driving method of electronic paper type display panel and display device - Google Patents
Array substrate, electronic paper type display panel, driving method of electronic paper type display panel and display device Download PDFInfo
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- CN108806582B CN108806582B CN201810708299.4A CN201810708299A CN108806582B CN 108806582 B CN108806582 B CN 108806582B CN 201810708299 A CN201810708299 A CN 201810708299A CN 108806582 B CN108806582 B CN 108806582B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
- G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
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Abstract
The invention discloses an array substrate, an electronic paper type display panel, a driving method of the electronic paper type display panel and a display device. The array substrate comprises at least two subarea control signal lines and a reference voltage signal line, a subarea control module of a pixel circuit is used for conducting or switching off a first input end and an output end of the subarea control module according to the voltage of a control end of the subarea control module, and conducting or switching off a second input end and an output end of the subarea control module, so that different pixels are controlled to be refreshed or kept respectively, the problem that the power consumption of the array substrate is high in the whole refreshing of all pixels in the prior art is solved, the pixels which do not need refreshing on the array substrate are kept, the pixels which are kept do not need to be charged to a pixel electrode again through a data line, the pixels which are kept are not interfered by signals generated by other pixels which are refreshed, and the display quality of a display panel formed by the array substrate is improved while the power consumption of the.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, an electronic paper type display panel, a driving method of the electronic paper type display panel and a display device.
Background
The electronic paper display is a flat panel display technology with paper display performance, and an electronic paper display panel has a huge application space in the fields of electronic paper labels, electronic readers (electronic books), electronic price tags, industrial instruments, dynamic display billboards, media products and the like.
In the prior art, most electronic paper displays are overall displays and are refreshed integrally, for example, for an electronic paper label which is long in length and includes a plurality of display items, if some individual display items need to be replaced, the display areas corresponding to the display items need to be refreshed, and the display areas corresponding to other display items also need to be refreshed, which undoubtedly increases the power consumption required for displaying. Therefore, the conventional electronic paper display has a problem of large power consumption.
Disclosure of Invention
The invention provides an array substrate, an electronic paper type display panel, a driving method of the electronic paper type display panel and a display device, and aims to achieve the effect of reducing power consumption.
In a first aspect, an embodiment of the present invention provides an array substrate, where the array substrate includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels defined by the plurality of scan lines and the plurality of data lines;
the array substrate further comprises at least two partition control signal lines and a reference voltage signal line, the pixel comprises a pixel circuit and a pixel electrode, and the pixel circuit comprises:
the input module comprises an input end, an output end and a control end; the control end of the input module is electrically connected with the scanning line, and the input end of the input module is electrically connected with the data line; the input module is used for switching on or switching off the input end and the output end of the input module according to the voltage of the control end of the input module;
the partition control module comprises a control end, a first input end, a second input end and an output end, the control end of the partition control module is electrically connected with the partition control signal line, the first input end of the partition control module is electrically connected with the output end of the input module, the second input end of the partition control module is electrically connected with the reference voltage signal line, the output end of the partition control module is electrically connected with the pixel electrode of the pixel, and the partition control module is used for conducting or switching off the first input end and the output end of the partition control module according to the voltage of the control end of the partition control module and conducting or switching off the second input end and the output end of the partition control module.
In a second aspect, an embodiment of the present invention further provides an electronic paper type display panel, where the electronic paper type display panel includes the array substrate, the electrophoretic film, and the common electrode layer, and the electrophoretic film is located between the array substrate and the common electrode layer.
In a third aspect, an embodiment of the present invention further provides a display device, where the display device includes the electronic paper display panel according to any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a driving method of an electronic paper type display panel according to any embodiment of the present invention, where the driving method includes:
transmitting a control signal to the partition control signal line electrically connected with the pre-holding area, controlling the first input end and the output end of the partition control module of the pre-holding area to be switched off, and controlling the second input end and the output end to be switched on; transmitting a control signal to the partition control signal line electrically connected with the pre-refreshing area, controlling the conduction between a first input end and an output end of the partition control module of the pre-refreshing area, and switching off between a second input end and the output end;
a scan signal is sequentially input to each of the scan lines and a corresponding data signal is input to each of the data lines.
The invention controls different pixels to refresh or maintain respectively by arranging an array substrate which comprises at least two subarea control signal lines and reference voltage signal lines, a pixel comprises a pixel circuit and a pixel electrode, the pixel circuit comprises a subarea control module, the subarea control module comprises a control end, a first input end, a second input end and an output end, the control end of the subarea control module is electrically connected with the subarea control signal line, the first input end of the subarea control module is electrically connected with the output end of an input module, the second input end of the subarea control module is electrically connected with the reference voltage signal line, the output end of the subarea control module is electrically connected with the pixel electrode of the pixel, the subarea control module is used for conducting or switching off the first input end and the output end and conducting or switching off the second input end and the output end according to the voltage of the control end, the problem of among the prior art all the whole refreshes of pixel have array substrate power consumption big is solved for the pixel that need not refresh on the array substrate keeps, and the pixel that keeps need not the data line and charges to the pixel electrode again, and the pixel that keeps does not receive the signal interference that other pixels that carry out the refresh produced, when effectively having reduced array substrate's power consumption, has promoted array substrate's formation display panel's display quality.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a pixel circuit according to an embodiment of the invention;
FIG. 3 is a circuit diagram of another pixel circuit according to an embodiment of the present invention;
fig. 4 is a circuit diagram of another pixel circuit according to an embodiment of the invention;
fig. 5 is a circuit diagram of another pixel circuit according to an embodiment of the invention;
fig. 6 is a circuit diagram of another pixel circuit according to an embodiment of the invention;
FIG. 7 is a circuit diagram of another pixel circuit according to an embodiment of the present invention;
fig. 8 is a circuit diagram of another pixel circuit according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of an electronic paper display panel according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 11 is a flowchart of a driving method of an electronic paper type display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. Referring to fig. 1, the array substrate 1 includes a plurality of scan lines (exemplarily including M scan lines in fig. 1, respectively denoted by Gate1, Gate2, Gate3, …, Gate M-1, Gate M), a plurality of data lines (exemplarily including P data lines in fig. 1, respectively denoted by SD1, SD2, SD3, …, SDP-1, SDP), and a plurality of pixels 10 defined by the plurality of scan lines and the plurality of data lines. The array substrate 1 further includes at least two divisional control signal lines (exemplarily including N divisional control signal lines, denoted by K1, …, KN, respectively, in fig. 1) and a reference voltage signal line REF, and the pixel 10 includes a pixel circuit and a pixel electrode.
Fig. 2 is a circuit diagram of a pixel circuit according to an embodiment of the invention. Referring to fig. 2, it should be noted that, in the pixel circuit 11 provided in the embodiment of the present invention, a scan line electrically connected to the pixel circuit 11 is denoted by a reference symbol Gate, a data line electrically connected to the pixel circuit 11 is denoted by a reference symbol SD, and a partition control signal line electrically connected to the pixel circuit 11 is denoted by a reference symbol K, in which the pixel circuit 11 may be the pixel circuit 11 of any one of the pixels 10 in fig. 1.
With continued reference to fig. 2, the pixel circuit 11 includes: an input module 200 and a zone control module 100. The input module 200 includes an input terminal 201, an output terminal 202, and a control terminal 203, the control terminal 203 of the input module 200 is electrically connected to the scan line Gate, the input terminal 201 of the input module 200 is electrically connected to the data line SD, and the input module 200 is configured to turn on or off the input terminal 201 and the output terminal 202 according to a voltage of the control terminal 203. The partition control module 100 includes a control terminal 103, a first input terminal 101, a second input terminal 102 and an output terminal 104, the control terminal 103 of the partition control module 100 is electrically connected to a partition control signal line K, the first input terminal 101 of the partition control module 100 is electrically connected to an output terminal 202 of the input module 200, the second input terminal 102 of the partition control module 100 is electrically connected to a reference voltage signal line REF, the output terminal 104 of the partition control module 100 is electrically connected to a pixel electrode of a pixel, and the partition control module 100 is configured to turn on or off between the first input terminal 101 and the output terminal 104 thereof and turn on or off between the second input terminal 102 and the output terminal 104 thereof according to a voltage of the control terminal 103 thereof.
The following describes the operation of the pixel circuit 11 provided in the present invention by taking the pixel circuit 11 in fig. 2 as an example. When the partition control signal line K connected to the partition control module 100 transmits a low voltage (i.e., a refresh signal), the low voltage controls conduction between the first input terminal 101 and the output terminal 104 of the partition control module 100. At this time, if the scan line Gate connected to the pixel circuit 11 transmits a low voltage (i.e., a scan signal), the input terminal 201 and the output terminal 202 of the input module 200 are controlled to be conducted by the low voltage. Since the output terminal 202 of the input module 200 is electrically connected to the first input terminal 101 of the partition control module 100, and the output terminal 104 of the partition control module 100 is electrically connected to the pixel electrode, a path is formed between the data line SD and the pixel electrode, and the voltage (i.e., the data signal) on the data line SD is written into the pixel electrode, thereby refreshing the pixel. When a high voltage (i.e., a hold signal) is transmitted on the partition control signal line K connected to the partition control module 100, the high voltage controls the partition control module 100 to be turned on between the second input terminal 102 and the output terminal 104 and to be turned off between the first input terminal 101 and the output terminal 104. Therefore, the data line SD is disconnected from the pixel electrode, the voltage on the data line SD cannot be written to the pixel electrode, the pixel electrode is connected to the reference voltage signal line REF, and the voltage on the reference voltage signal line REF is written to the pixel electrode, so that the voltage on the pixel electrode is maintained as the reference voltage, the pixel is maintained, and the pixel for maintaining is prevented from being interfered by the signal of the pixel for refreshing. With reference to fig. 1, in the embodiment of the present invention, at least two partition control signal lines and reference voltage signal lines REF are disposed on the array substrate 1, so that the pixels 10 electrically connected to the partition control signal lines K can be controlled to perform refreshing or maintaining respectively, that is, the pixels 10 electrically connected to different partition control signal lines K can perform refreshing simultaneously, maintaining simultaneously or performing refreshing partially, and performing maintaining partially, and the pixels 10 performing maintaining are not interfered by signals of other pixels 10 performing refreshing.
With continued reference to fig. 1 and fig. 2, the array substrate 1 according to the embodiment of the invention includes at least two partition control signal lines K and reference voltage signal lines REF, the pixel 10 includes a pixel circuit 11 and a pixel electrode, the pixel circuit 11 includes a partition control module 100, the partition control module 100 includes a control terminal 103, a first input terminal 101, a second input terminal 102 and an output terminal 104, the control terminal 103 of the partition control module 100 is electrically connected to one partition control signal line K, the first input terminal 101 of the partition control module 100 is electrically connected to an output terminal 202 of the input module 200, the second input terminal 102 of the partition control module 100 is electrically connected to the reference voltage signal line REF, the output terminal 101 of the partition control module 100 is electrically connected to the pixel electrode of the pixel 10, the partition control module 100 is configured to turn on or off between the first input terminal 101 and the output terminal 104 according to a voltage of the control terminal 103, and the second input terminal 102 and the output terminal 104 are turned on or off to control the pixels 10 electrically connected to the different partition control signal lines K to refresh or hold, respectively. Since the data line SD needs to charge the pixel electrode when the pixel 10 is refreshed, the more the refreshed pixels 10 are, the larger the power consumption of the array substrate 1 is. Compared with the scheme of integrally refreshing all pixels in the prior art, the embodiment of the invention controls the pixels 10 which do not need to be refreshed to be kept, the pixels 10 which do not need to be refreshed are charged to the pixel electrodes again, and the pixels 10 which do not need to be kept are not interfered by signals generated by other pixels 10 which do not need to be refreshed, so that the power consumption of the array substrate 1 is effectively reduced, and the display quality of the array substrate 1 is improved.
It should be noted that the refresh signal transmitted by the partition control signal line K may be low voltage or high voltage, and the scan signal transmitted by the scan line Gate may be low voltage or high voltage; similarly, the holding signal transmitted by the partition control signal line K may be a high voltage or a low voltage, and may be set as needed in practical application, which is not limited in the present invention. The partition control signal line K may be electrically connected to the partition control module 100 in one pixel circuit 11 to control one pixel 10 to refresh or maintain, or may be electrically connected to the partition control modules 100 of a plurality of pixel circuits 11 to control a plurality of pixels 10 to refresh or maintain simultaneously.
With reference to fig. 1, on the basis of the foregoing embodiment, optionally, the array substrate 1 further includes a display area 20 and a non-display area 30, the pixels 10 are disposed in the display area 20, the display area 20 includes at least two sub-display areas 21, each sub-display area 21 is correspondingly disposed with a partition control signal line, and the partition control signal line is electrically connected to a control terminal of each partition control module in the corresponding sub-display area 21. That is, in the embodiment of the present invention, the plurality of pixels 10 in the same sub-display area 21 are electrically connected to the same partition control signal line, and all the pixels 10 in the same sub-display area 21 are controlled to refresh or maintain, so as to control the display image of the sub-display area 21 to refresh or maintain. For example, when all the sub-display sections 21 are required to be refreshed, the divisional control signal lines K1 through KN each output a low voltage, and the voltage on the data line SD is normally written to the pixel electrode. When a certain sub-display area 21 needs to be refreshed, the output of the partition control signal line corresponding to the sub-display area 21 is low voltage, and the voltage on the data line in the sub-display area 21 is normally written into the pixel electrode. The output of the divisional control signal line corresponding to the other sub-display area 21 is a high voltage, and the voltage on the reference voltage signal line is written to the pixel electrode corresponding to the sub-display area 21. The embodiment of the invention controls the sub-display area 21 which does not need to be refreshed to be kept, and the voltage on the reference voltage signal line connected with the sub-display area 21 which does not need to be refreshed is written into the pixel electrode, so that the voltage of the pixel electrode is kept as the reference voltage, therefore, the pixel electrode does not need to be charged again by a data line in the sub-display area 21 which does not need to be kept, the power consumption of the array substrate 1 is effectively reduced, the sub-display area 21 which does not need to be refreshed causes signal interference to the sub-display area 21 which does not need to be kept, and the display quality of the sub-display area 21 is improved. In addition, in the embodiment of the invention, only one reference voltage signal line REF is added on the whole array substrate 1, only one partition control signal line is added in each sub-display area 21, the number of the reference voltage signal lines REF and the partition control signal lines is small compared with the number of the scanning lines and the data lines, and when wiring is carried out, a larger frame width is not required to be arranged to arrange the reference voltage signal lines REF and the partition control signal lines. In the prior art, a plurality of scanning lines and a plurality of data lines are respectively electrically connected with a plurality of driving Integrated Circuits (ICs), and the driving Integrated Circuits (ICs) provide signals for the scanning lines and the data lines. In summary, the embodiment of the present invention not only realizes controlling different sub-display regions 21 to perform refreshing and maintaining respectively, increases the control function of the array substrate 1, but also does not affect the frame size of the array substrate 1, and is beneficial to adapting to the development trend of the array substrate 1 with multiple functions, low energy consumption and narrow frame.
On the basis of the above embodiments, optionally, the partition control signal line and the scan line are disposed on the same layer, so that it is not necessary to additionally provide a film layer for the partition control signal line, the thickness of the array substrate 1 is reduced, the development trend of the array substrate 1 to be light and thin is adapted, and a mask process can be reduced in the manufacturing process of the array substrate 1, thereby simplifying the production process and saving the cost.
On the basis of the above embodiments, optionally, the array substrate 1 further includes a common voltage signal line, and the common voltage signal line is used for providing a common voltage to the common electrode. The absolute value of the difference between the reference voltage on the reference voltage signal line REF and the common voltage on the common voltage signal line is smaller than the absolute value of the difference between the voltage transmitted to the pixel electrode and the common voltage. When the pixel is kept, the voltage on the reference voltage signal line REF is written into the pixel electrode, so that the voltage of the pixel electrode is kept as the reference voltage, the signal interference of the pixel which is refreshed on the pixel which is kept is avoided, and the pixel display quality is improved.
Fig. 3 is a circuit diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 3, on the basis of the above embodiment, optionally, the reference voltage signal line REF is a common voltage signal line COM, that is, the second input terminal 102 of the partition control module 100 is electrically connected to the common voltage signal line COM. The working process of the pixel circuit 11 further includes, when a high voltage (i.e. a hold signal) is transmitted on the partition control signal line K connected to the partition control module 100, disconnecting the data line SD from the pixel electrode, disabling the voltage on the data line SD to be written into the pixel electrode, connecting the pixel electrode with the common voltage signal line COM, and simultaneously writing the voltage on the common voltage signal line COM into the pixel electrode and the common electrode, so that there is no voltage difference between the pixel electrode and the common electrode. The array substrate 1 can be suitable for electrophoretic display, the electrophoretic particles are arranged between the pixel electrode and the common electrode, the position of the electrophoretic particles moving is controlled by an electric field between the two electrodes (the pixel electrode and the common electrode), and the reflection condition of light is controlled by the position of the electrophoretic particles moving, so that the required display image is realized. The state of the electrophoretic particles is kept unchanged when no voltage difference exists between the two electrodes, so that the control display image is kept unchanged. Therefore, when the pixel 10 is kept, the voltage on the common voltage signal line COM is controlled to be written into the pixel electrode and the common electrode at the same time, so that the current state of the electrophoretic particles can be kept, the pixel 10 which is refreshed is prevented from causing signal interference to the pixel 10 which is kept, the display quality of the display panel formed by the array substrate 1 is improved, the common voltage signal line COM which is inherent to the display panel is used for providing the keeping voltage, a new circuit element is not needed to be arranged, and the size of a frame is not influenced.
It should be noted that, the partition control module 100 in each of the above embodiments may be implemented in various ways, and several of the implementations are described below, but the implementations are not limited thereto.
Fig. 4 is a circuit diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 4, on the basis of the above embodiments, optionally, the partition control module 100 further includes a first transistor T1 and a second transistor T2, a control terminal of the first transistor T1 and a control terminal of the second transistor T2 are both electrically connected to the partition control signal line K, a first terminal of the first transistor T1 and a first terminal of the second transistor T2 are both electrically connected to the pixel electrode of the pixel, a second terminal of the first transistor T1 is electrically connected to the first input terminal 101 of the partition control module 100, a second terminal of the second transistor T2 is electrically connected to the second input terminal 102 of the partition control module 100, and conductive channels of the first transistor T1 and the second transistor T2 are different. In fig. 4, the first transistor T1 is exemplarily shown to be an N-type transistor, the second transistor T2 is a P-type transistor, and in practical applications, the first transistor T1 may be further configured to be a P-type transistor, and the second transistor T2 is also configured to be an N-type transistor.
Taking fig. 4 as an example, the pixel circuit 11 operates when the partition control signal line K connected to the partition control module 100 transmits a low voltage (i.e., a refresh signal), and the low voltage controls the first transistor T1 to be turned on, thereby controlling conduction between the first input terminal 101 and the output terminal 104 of the partition control module 100. At this time, if the scan line Gate connected to the pixel circuit 11 transmits a low voltage (i.e., a scan signal), the input terminal 201 and the output terminal 202 of the input module 200 are controlled to be conducted by the low voltage. Since the output end 202 of the input module 200 is electrically connected to the first input end 101 of the partition control module 100, and the output end 202 of the partition control module 100 is electrically connected to the pixel electrode, a path is formed between the data line SD and the pixel electrode, and the voltage on the data line SD is written into the pixel electrode, thereby refreshing the pixel. When a high voltage (i.e., a hold signal) is transmitted on the zone control signal line K connected to the zone control module 100, the high voltage controls the second transistor T2 to be turned on, thereby controlling conduction between the second input terminal 102 and the output terminal 104 of the zone control module 100, and the high voltage controls the first transistor T1 to be turned off, thereby controlling turn-off between the first input terminal 101 and the output terminal 104 of the zone control module 100. Therefore, the data line SD is disconnected from the pixel electrode, the voltage on the data line SD stops being written into the pixel electrode, the pixel electrode is connected to the reference voltage signal line REF, and the voltage on the reference voltage signal line REF is written into the pixel electrode, thereby maintaining the pixel.
Fig. 5 is a circuit diagram of another pixel circuit according to an embodiment of the invention. Referring to fig. 5, alternatively, unlike the above embodiment, the partition control module 100 includes a third transistor T3 and a fourth transistor T4, and the partition control signal lines include a first partition signal line K 'and a second partition signal line K ″, where the level signals on the first partition signal line K' and the second partition signal line K ″ are inverted signals. The control terminal of the third transistor T3 is electrically connected to the first partition signal line K', the first terminal is electrically connected to the pixel electrode of the pixel, the second terminal is electrically connected to the first input terminal 101 of the partition control module 100, the control terminal of the fourth transistor T4 is electrically connected to the second partition signal line K ″, the first terminal is electrically connected to the pixel electrode of the pixel, the second terminal is electrically connected to the second input terminal 102 of the partition control module 100, and the conduction channels of the third transistor T3 and the fourth transistor T4 are the same. While the third transistor T3 and the fourth transistor T4 are exemplarily shown in fig. 5 as P-type transistors, in practical applications, the third transistor T3 and the fourth transistor T4 may also be provided as N-type transistors.
Taking fig. 5 as an example, the pixel circuit 11 works such that when the first partition signal line K 'connected to the partition control module 100 transmits a low voltage and the second partition signal line K ″ transmits a high voltage, the low voltage of the first partition signal line K' controls the third transistor T3 to be turned on, thereby controlling conduction between the first input terminal 101 and the output terminal 104 of the partition control module 100, and the high voltage of the second partition signal line K ″ controls the fourth transistor T4 to be turned off, thereby controlling conduction between the second input terminal 102 and the output terminal 104 of the partition control module 100. At this time, if the scan line Gate connected to the pixel circuit 11 transmits a low voltage (i.e., a scan signal), the input terminal 201 and the output terminal 202 of the input module 200 are controlled to be conducted by the low voltage. Since the output end 202 of the input module 200 is electrically connected to the first input end 101 of the partition control module 100, and the output end 104 of the partition control module 100 is electrically connected to the pixel electrode, a path is formed between the data line SD and the pixel electrode, and the voltage on the data line SD is written into the pixel electrode, thereby refreshing the pixel. On the contrary, the pixel electrode is conducted with the reference voltage signal line REF, and the voltage on the reference voltage signal line REF is written into the pixel electrode, so that the pixel is held.
With continued reference to fig. 4 and 5, based on the above embodiments, optionally, the input module 200 further includes a seventh transistor T7, a control terminal of the seventh transistor T7 is electrically connected to the scan line Gate, a first terminal of the seventh transistor T7 is electrically connected to the first input terminal 101 of the partition control module 100, and a second terminal of the seventh transistor T7 is electrically connected to the data line SD. In fig. 4 and 5, the seventh transistor T7 is exemplarily shown to be a P-type transistor, and in practical applications, the seventh transistor T7 may also be provided to be an N-type transistor. Taking fig. 4 and fig. 5 as an example, the operation process of the pixel circuit 11 is that, if the first input terminal 101 and the output terminal 104 of the partition control module 100 are in the on state, and the second input terminal 102 and the output terminal 104 are in the off state, that is, the pixel needs to be refreshed, when the scan line Gate connected to the pixel circuit 11 transmits a low voltage (i.e., a scan signal), the low voltage controls the seventh transistor T7 to be turned on, so that the input terminal 201 and the output terminal 202 of the input module 200 are turned on. The voltage on the data line SD is transmitted to the first input terminal 101 of the partition control module 100, and then written into the pixel electrode, so as to refresh the pixel.
Fig. 6 is a circuit diagram of another pixel circuit according to an embodiment of the present invention, and fig. 7 is a circuit diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 6 and 7, on the basis of the above embodiments, optionally, the input module 200 further includes n eighth transistors T8 (n is 2 exemplarily shown in fig. 6 and 7), the n eighth transistors T8 are connected in series between the data line SD and the first input terminal 101 of the partition control module 100, and the control terminals of the n eighth transistors T8 are all electrically connected to the scan line Gate, where n is an integer greater than 1. The eighth transistor T8 is exemplarily shown as a P-type transistor in fig. 6 and 7, and in practical applications, the eighth transistor T8 may also be provided as an N-type transistor. Since the n eighth transistors T8 are connected in series, when the scan line Gate connected to the pixel circuit 11 transmits a low voltage (i.e., a scan signal), the low voltage controls the n eighth transistors T8 to be simultaneously turned on, thereby turning on between the input terminal 201 and the output terminal 202 of the input block 200. In the embodiment of the present invention, the n eighth transistors T8 are serially connected between the data line SD and the first input terminal 101 of the partition control module 100, so that a voltage difference between the first terminal and the second terminal of each eighth transistor T8 is reduced, and after the eighth transistors are turned off, a leakage current generated is small, thereby reducing a leakage current of the pixel electrode, making an image display time longer, and facilitating a product (e.g., an electronic tag, etc.) which needs to keep a longer time for displaying an image to improve a display quality.
With reference to fig. 7, in particular, on the basis of the above embodiments, optionally, the partition control module 100 includes a third transistor T3 and a fourth transistor T4, both the third transistor T3 and the fourth transistor T4 are P-type transistors, and the input module 200 includes 2 eighth transistors T8, and the eighth transistor T8 is a P-type transistor, that is, both the transistors in the pixel circuit 11 are P-type transistors. In other embodiments, the transistors in the pixel circuit 11 may also be all N-type transistors. The array substrate 1 is provided with the pixel circuits 11, and the transistors are of the same type, so that the same doping process is favorably carried out on the semiconductor layers of the transistors in the manufacturing process of the array substrate 1, different doping processes do not need to be carried out on the P-type transistors and the N-type transistors respectively, the manufacturing process of the array substrate 1 is simplified, and the manufacturing cost of the array substrate 1 is saved.
Fig. 8 is a circuit diagram of another pixel circuit 11 according to an embodiment of the present invention. Referring to fig. 8, on the basis of the above embodiments, the partition control module 100 optionally includes m fifth transistors T5 connected in series and m sixth transistors T6 connected in series (fig. 8 exemplarily shows that m is 2 and n is 3). The m series-connected fifth transistors T5 are connected between the first input terminal 101 and the output terminal 104 of the partition control module 100, the control terminals of the m series-connected fifth transistors T5 are all electrically connected to the first partition signal line K', the m series-connected sixth transistors T6 are all electrically connected between the second input terminal 102 and the output terminal 104 of the partition control module 100, and the control terminals of the m series-connected sixth transistors T6 are all electrically connected to the second partition signal line K ″, where m is an integer greater than 1. The embodiment of the invention reduces the voltage difference between the first end and the second end of each fifth transistor T5 and each sixth transistor T6 by arranging the m fifth transistors T5 in series between the first input end 101 and the output end 104 of the partition control module 100 and arranging the m sixth transistors T6 in series between the second input end 102 and the output end 104 of the partition control module 100, thereby reducing the leakage current of the pixel electrode, enabling the image display time to be longer, and being beneficial to improving the display quality of products (such as electronic labels and the like) which need to keep the image for a longer time.
In the above embodiments, the more transistors in the partition control module 100 and the input module 200 are connected in series, the smaller the leakage current of the pixel electrode is, the longer the image display time is, and the more suitable the array substrate is for maintaining the image display for a longer time. The fewer transistors in the partition control module 100 and the input module 200 are connected in series, the faster the pixel electrode is charged, and the more suitable it is for the array substrate that needs to be refreshed frequently for displaying images or high pixel density (Pixels Per inc, PPI). In practical applications, the number of transistors in the partition control module 100 and the input module 200 in series may be set as desired.
In the above embodiments, the plurality of transistors in the input module 200 and the partition control module 100 may be configured as low-temperature polysilicon transistors as needed. The low-temperature polycrystalline silicon transistor can be set as a P-type transistor and also can be set as an N-type transistor, the electron mobility ratio of the low-temperature polycrystalline silicon transistor is higher, the attenuation degree is smaller, the charging speed is high, the faster refreshing speed of the array substrate 1 can be realized, and the user experience is improved.
The embodiment of the invention also provides the electronic paper type display panel. Fig. 9 is a schematic structural diagram of an electronic paper display panel according to an embodiment of the present invention. Referring to fig. 9, the electronic paper type display panel 4 includes an array substrate 1, an electrophoretic film 2 and a common electrode layer 3 provided in any embodiment of the present invention, and the electrophoretic film 2 is located between the array substrate 1 and the common electrode layer 3.
The working principle of the electronic paper type display panel is that the array substrate 1 is provided with the pixel electrode 19, the electrophoretic film 2 comprises a plurality of electrophoretic particles 29, the position of the electrophoretic particles 29 can be controlled by an electric field between the two electrodes (the pixel electrode 19 and the common electrode layer 3), and the reflection condition of light is controlled by the position of the electrophoretic particles 29, so that the electronic paper type display panel 4 can realize the required display image. The electronic paper type display panel 4 provided by the embodiment of the invention controls the voltage of the pixel electrode 19 through the array substrate, thereby controlling the electric field between the two electrodes. Specifically, the electronic paper display panel 4 is provided with an array substrate comprising at least two subarea control signal lines and reference voltage signal lines, the pixel comprises a pixel circuit and a pixel electrode, the pixel circuit comprises a subarea control module, the subarea control module comprises a control end, a first input end, a second input end and an output end, the control end of the subarea control module is electrically connected with a subarea control signal line, the first input end of the subarea control module is electrically connected with the output end of the input module, the second input end of the subarea control module is electrically connected with the reference voltage signal line, the output end of the subarea control module is electrically connected with the pixel electrode of the pixel, the subarea control module is used for switching on or off the first input end and the output end according to the voltage of the control end, and switching on or off the second input end and the output end of the pixel to control different pixels to refresh or maintain respectively. Since the pixel needs to be charged with the data line when refreshing, the more the pixels are refreshed, the greater the power consumption of the electronic paper display panel. Compared with the scheme of integrally refreshing all pixels in the prior art, the embodiment of the invention controls the pixels which do not need to be refreshed to be kept, the pixels which do not need to be refreshed are not required to be charged to the pixel electrode again, and the pixels which do not need to be kept are not interfered by signals generated by other pixels which do not need to be refreshed, so that the power consumption of the electronic paper type display panel is effectively reduced, and the display quality of the electronic paper type display panel is improved.
The embodiment of the invention also provides a display device. Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 10, the display device includes an electronic paper type display panel 4 provided in any embodiment of the present invention. The display device may be, for example, an electronic paper label, an electronic reader (e-book), an electronic price tag, an industrial instrument, a dynamic display billboard, or the like.
The display device provided by the embodiment of the invention is provided with an array substrate which comprises at least two subarea control signal lines and a reference voltage signal line, a pixel comprises a pixel circuit and a pixel electrode, the pixel circuit comprises a subarea control module, the subarea control module comprises a control end, a first input end, a second input end and an output end, the control end of the subarea control module is electrically connected with the subarea control signal line, the first input end of the subarea control module is electrically connected with the output end of an input module, the second input end of the subarea control module is electrically connected with the reference voltage signal line, the output end of the subarea control module is electrically connected with the pixel electrode of the pixel, the subarea control module is used for switching on or off the first input end and the output end according to the voltage of the, and switching on or off the second input end and the output end of the pixel to control different pixels to refresh or maintain respectively. Since the data lines are required to charge the pixel electrodes when the pixels are refreshed, the more pixels are refreshed, the greater the power consumption of the display device. Compared with the scheme of integrally refreshing all pixels in the prior art, the embodiment of the invention controls the pixels which do not need to be refreshed to be kept, the pixels which do not need to be refreshed are not required to be charged to the pixel electrode again, and the pixels which do not need to be kept are not interfered by signals generated by other pixels which do not need to be refreshed, so that the power consumption of the display device is effectively reduced, and the display quality of the display device is improved.
The embodiment of the invention also provides a driving method of the electronic paper type display panel provided by any embodiment of the invention. Fig. 11 is a flowchart of a driving method of an electronic paper display panel according to an embodiment of the present invention, and referring to fig. 11, the driving method of the electronic paper display panel includes the steps of:
s210, transmitting a control signal to a partition control signal line electrically connected with the pre-holding area, controlling the first input end and the output end of a partition control module of the pre-holding area to be switched off, and controlling the second input end and the output end to be switched on; and transmitting a control signal to a partition control signal line electrically connected with the pre-refreshing area, controlling the conduction between a first input end and an output end of a partition control module of the pre-refreshing area, and switching off between a second input end and the output end.
The electronic paper type display panel comprises a plurality of areas, wherein images displayed in some areas need to be kept, images displayed in some areas need to be refreshed, each area is provided with a corresponding partition control signal line, the partition control signal lines are electrically connected with a driving Integrated Circuit (IC), a partition controller is integrated in the driving Integrated Circuit (IC), and the partition controller provides signals for the partition control signal lines to control the images displayed in all the areas to be kept or refreshed.
S220, sequentially inputting a scan signal to each scan line and inputting a corresponding data signal to each data line.
The drive Integrated Circuit (IC) further comprises a scanning driver and a data driver, wherein the scanning line and the data line are respectively and electrically connected with the drive Integrated Circuit (IC), the scanning driver and the data driver respectively provide signals for the scanning line and the data line, for the pre-holding area, the data line and the pixel electrode are switched off, the reference voltage signal line and the pixel electrode are switched on, and the reference voltage signal is written into the pixel electrode; for the pre-refresh area, the data line and the pixel electrode are conducted, and the data signal is written into the pixel electrode to control each area to be kept or refreshed. The driving method of the electronic paper type display panel provided by the embodiment of the invention is characterized in that a control signal is transmitted to a partition control signal line electrically connected with a pre-holding area, the first input end and the output end of a partition control module of the pre-holding area are controlled to be turned off, and the second input end and the output end are connected, and a control signal is transmitted to a partition control signal line electrically connected with a pre-refreshing area, the first input end and the output end of a partition control module of the pre-refreshing area are controlled to be turned on, and the second input end and the output end are turned off, so that different pixels are controlled to be refreshed or held respectively. When the display area is refreshed, the data lines need to be charged to the pixel electrodes of the display area, and the more the display area is refreshed, the greater the power consumption of the electronic paper display panel is. Compared with the scheme of integrally refreshing all display areas in the prior art, the embodiment of the invention controls the display area which does not need to be refreshed to be kept, the display area which is kept does not need to be charged to the pixel electrode again by a data line, and the display area which is kept is not interfered by signals generated by other display areas which are refreshed, so that the power consumption of the electronic paper type display panel is effectively reduced, and the display quality of the electronic paper type display panel is improved.
With continued reference to fig. 11, on the basis of the foregoing embodiments, optionally, before transmitting the control signal to the partition control signal line electrically connected to the pre-holding area in step S210, the method further includes the steps of:
and S110, transmitting a control signal to each partition control signal line, controlling the partition control signal line to be electrically connected between a first input end and an output end of a partition control module, and controlling the partition control signal line to be electrically connected between a second input end and an output end to be switched off.
And S120, sequentially inputting scanning signals to the scanning lines and inputting corresponding data signals to the data lines to display the image, namely, controlling all display areas to be refreshed by the partition control signal lines to enable all the display areas to be refreshed to display the image so as to ensure normal display of the display panel.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (15)
1. The array substrate is characterized by comprising a plurality of scanning lines, a plurality of data lines and a plurality of pixels defined by the plurality of scanning lines and the plurality of data lines;
the array substrate further comprises at least two partition control signal lines and a reference voltage signal line, the pixel comprises a pixel circuit and a pixel electrode, and the pixel circuit comprises:
the input module comprises an input end, an output end and a control end; the control end of the input module is electrically connected with the scanning line, and the input end of the input module is electrically connected with the data line; the input module is used for switching on or switching off the input end and the output end of the input module according to the voltage of the control end of the input module;
the partition control module comprises a control end, a first input end, a second input end and an output end, the control end of the partition control module is electrically connected with the partition control signal line, the first input end of the partition control module is electrically connected with the output end of the input module, the second input end of the partition control module is electrically connected with the reference voltage signal line, the output end of the partition control module is electrically connected with the pixel electrode of the pixel, and the partition control module is used for conducting or switching off the first input end and the output end of the partition control module according to the voltage of the control end of the partition control module, and conducting or switching off the second input end and the output end of the partition control module.
2. The array substrate of claim 1, further comprising a display area and a non-display area, wherein the pixels are disposed in the display area, the display area comprises at least two sub-display areas, and each sub-display area is correspondingly disposed with one of the partition control signal lines; the partition control signal line is electrically connected with the control end of each partition control module in the corresponding sub-display area.
3. The array substrate of claim 1, wherein the partition control signal lines are disposed on the same layer as the scan lines.
4. The array substrate of claim 1, further comprising a common voltage signal line for providing a common voltage to the common electrode;
the absolute value of the voltage difference between the reference voltage on the reference voltage signal line and the common voltage on the common voltage signal line is smaller than the absolute value of the difference between the voltage transmitted to the pixel electrode and the common voltage.
5. The array substrate of claim 1, wherein the reference voltage signal line is a common voltage signal line.
6. The array substrate of claim 1, wherein the partition control module further comprises a first transistor and a second transistor;
a control end of the first transistor and a control end of the second transistor are electrically connected with the partition control signal line, a first end of the first transistor and a first end of the second transistor are electrically connected with a pixel electrode of the pixel, a second end of the first transistor is electrically connected with a first input end of the partition control module, and a second end of the second transistor is electrically connected with a second input end of the partition control module;
the first transistor and the second transistor have different conductive channels.
7. The array substrate of claim 1, wherein the partition control module comprises a third transistor and a fourth transistor; the partition control signal line comprises a first partition signal line and a second partition signal line, and level signals on the first partition signal line and the second partition signal line are mutually reverse signals;
the control end of the third transistor is electrically connected with the first partition signal line, the first end of the third transistor is electrically connected with the pixel electrode of the pixel, and the second end of the third transistor is electrically connected with the first input end of the partition control module;
a control end of the fourth transistor is electrically connected with the second partition signal line, a first end of the fourth transistor is electrically connected with a pixel electrode of the pixel, and a second end of the fourth transistor is electrically connected with a second input end of the partition control module;
the conduction channels of the third transistor and the fourth transistor are the same.
8. The array substrate of claim 7, wherein the partition control module comprises m fifth transistors connected in series and m sixth transistors connected in series; the m fifth transistors after being connected in series are connected between the first input end and the output end of the partition control module, and the control ends of the m fifth transistors after being connected in series are all electrically connected with the first partition signal line; the m sixth transistors after being connected in series are electrically connected between the second input end and the output end of the partition control module, the control ends of the m sixth transistors after being connected in series are all electrically connected with the second partition signal line, and m is an integer greater than 1.
9. The array substrate of claim 1, wherein the input module further comprises a seventh transistor, a control terminal of the seventh transistor is electrically connected to the scan line, a first terminal of the seventh transistor is electrically connected to the first input terminal of the partition control module, and a second terminal of the seventh transistor is electrically connected to the data line.
10. The array substrate of claim 9, wherein the input module further comprises n eighth transistors, the n eighth transistors are connected in series between the data line and the first input terminal of the partition control module, the control terminals of the n eighth transistors are all electrically connected to the scan line, and n is an integer greater than 1.
11. The array substrate of claim 1, wherein the input module and the partition control module further comprise a plurality of transistors, and wherein the transistors are low temperature polysilicon transistors.
12. An electronic paper type display panel comprising the array substrate according to any one of claims 1 to 11, an electrophoretic film, and a common electrode layer, wherein the electrophoretic film is located between the array substrate and the common electrode layer.
13. A display device characterized by comprising the electronic paper-type display panel according to claim 12.
14. A driving method of the electronic paper type display panel according to claim 12, comprising:
transmitting a control signal to the partition control signal line electrically connected with a pre-holding area, controlling the connection between a first input end of the partition control module and an output end of the partition control module of the pre-holding area, and controlling the connection between a second input end of the partition control module and the output end of the partition control module; transmitting a control signal to the partition control signal line electrically connected with the pre-refreshing area, controlling the conduction between a first input end of the partition control module and an output end of the partition control module in the pre-refreshing area, and switching off between a second input end of the partition control module and the output end of the partition control module;
a scan signal is sequentially input to each of the scan lines and a corresponding data signal is input to each of the data lines.
15. The method for driving an electronic paper type display panel according to claim 14, further comprising, before the transmitting the control signal to the partition control signal line electrically connected to the pre-holding area:
transmitting a control signal to each partition control signal line, controlling the connection between a first input end of the partition control module and an output end of the partition control module, which are electrically connected with the partition control signal line, and the connection between a second input end of the partition control module and the output end of the partition control module;
a scan signal is sequentially input to each of the scan lines and a corresponding data signal is input to each of the data lines.
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| CN109830217B (en) * | 2019-04-09 | 2021-04-09 | 上海中航光电子有限公司 | Liquid crystal display panel, display device and driving method |
| CN110060646B (en) * | 2019-05-08 | 2021-08-03 | 京东方科技集团股份有限公司 | Data latch circuit, pixel circuit, array substrate and liquid crystal display panel |
| CN115394266A (en) * | 2022-09-05 | 2022-11-25 | 鑫汭智造(北京)科技有限公司 | Non-spliced integrated liquid crystal display screen capable of achieving partition independent display |
| WO2024087402A1 (en) * | 2022-10-28 | 2024-05-02 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, and display apparatus |
| CN117975899B (en) * | 2024-01-29 | 2024-09-17 | 深圳今朝辉科技有限公司 | Data calling method and system of energy-saving LCM (liquid Crystal display module) |
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