CN108735733B - Silicon controlled electrostatic protector - Google Patents
Silicon controlled electrostatic protector Download PDFInfo
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- CN108735733B CN108735733B CN201810542367.4A CN201810542367A CN108735733B CN 108735733 B CN108735733 B CN 108735733B CN 201810542367 A CN201810542367 A CN 201810542367A CN 108735733 B CN108735733 B CN 108735733B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 26
- 239000010703 silicon Substances 0.000 title claims abstract description 26
- 230000001012 protector Effects 0.000 title description 2
- 238000002347 injection Methods 0.000 claims abstract description 93
- 239000007924 injection Substances 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thyristors (AREA)
Abstract
The invention provides a silicon controlled electrostatic protection device which comprises a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first N + injection region, a second N + injection region and a first P + injection region are arranged in the P well, and a third N + injection region, a second P + injection region and a third P + injection region are arranged in the N well; the first N + injection region, the third N + injection region and the second P + injection region are connected with an anode, and the second N + injection region, the first P + injection region and the third P + injection region are connected with a cathode; the second N + injection region, the P well and the N well form an NPN structure, and the P well, the N well and the third P + injection region form a PNP structure to form a silicon controlled rectifier structure; the first N + injection region and the P trap form a first reverse bias diode, and the third P + injection region and the N trap form a second reverse bias diode. The invention can solve the problem of overhigh trigger voltage.
Description
Technical Field
The invention relates to the technical field of integrated circuit electrostatic protection, in particular to a silicon controlled electrostatic protection device.
Background
LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices are widely used in power management chips, such as DC-DC converters, AC-DC converters, and the like. With the development of integrated circuits at high speed and high voltage, the weak electrostatic protection capability of the LDMOS device becomes a bottleneck limiting the development thereof. Therefore, how to improve the electrostatic discharge (ESD) capability of the LDMOS device becomes a hot point of research.
Silicon Controlled Rectifier (SCR) has strong electrostatic discharge capability by using the positive feedback effect of PNPN structure, and has received wide attention. Referring to fig. 4, the electrostatic discharge capability can be improved by embedding the SCR structure into the LDMOS device, but the triggering of the SCR device depends on the avalanche breakdown of the N-well and the P-well, so the trigger voltage thereof mainly depends on the PN junction doping concentration near the trigger point. The trigger voltage of the SCR device is higher due to the lower doping concentration of the N well and the P well. When the trigger voltage is higher than the breakdown voltage inside the device, the electrostatic protection function may not be performed.
Disclosure of Invention
In view of the above, there is a need to provide a thyristor electrostatic protection device to solve the problem of excessive trigger voltage.
A silicon controlled electrostatic protection device comprises a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first N + injection region, a second N + injection region and a first P + injection region are arranged in the P well, and a third N + injection region, a second P + injection region and a third P + injection region are arranged in the N well; the first N + injection region, the third N + injection region and the second P + injection region are connected with an anode, and the second N + injection region, the first P + injection region and the third P + injection region are connected with a cathode; the second N + injection region, the P well and the N well form an NPN structure, and the P well, the N well and the third P + injection region form a PNP structure to form a silicon controlled rectifier structure; the first N + injection region and the P trap form a first reverse bias diode, and the third P + injection region and the N trap form a second reverse bias diode.
According to the silicon controlled electrostatic protection device, the first reverse bias diode is a PN junction formed by the P trap and the first N + injection region, the second reverse bias diode is a PN junction formed by the third P + injection region and the N trap, and the first N + injection region is connected with the anode, and the third P + injection region is connected with the cathode, so that the first reverse bias diode and the second reverse bias diode are reverse bias diodes. The concentration of the injection region is higher than that of the trap, so that the avalanche breakdown voltages of the two reverse biased diodes are lower than that of a P trap/N trap junction, and the structure can effectively reduce the trigger voltage. In addition, an NPN structure is embedded in the P well, a PNP structure is embedded in the N well, a complementary CMOS structure is formed, and the whole structure does not contain a field oxide region, so that the device has strong electrostatic discharge capacity and the advantage of total dose radiation resistance, and can be used for electrostatic protection of a high-reliability integrated circuit.
In addition, the silicon controlled electrostatic protection device provided by the invention can also have the following additional technical characteristics:
furthermore, a first gate oxide layer is arranged between the first N + injection region and the second N + injection region, a first polysilicon gate covers the first gate oxide layer, and the first polysilicon gate is connected with the cathode.
Further, a second gate oxide layer is arranged between the second P + injection region and the third P + injection region, a second polysilicon gate covers the second gate oxide layer, and the second polysilicon gate is connected with the anode.
Furthermore, the deep N well is sequentially provided with the P well and the N well from left to right, the P well is sequentially provided with the first N + injection region, the second N + injection region and the first P + injection region from left to right, and the N well is sequentially provided with the third N + injection region, the second P + injection region and the third P + injection region from left to right.
Furthermore, the silicon controlled electrostatic protection device has three electrostatic discharge paths from the anode to the cathode, and the first path is the first N + injection region, the P-well and the first P + injection region; the second path is the third N + injection region, the N well and the third P + injection region; the third path is the second P + implantation region, the N-well, the P-well, the first N + implantation region, and the first P + implantation region.
Further, when the voltage of the anode is higher than a threshold value, the first reverse biased diode and the second reverse biased diode trigger before the P-well or the N-well, and free electron-hole pairs are generated in the N-well and the P-well, and electrostatic discharge is started through a path formed by the first reverse biased diode and a P-well resistor, and the second reverse biased diode and an N-well resistor.
Further, the substrate is a P-type silicon substrate.
Drawings
Fig. 1 is a schematic structural diagram of a thyristor electrostatic protection device according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of FIG. 1;
fig. 3 is a layout of a thyristor electrostatic protection device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a thyristor electrostatic protection device in the prior art.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are for illustrative purposes only and do not indicate or imply that the referenced device or element must be in a particular orientation, constructed or operated in a particular manner, and is not to be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 1 and fig. 2, a silicon controlled electrostatic protection device according to an embodiment of the present invention includes a substrate 100, and in this embodiment, the substrate 100 is a P-type silicon substrate.
The substrate 100 is provided with a deep N-well 200, and the deep N-well 200 is provided with a P-well 300 and an N-well 301. Specifically, in the present embodiment, the P-well 300 and the N-well 301 are sequentially disposed from left to right in the deep N-well 200.
A first N + implantation region 400, a second N + implantation region 401 and a first P + implantation region 402 are disposed in the P-well 300. Specifically, in the present embodiment, the first N + implantation region 400, the second N + implantation region 401, and the first P + implantation region 402 are sequentially disposed from left to right in the P well 300.
A third N + implantation region 403, a second P + implantation region 404, and a third P + implantation region 405 are disposed in the N-well 301. Specifically, in the present embodiment, the third N + implantation region 403, the second P + implantation region 404, and the third P + implantation region 405 are sequentially disposed from left to right in the N-well 301.
The first N + injection region 400, the third N + injection region 403, and the second P + injection region 404 are connected to an anode, and the second N + injection region 401, the first P + injection region 402, and the third P + injection region 405 are connected to a cathode.
The second N + injection region 401, the P-well 300, and the N-well 301 form an NPN structure, i.e., an NMOS transistor Qn, and the P-well 300, the N-well 301, and the third P + injection region 405 form a PNP structure, i.e., a PMOS transistor Qp, forming a complementary CMOS structure, thereby forming a thyristor structure. The grid electrodes and the source electrodes of the two MOS tubes are all in short circuit with the respective substrates. The structure avoids the use of a thicker field oxide layer, and therefore has stronger capability of resisting total dose radiation.
The first N + implant region 400 and the P-well 300 constitute a first reverse biased diode, Dpw; the third P + implant region 405 and the N-well 301 constitute a second reverse biased diode, Dnw.
Wherein Rpw1 and Rpw2 are both resistances of P well 300, and Rnw1 and Rnw2 are both resistances of P well 301.
When the voltage of the anode is higher than the threshold, the first reverse biased diode Dpw and the second reverse biased diode Dnw trigger before the P-well 300 or the N-well 301, and a large number of free electron-hole pairs are generated in the N-well 301 and the P-well 300, and start to perform electrostatic discharge through a path formed by the first reverse biased diode Dpw and the resistances Rpw1 and Rpw2 of the P-well 300, and the second reverse biased diode Dnw and the resistances Rnw1 and Rnw2 of the N-well 301, and trigger the thyristor structure, so as to further increase the discharge electrostatic current, and thus the structure has high ESD robustness.
In this embodiment, a first gate oxide layer 500 is disposed between the first N + injection region 400 and the second N + injection region 401, a first polysilicon gate 501 covers the first gate oxide layer 500, and the first polysilicon gate 501 is connected to a cathode.
A second gate oxide layer 502 is arranged between the second P + injection region 404 and the third P + injection region 405, a second polysilicon gate 503 covers the second gate oxide layer 502, and the second polysilicon gate 503 is connected with the anode.
From the anode to the cathode, the scr esd protection device has three electrostatic discharge paths, the first path is the first N + injection region 400, the P-well 300, and the first P + injection region 402; the second path is the third N + implantation region 403, the N well 301, and the third P + implantation region 405; the third path is the second P + implantation region 404, the N-well 301, the P-well 300, the first N + implantation region 400, and the first P + implantation region 402.
The layout form of the silicon controlled electrostatic protection device is shown in fig. 3, and compared with the layout of the conventional silicon controlled electrostatic protection device, the structure provided by the embodiment can reduce the injection efficiency of the emitter and improve the holding voltage.
In summary, according to the silicon controlled electrostatic protection device provided in this embodiment, the first reverse bias diode is a PN junction formed by the P well and the first N + injection region, and the second reverse bias diode is a PN junction formed by the third P + injection region and the N well, and since the first N + injection region is connected to the anode and the third P + injection region is connected to the cathode, they are both reverse bias diodes. The concentration of the injection region is higher than that of the trap, so that the avalanche breakdown voltages of the two reverse biased diodes are lower than that of a P trap/N trap junction, and the structure can effectively reduce the trigger voltage. In addition, an NPN structure is embedded in the P well, a PNP structure is embedded in the N well, a complementary CMOS structure is formed, and the whole structure does not contain a field oxide region, so that the device has strong electrostatic discharge capacity and the advantage of total dose radiation resistance, and can be used for electrostatic protection of a high-reliability integrated circuit.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A silicon controlled electrostatic protection device is characterized by comprising a substrate, wherein a deep N well is arranged on the substrate, a P well and an N well are arranged in the deep N well, a first N + injection region, a second N + injection region and a first P + injection region are arranged in the P well, and a third N + injection region, a second P + injection region and a third P + injection region are arranged in the N well; the first N + injection region, the third N + injection region and the second P + injection region are connected with an anode, and the second N + injection region, the first P + injection region and the third P + injection region are connected with a cathode; the second N + injection region, the P well and the N well form an NPN structure, and the P well, the N well and the third P + injection region form a PNP structure to form a silicon controlled rectifier structure; the first N + injection region and the P trap form a first reverse bias diode, and the third P + injection region and the N trap form a second reverse bias diode.
2. The silicon controlled electrostatic protection device according to claim 1, wherein a first gate oxide layer is disposed between the first N + injection region and the second N + injection region, and a first polysilicon gate is covered on the first gate oxide layer and connected to the cathode.
3. The silicon controlled electrostatic protection device according to claim 1, wherein a second gate oxide layer is disposed between the second P + implantation region and the third P + implantation region, and a second polysilicon gate covers the second gate oxide layer and is connected to the anode.
4. The silicon controlled electrostatic protection device according to claim 1, wherein the P-well and the N-well are sequentially disposed in the deep N-well from left to right, the first N + implantation region, the second N + implantation region and the first P + implantation region are sequentially disposed in the P-well from left to right, and the third N + implantation region, the second P + implantation region and the third P + implantation region are sequentially disposed in the N-well from left to right.
5. The silicon controlled electrostatic protection device according to any one of claims 1 to 4, wherein the silicon controlled electrostatic protection device has three electrostatic discharge paths from an anode to a cathode, a first path being the first N + injection region, the P well, the first P + injection region; the second path is the third N + injection region, the N well and the third P + injection region; the third path is the second P + implantation region, the N-well, the P-well, the first N + implantation region, and the first P + implantation region.
6. The SCR electrostatic protection device of any one of claims 1 to 4, wherein when the voltage of said anode is higher than a threshold value, said first reverse biased diode and said second reverse biased diode trigger before said P-well or said N-well, and at the same time, free electron-hole pairs are generated in said N-well and said P-well, and electrostatic discharge is initiated through a path formed by said first reverse biased diode and a P-well resistor, and said second reverse biased diode and an N-well resistor.
7. The silicon controlled electrostatic protection device as claimed in claim 1, wherein said substrate is a P-type silicon substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810542367.4A CN108735733B (en) | 2018-05-30 | 2018-05-30 | Silicon controlled electrostatic protector |
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| CN201810542367.4A CN108735733B (en) | 2018-05-30 | 2018-05-30 | Silicon controlled electrostatic protector |
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| CN108735733B true CN108735733B (en) | 2021-04-13 |
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| EP4020551A4 (en) | 2020-05-12 | 2022-12-28 | Changxin Memory Technologies, Inc. | Electrostatic protection circuit |
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| US6448123B1 (en) * | 2001-02-20 | 2002-09-10 | Taiwan Semiconductor Manufacturing Company | Low capacitance ESD protection device |
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2018
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| US5182220A (en) * | 1992-04-02 | 1993-01-26 | United Microelectronics Corporation | CMOS on-chip ESD protection circuit and semiconductor structure |
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