CN108695396B - Diode and manufacturing method thereof - Google Patents
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- CN108695396B CN108695396B CN201810553861.0A CN201810553861A CN108695396B CN 108695396 B CN108695396 B CN 108695396B CN 201810553861 A CN201810553861 A CN 201810553861A CN 108695396 B CN108695396 B CN 108695396B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66212—Schottky diodes
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Abstract
A diode device and a manufacturing method thereof belong to the technical field of power semiconductor devices. The cell structure of the device comprises a metal cathode, an N + substrate and an N-epitaxial layer, wherein two sides of the top layer of the N-epitaxial layer are provided with groove structures, and each groove structure comprises a P-type semiconductor region and a hetero-semiconductor from bottom to top; the top layer of the N-epitaxial layer is also provided with a P-type Schottky barrier contact region, the P-type Schottky barrier contact region, part of the N-epitaxial layer and the hetero-semiconductor are in contact through the dielectric layer on the side wall of the groove, and the hetero-semiconductor, the dielectric layer, the P-type silicon carbide ohmic contact region and the N-epitaxial layer form a super-barrier structure. The invention reduces the forward starting voltage of the device, remarkably improves the rectification efficiency of the diode, and is beneficial to reducing the on-state loss of the device; meanwhile, the blocking voltage capability of the device is improved, the mirror image force induced barrier lowering effect is overcome, the leakage is lower, the safe working area is larger, and the reliability of the device is improved. In addition, the manufacturing method of the device provided by the invention is compatible with the existing manufacturing process.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a diode and a manufacturing method thereof.
Background
Since the 21 st century of human history, fossil energy has been the dominant source of energy for world energy production and consumption. Combined with the development and utilization of current energy resources, fossil energy remains the energy basis for human survival and development for a long period of time. The fossil energy will be exhausted and environmental pollution will be caused easily, so that the environmental and sustainable development problems caused by the exhaustion of the fossil energy are the problems that human beings must face. Electric energy is one of the main forms of energy available to human beings, and the improvement of the use efficiency of the electric energy is an important solution to the world energy problem. The electric power system is a necessary way for human beings to utilize electric energy and improve the use efficiency of the electric energy, and the electric power system reflects the modernization degree of the electric power system on the aspects of the transportation, management and use efficiency of the electric energy. Specifically, the power system mainly adjusts, measures, controls, protects, schedules, communicates, and the like, in the process of generating electric energy, and in the process, the power semiconductor device plays a central role. The performance of the power semiconductor device determines the performance of the power system. To a certain extent, the performance of the power semiconductor device is good and bad, and the energy conservation and emission reduction benefits are concerned.
The most commonly used power diodes today belong to the Schottky Barrier Diode (SBD) and PIN diodes. PIN diodes belong to bipolar devices, have the advantage of high breakdown voltage and low reverse current, with a reverse recovery process due to the injection of minority carriers. The SBD belongs to a multi-sub device or a single-pole device, the reverse recovery time of the SBD is shorter than that of a fast recovery diode or an ultra-fast recovery diode, and no obvious voltage overshoot is generated in the forward recovery process, so that the SBD is an ideal device for a high-frequency circuit and an ultra-high-speed switching circuit. The conventional SBD device structure is generally a vertical structure, and the cell structure thereof is shown in fig. 1. The device structure comprises an ohmic contact cathode, an N + substrate, an N-drift region and a Schottky contact anode from bottom to top in sequence. The basic operating principle of the SBD device is as follows: when the anode metal is contacted with the semiconductor, Schottky contact is formed, and the unidirectional conduction of the SBD is realized. The Schottky contact and the ohmic contact of the structure are realized through the doping concentration of materials, and a semiconductor in contact with an ohmic electrode is heavily doped. When forward bias is applied, the barrier height is reduced, electrons flow from the semiconductor to the metal easily, and a current flows from the metal to the semiconductor; when the device is reversely biased, the barrier height is increased, electrons hardly pass through the high barrier, and therefore the purpose of reverse cut-off is achieved, and therefore the unidirectional conductivity of the device is achieved. Compared with PIN diodes, SBD devices have the advantages of good reverse recovery characteristics, low turn-on voltage drop, high forward-on current, high thermal conductivity, and the like, and thus have received certain attention in the power device market. However, when the SBD is applied in the reverse direction, the inherent "image force" inevitably lowers the schottky barrier height, i.e. lowers the "threshold" for blocking the movement of photons, which causes the SBD to have the disadvantages of large reverse leakage and low breakdown voltage.
Meanwhile, with the gradual maturity of power semiconductor technology, the characteristics of silicon-based power devices gradually approach the theoretical limit. Researchers strive to find better parameters in a narrow optimization space of a silicon-based power device and pay attention to excellent material characteristics of third-generation wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and the like in the fields of high power, high frequency, high temperature resistance, radiation resistance and the like. The silicon carbide power diode device is called a green energy device of a new energy revolution by the industry because the silicon carbide which is a wide-bandgap semiconductor material has a remarkable effect of reducing power loss. Besides, the silicon carbide material has many attractive properties, such as 10 times of the critical breakdown electric field strength of the silicon material, high thermal conductivity, large forbidden band width, high electron saturation drift velocity, etc., and these performance advantages make the silicon carbide material a hot research point for power semiconductor devices internationally. Silicon carbide schottky barrier diode (SiC SBD) devices have grown to maturity and exhibit the drawbacks of wide bandgap semiconductor materials: the wide bandgap of the material results in a large knee voltage, which affects the rectification efficiency in the forward application of the SBD, and the on-state characteristics of the device are reduced accordingly.
In summary, the present shortages of the schottky barrier diode are a barrier widely popularized in the market, and it is necessary to solve the above technical problems if the potential of the schottky barrier diode in the market is to be fully developed.
Disclosure of Invention
In view of the above, the present invention aims to: aiming at the problems of larger reverse leakage, poor voltage blocking capability and the like of a Schottky barrier diode in the prior art, the diode structure which can improve the voltage blocking capability, reduce the reverse leakage level and lower forward conduction voltage is provided, and the diode structure is suitable for various semiconductor materials; meanwhile, the invention also provides a preparation method of the diode device.
On one hand, the invention provides a diode device, the cellular structure of which comprises a metal cathode 4, an N + wide bandgap semiconductor substrate 3, an N-wide bandgap semiconductor epitaxial layer 2 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer 2 are provided with groove structures, each groove structure comprises a P + wide bandgap semiconductor region 6 arranged at the bottom of each groove and a narrow bandgap semiconductor 5 arranged at the top of each groove, and the P + wide bandgap semiconductor region 6 is in direct contact with the narrow bandgap semiconductor 5; a P-type wide bandgap semiconductor Schottky contact region 8 is also arranged between the groove structures at the two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer 2; the method is characterized in that: the P-type wide bandgap semiconductor Schottky contact region 8 and part of the N-wide bandgap semiconductor epitaxial layer 2 are in contact with the narrow bandgap semiconductor 5 through the dielectric layer 7 on the side wall of the groove; the narrow bandgap semiconductor 5, the dielectric layer 7 and the P-type wide bandgap semiconductor Schottky contact region 8 are in contact with the metal anode 1 above the narrow bandgap semiconductor; wherein: the narrow bandgap semiconductor 5, the dielectric layer 7, the P type wide bandgap semiconductor Schottky contact region 8 and the N-wide bandgap semiconductor epitaxial layer 2 form a super barrier structure, and the narrow bandgap semiconductor 5 and the N-wide bandgap semiconductor epitaxial layer 3 form a heterojunction at a contact interface.
Further, the P + wide bandgap semiconductor region 6 may be shorted to the ground or may be arranged in a floating manner.
Further, a P-type wide bandgap semiconductor body region 9 is further arranged below the P-type wide bandgap semiconductor schottky contact region 8 and between the N-wide bandgap semiconductor epitaxial layer 2 and the dielectric layer 7.
Further, the width of the P + wide bandgap semiconductor region 6 is larger than the width of the trench in the present invention.
Furthermore, the narrow bandgap semiconductor 5 of the invention further comprises a dielectric layer 7 which divides the narrow bandgap semiconductor 5 into two parts independent of each other, the narrow bandgap semiconductor 5 above the dielectric layer 7 is called a first narrow bandgap semiconductor, the narrow bandgap semiconductor 5 below the dielectric layer 7 is called a second narrow bandgap semiconductor, and the second narrow bandgap semiconductor is shorted with the metal anode 1 through ohmic contact.
Furthermore, in the invention, the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2 form a super junction structure; according to the common general knowledge of those skilled in the art, the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2 satisfy the requirement of Qp ═ Qn.
Preferably, when the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2 form a super junction structure, the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer 2 is higher than the doping concentration below the top layer.
Preferably, when the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2 form a super junction structure, the doping concentration of the top layer of the P + wide bandgap semiconductor region 6 is higher than the doping concentration below the top layer.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor is made of a silicon material, the narrow bandgap semiconductor may be polysilicon or monocrystalline silicon, the polycrystalline silicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
On the other hand, the invention provides a manufacturing method of a diode device, which is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate 3 and an N-wide bandgap semiconductor epitaxial layer 2;
step 2: forming a P-type wide bandgap semiconductor Schottky contact region 8 positioned above the N-wide bandgap semiconductor epitaxial layer 2 through an ion implantation process or an epitaxial process;
and step 3: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer 2 through a groove etching process;
and 4, step 4: depositing a P-type wide bandgap semiconductor material at the bottom of the groove or injecting a P-type wide bandgap semiconductor material below the groove by a deposition and etching process or an ion injection process to form a P + wide bandgap semiconductor region 6;
and 5: depositing a narrow bandgap semiconductor material on the upper surface of the P + wide bandgap semiconductor region 6 through deposition and etching processes, removing redundant narrow bandgap semiconductor material through etching, and reserving a part of narrow bandgap semiconductor material at the bottom of the groove to be used as a second narrow bandgap semiconductor;
step 6: forming a dielectric layer 7 on the surface and the side wall of the narrow bandgap semiconductor through a dry oxygen oxidation or deposition process;
and 7: continuously depositing a narrow-bandgap semiconductor material on the dielectric layer 7 through a deposition and etching process, and removing redundant narrow-bandgap semiconductor material through etching to form a first narrow-bandgap semiconductor positioned on the dielectric layer 7, wherein the first narrow-bandgap semiconductor and the second narrow-bandgap semiconductor form a narrow-bandgap semiconductor 6 separated by the dielectric layer 7;
and 8: through deposition, photoetching and etching processes, a metal anode 1 is formed on the upper surfaces of the narrow bandgap semiconductor 5, the dielectric layer 7 and the P-type wide bandgap semiconductor Schottky contact region 8, and a metal cathode 4 is formed on the back surface of the turnover device, so that the manufacture of the device is completed.
According to the embodiment of the present invention, the material of the wide bandgap semiconductor is silicon carbide, and the material of the narrow bandgap semiconductor is silicon material, and according to the common general knowledge in the art, other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided by the present invention, and the present invention is not limited thereto.
Further, when the narrow bandgap semiconductor deposited in step 5 and step 7 is silicon, the semiconductor may be polysilicon or monocrystalline silicon, the polysilicon may be P-type polysilicon or N-type polysilicon, and the monocrystalline silicon may be P-type monocrystalline silicon or N-type monocrystalline silicon.
Further, when the narrow bandgap semiconductor is polysilicon, the operations of forming the dielectric layer 7 and the polysilicon in steps 6 and 7 may be replaced by the following operations: silicon nitride is deposited through the bottom of the trench and then thermal oxidation is performed. And then, etching the silicon nitride by using hot phosphoric acid, and finally forming the polycrystalline silicon in the groove by deposition and etching processes.
Further, the step 7 further comprises the following steps: and selectively removing the dielectric layer 7 on the surface of the narrow bandgap semiconductor through an etching process, so that the continuous narrow bandgap semiconductor 5 is formed in the subsequent manufacturing.
Further, the step 4 further includes, after depositing the P + wide bandgap semiconductor region 6, making the width of the P + wide bandgap semiconductor region 6 larger than the width of the trench through a thermal diffusion process.
Further, after the second narrow bandgap semiconductor is formed in the step 5, a metal anode region 1a is formed between the second narrow bandgap semiconductor and the P + wide bandgap semiconductor region 6 by adding trench etching, depositing metal, and removing excess metal by etching.
Further, the operations of forming the trench and the P + wide bandgap semiconductor region 6 in the steps 3 and 4 may be replaced by the following operations: the depth of the groove etching is deepened through multiple times of epitaxy, thermal diffusion and etching, so that the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2 are distributed at intervals, and a super junction structure is formed by controlling the width and the doping concentration of the P + wide bandgap semiconductor region 6 and the N-wide bandgap semiconductor epitaxial layer 2.
Further, when the super junction structure is formed, after the trench is formed in step 3, forming a heavily doped N-wide bandgap semiconductor epitaxial layer 2b on top of the N-wide bandgap semiconductor epitaxial layer 2 by an ion implantation process.
Further, in the forming of the super junction structure, after the forming of the P + wide bandgap semiconductor region 6 in the step 4, forming a P + + wide bandgap semiconductor region 6b on top of the P + wide bandgap semiconductor region 6 by an ion implantation process is further included.
According to the invention, by reasonably improving the device structure, the narrow-bandgap semiconductor, the dielectric layer, the Schottky contact region and the epitaxial layer form a super-barrier structure, and the narrow-bandgap semiconductor in the super-barrier structure and the epitaxial layer form a heterojunction at a contact interface. Through the integration of the functional regions, the Schottky barrier diode device can solve the problems of weak blocking voltage capability, large reverse leakage, large forward starting voltage and the like existing in the conventional Schottky barrier diode device. It should be noted that the device structure proposed by the present invention is applicable not only to N-channel devices, but also to P-channel devices.
The principles of the present invention will be explained in detail below by selecting a diode device formed by using silicon carbide as a wide bandgap semiconductor and polysilicon as a narrow bandgap semiconductor, and those skilled in the art can easily obtain the principles of the device by combining other wide and narrow bandgap semiconductor materials according to the following disclosure.
When the anode of the structure is applied with forward bias voltage, the Schottky junction is in a reverse bias state, and the depletion layer is expanded in the P-type wide bandgap semiconductor Schottky contact region. When the surplus minority carriers exist in the depletion layer of the P-type wide bandgap semiconductor Schottky contact region, the surplus minority carriers are extracted by the anode. In the diode device provided by the invention, the polycrystalline silicon, the dielectric layer and the Schottky contact region form a metal (M) -insulator (I) -semiconductor (S) structure (hereinafter referred to as MIS structure), and parameters such as the doping concentration of the polycrystalline silicon, the thickness and the charge number of the dielectric layer, the doping concentration of the P-type wide bandgap semiconductor Schottky contact region and the like are adjusted through process control, so that the threshold voltage of the MIS structure is smaller than 0.4V. When the voltage applied on the metal anode is close to 0.4V, a small part of current of carriers (electrons) flows through the N-wide band gap semiconductor epitaxial layer and the P-type wide band gap semiconductor Schottky contact region due to the existence of the current of the sub-threshold region of the MIS structure. The carrier current causes a voltage drop across the P-type wide bandgap semiconductor schottky contact. Meanwhile, at the other end of the dielectric layer, because the Si/SiC heterojunction is larger than the forward starting voltage of 0.4V, no current flows in the region where the polycrystalline silicon is located, namely the potential of the region where the polycrystalline silicon is located is the same everywhere. The potential on the two sides of the dielectric layer is gradually increased from top to bottom along the vertical direction of the device, and the difference ensures that the voltage on the metal anode does not need to be added to 0.4V (namely the gate voltage of the super-barrier structure), minority carriers can be accumulated in the P-type wide bandgap semiconductor Schottky contact area, and the minority carriers can be quickly swept away by the anode, namely the on-state of the device. From the above, the change of the energy band by the super barrier structure causes the knee voltage of the rectifying structure to drop below 0.4V, and the specific drop value can be adjusted by changing the parameter. Generally speaking, the knee voltage of the traditional silicon carbide Schottky diode is about 1V, so the turn-on voltage of the device structure provided by the invention is lower than that of the traditional Schottky barrier diode with the same specification, and the device structure provided by the invention has absolute advantages in low-voltage application, and meanwhile, the device has the characteristic of large current density under normal working bias through structural improvement.
The diode device provided by the invention also introduces the heterojunction while forming the super barrier structure, and the existence of the heterojunction increases the multi-sub-current level of the device, so that the device has lower voltage drop under the same conduction current level; furthermore, under larger anode current, the PN junction formed by the P-type wide bandgap semiconductor Schottky contact region and the N-wide bandgap semiconductor epitaxial layer can be conducted, so that the forward conduction current density of the device is increased by the current branch, and the method has important significance for reducing the on-state loss of the device; in addition, a PN junction formed by the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer has high voltage blocking capability on one hand, so that the defect of low withstand voltage capability of the traditional Schottky diode can be overcome, and high reverse withstand voltage can be borne on the other hand, so that the PN junction has high barrier potential and does not have 'mirror force' at the same time of reverse bias. Therefore, compared with the conventional Schottky diode device, the Schottky diode device provided by the invention has lower reverse leakage. And a P + wide bandgap semiconductor region and an N-wide bandgap semiconductor epitaxial layer are further formed to form a super junction structure, so that the voltage blocking capability of the device can be obviously improved, and the better compromise characteristic of forward voltage drop and breakdown voltage is obtained.
The invention has the beneficial effects that:
compared with the traditional wide bandgap Schottky diode device, the diode device provided by the invention has lower forward starting voltage, the rectification efficiency of the diode is obviously improved, the on-state loss of the device is reduced, and the energy resource is saved.
The P + wide bandgap semiconductor region introduced by the diode device can well protect the super barrier structure and the heterojunction structure in a blocking state, and has higher voltage blocking capability compared with the traditional device.
And thirdly, the withstand voltage of the diode device provided by the invention is born by a PN junction formed by the P + wide bandgap semiconductor region and the N-wide bandgap semiconductor epitaxial layer, so that the diode device has higher potential barrier in a blocking state, and meanwhile, the mirror image force induced potential barrier lowering effect does not exist, thereby having lower electric leakage, larger safe working area and improving the reliability of the device.
And fourthly, the diode device provided by the invention adopts a super junction structure, so that the voltage blocking capability of the device is obviously improved, and further, a better compromise characteristic is obtained between the forward voltage drop and the breakdown voltage.
Drawings
Fig. 1 is a schematic diagram of a cell structure of a conventional schottky barrier diode device;
fig. 2 is a schematic diagram of a cell structure of a diode device provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a cell structure of a diode device provided in embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a cell structure of a diode device provided in embodiment 3 of the present invention;
fig. 5 is a schematic diagram of a cell structure of a diode device provided in embodiment 4 of the present invention;
fig. 6 is a schematic diagram of a cell structure of a diode device provided in embodiment 5 of the present invention;
fig. 7 is a schematic diagram of a cell structure of a diode device provided in embodiment 6 of the present invention;
fig. 8 is a functional region division schematic diagram of a diode device provided in embodiment 1 of the present invention;
fig. 9 is a schematic diagram of the potential distribution on both sides of the dielectric layer in the diode device provided in embodiment 1 of the present invention;
fig. 10 is an I-V characteristic curve of each functional region in the diode device provided in embodiment 1 of the present invention;
fig. 11 is an I-V characteristic curve of a diode device provided in embodiment 1 of the present invention;
fig. 12 is a schematic structural view of a silicon carbide substrate and a silicon carbide epitaxial layer provided in example 1 of the present invention;
fig. 13 is a schematic structural diagram of forming a P-type silicon carbide schottky contact region according to embodiment 1 of the present invention;
fig. 14 is a schematic structural view of forming a trench according to embodiment 1 of the present invention;
fig. 15 is a schematic structural view of forming a P + silicon carbide region provided in embodiment 1 of the present invention;
fig. 16 is a schematic structural view of the second polysilicon provided in embodiment 1 of the present invention;
fig. 17 is a schematic structural diagram of forming a dielectric layer provided in embodiment 1 of the present invention;
FIG. 18 is a schematic structural diagram after a dielectric layer on the surface of a second polysilicon is selectively etched according to embodiment 1 of the present invention;
fig. 19 is a schematic structural diagram of forming first polysilicon according to embodiment 1 of the present invention;
fig. 20 is a schematic structural diagram of forming a metal anode and a metal cathode provided in embodiment 1 of the present invention.
The numbering in the figures means the following:
1 is a metal anode, 2 is an N-silicon carbide epitaxial layer, 2a is a lightly doped N-silicon carbide epitaxial layer, 2b is a heavily doped N-silicon carbide epitaxial layer, 3 is an N + silicon carbide substrate, 4 is a metal cathode, 5 is polysilicon, 6 is a P + silicon carbide region, 6a is a lightly doped P + silicon carbide region, 6b is a heavily doped P + silicon carbide region, 7 is a dielectric layer, 8 is a P-type silicon carbide Schottky contact region, and 9 is a P-type silicon carbide body region; a is a super barrier structure; b is a heterojunction.
Detailed Description
The structure and fabrication method of the device are described in detail below with reference to the drawings, so that those skilled in the art can clearly understand the technical scheme and principle of the present invention. The specific examples are provided for illustration only and are not intended to limit the scope of the invention.
Example 1:
a diode device, the cellular structure of which is shown in figure 2, comprises a metal cathode 4, an N + wide bandgap semiconductor substrate 3, an N-wide bandgap semiconductor epitaxial layer 2 and a metal anode 1 which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer 2 are provided with groove structures, each groove structure comprises a P + wide bandgap semiconductor region 6 arranged at the bottom of each groove and a narrow bandgap semiconductor 5 arranged at the top of each groove, and the P + wide bandgap semiconductor region 6 is in direct contact with the narrow bandgap semiconductor 5; a P-type wide bandgap semiconductor Schottky contact region 8 is also arranged between the groove structures at the two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer 2; the method is characterized in that: the P-type wide bandgap semiconductor Schottky contact region 8 and part of the N-wide bandgap semiconductor epitaxial layer 2 are in contact with the narrow bandgap semiconductor 5 through the dielectric layer 7 on the side wall of the groove; the narrow bandgap semiconductor 5, the dielectric layer 7 and the P-type wide bandgap semiconductor Schottky contact region 8 are in contact with the metal anode 1 above the narrow bandgap semiconductor; wherein: the narrow bandgap semiconductor 5, the dielectric layer 7, the P type wide bandgap semiconductor Schottky contact region 8 and the N-wide bandgap semiconductor epitaxial layer 2 form a super barrier structure, and the narrow bandgap semiconductor 5 and the N-wide bandgap semiconductor epitaxial layer 3 form a heterojunction at a contact interface.
In this embodiment, the wide bandgap semiconductor is silicon carbide, the narrow bandgap semiconductor is polysilicon, and parameters of each structure are given below by taking a 1200V N channel diode device as an example:
the thickness of the metal anode 1 and the metal cathode 4 is 0.5-2 μm, and the width is 0.5-2 μm; the doping concentration of the N + silicon carbide substrate 3 is 1e 18-9 e18/cm3The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide epitaxial layer 2 is 2e 15-8 e15/cm3The thickness is 5-8 μm, and the width is 0.5-2 μm; the P + SiC region 6 has a thickness of about 0.8 to 1.1 μm and a doping concentration of about 1e19 to 7e19/cm3The width is about 0.3-0.5 μm; the width of the polysilicon 5 is about 0.3-0.5 μm, and the thickness is about 0.8-1.6 μm; the thickness of the dielectric layer 7 is about 10 nm-50 nm; the P-type silicon carbide Schottky contact region 8 has a thickness of about 0.1-0.2 μm, a width of about 0.2-0.4 μm, and a doping concentration of about 1e 18-1 e19/cm3。
According to the invention, the device structure is reasonably improved to form four functional regions of a super-barrier structure, a Schottky barrier contact, a heterojunction and a PN junction, so that the comprehensive performance of the device is obviously superior to that of the traditional Schottky barrier diode.
The principles and features of the present invention will be described in detail below with reference to specific embodiments:
in this embodiment, an N-channel diode device formed by using silicon carbide as a wide bandgap semiconductor material and polysilicon as a narrow bandgap semiconductor material is taken as an example to explain the principle and characteristics of the present invention in detail, and a person skilled in the art can derive the principle of a P-channel diode device and the principle of a diode device formed by combining the remaining wide and narrow bandgap semiconductor materials according to the following disclosure:
the Schottky barrier diode aims at the problems of large forward opening voltage, weak voltage blocking capability, large reverse leakage and the like of the traditional Schottky barrier diode, and reasonably improves the structure of the device to optimize the performance. For convenience of explanation of the principle of the present invention, two functional regions to be mentioned later and position points a1, a2, b1 and b2 on both sides of the dielectric layer 8 are respectively labeled as shown in fig. 8.
When the anode of the structure is applied with a forward bias voltage, the Schottky junction is in a reverse bias state. When there is excess minority carriers in the P-type silicon carbide schottky contact region 8, this portion of minority carriers will be extracted by the anode. In the diode device provided by the invention, the polycrystalline silicon 5, the dielectric layer 7 and the P-type silicon carbide Schottky contact region 8 form a metal M-insulator I-semiconductor S structure which is hereinafter referred to as MIS structure, and parameters such as the doping concentration of the polycrystalline silicon 5, the thickness and the charge number of the dielectric layer 7, the doping concentration of the P-type silicon carbide Schottky contact region 8 and the like are adjusted through process control, so that the threshold voltage of the MIS structure is smaller than 0.4V. When the voltage applied to the metal anode 1 is close to 0.4V, a small part of the current of carriers flows through the N-silicon carbide epitaxial layer 2 and the P-type silicon carbide Schottky contact region 8 due to the existence of the current of the sub-threshold region of the MIS structure. This carrier current causes a voltage drop across the P-type silicon carbide schottky contact 8. Meanwhile, at the other end of the dielectric layer 7, since the Si/SiC heterojunction is greater than the forward-direction turn-on voltage of 0.4V, it can be considered that no current flows in the region where the polycrystalline silicon 5 is located, i.e., the potential of the region where the polycrystalline silicon 5 is located is the same everywhere. Fig. 9 is a graph showing potential distribution on both sides of the dielectric layer 7, in which a1 and a2 have almost no potential difference, and the potential difference increases from top to bottom in the vertical direction from point a to point b. This difference makes the voltage on the metal anode 1 not need to be applied to 0.4V (i.e. the gate voltage of the super barrier structure), and there is a minority carrier accumulation in the P-type silicon carbide schottky contact region 8, which will be swept away by the anode rapidly, i.e. the on-state of the device. The device will have a significant current flow through it, i.e., the on state. As can be seen from the above, the change of the energy band by the super barrier structure causes the knee voltage of the rectifying structure to drop below 0.4V, and the specific drop value can be adjusted by the change of the parameter. Generally speaking, the knee voltage of the traditional silicon carbide schottky diode is about 1V, so the turn-on voltage of the device structure provided by the invention is lower than that of the traditional schottky barrier diode with the same specification, and the device structure provided by the invention has absolute advantages in low-voltage application.
For convenience of illustration, the present embodiment takes P-type polysilicon as an example, and those skilled in the art can derive the principle of N-type polysilicon based on the above. Two functional regions are shown in fig. 8, where a is a super barrier + schottky barrier structure and B is a Si/SiC heterojunction. In the case of neglecting the resistance, the I-V characteristic curve of the single functional region is shown in FIG. 10, the forward turn-on voltage drop of the super barrier + Schottky barrier structure is less than 0.4V, and the forward turn-on voltage drop of the Si/SiC heterojunction is about 1.1V. As the voltage applied to the metal anode 1 increases, the voltage drop across the Si/SiC heterojunction also increases. When the voltage drop across the Si/SiC heterojunction reaches 1.1V, the Si/SiC heterojunction will conduct. And the I-V characteristic of the diode device is shown in fig. 11. Curve a in fig. 11 represents the case where only the super barrier + schottky barrier structure is on; the curve A + B represents the conduction of the super barrier + Schottky barrier structure and the Si/SiC heterojunction. As can be seen from fig. 11: due to the fact that the heterojunction is arranged, the multi-sub-current level of the device is increased, and the device provided by the invention has lower voltage drop under the same conduction current level; further, under larger anode current, the PN junction formed by the P-type silicon carbide Schottky contact region 8 and the N-silicon carbide epitaxial layer 2 can be conducted, so that the forward conduction current density of the device is increased by current branches, and the method has important significance for reducing the on-state loss of the device; in addition, the PN junction formed by the P + silicon carbide region 6 and the N-silicon carbide epitaxial layer 2 has a high voltage blocking capability, so that the defect of low withstand voltage capability of the conventional schottky diode can be overcome, and can bear high reverse withstand voltage, so that the PN junction has a high barrier potential and does not have "image force". Therefore, compared with the conventional Schottky diode device, the Schottky diode device provided by the invention has lower reverse leakage.
Example 2:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 3, and the difference compared with embodiment 1 is that: and P-type silicon carbide body regions are arranged below the P-type silicon carbide Schottky contact region 8, above the N-silicon carbide epitaxial layer 2 and between the dielectric layers 7. Generally, the doping levels required for silicon carbide schottky contacts and for silicon carbide epitaxial layers in the art are moderate, but there is some difference between the two. The silicon carbide schottky contact needs to take the barrier height of the schottky contact into consideration; and the silicon carbide epitaxial layer is concerned with the magnitude of the threshold voltage. To form further optimization, the region may be divided into two ion implantations or epitaxial processes to achieve optimal device performance.
Example 3:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 4, and the difference compared with embodiment 2 is that: the bottom end of the dielectric layer 7 extends transversely to separate the polycrystalline silicon 5 into two mutually independent parts, the polycrystalline silicon under the dielectric layer 7 is in short circuit with the metal anode 1, the potential of the polycrystalline silicon 5 is always kept consistent with the potential of the metal anode 1 in this way, and the potential of the polycrystalline silicon 5 is prevented from changing after the heterojunction is conducted, so that the fluctuation influence is generated on the I-V characteristic of the super barrier structure. This embodiment improves the reliability of the device in practical use as compared with embodiment 2.
Example 4:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 5, and the difference compared with embodiment 3 is that: the lateral width of the P + silicon carbide region 6 is made larger. Compared with embodiment 2, the larger the lateral width of the P + silicon carbide region 6 is, the stronger the electric field shielding effect on the region above the P + silicon carbide region 6 is when the device is in the blocking state, which not only protects the structures such as the heterojunction and the super barrier structure, but also improves the voltage withstanding performance of the device. It is to be noted that the wider the width of the P + silicon carbide region 6, the greater the on-resistance of the device when it is operating in the forward direction. The width of the P + silicon carbide region 6 needs to be balanced between forward and reverse operation.
Example 5:
the difference between the cell structure of the diode device provided by this embodiment and that of embodiment 1 is: the P + silicon carbide region 6 forms a super junction structure with the N-silicon carbide epitaxial layer 2. By controlling and adjusting the process parameters, the N columns, i.e., the N-silicon carbide epitaxial layer 2, and the P columns, i.e., the P + silicon carbide regions 6 satisfy Qn — Qp.
The super junction structure introduced in the embodiment can improve the voltage blocking capability of the device by optimizing the electric field distribution in the blocking mode, and obtains better compromise characteristics of forward voltage drop and voltage blocking capability.
Example 6:
the schematic diagram of the cell structure of the diode device provided by this embodiment is shown in fig. 6, and the difference compared with embodiment 5 is that: the doping concentration at the top of the N-silicon carbide epitaxial layer 2 is greater than that of the semiconductor region below the top thereof, thereby forming a heavily doped N-silicon carbide epitaxial layer 2b and a lightly doped N-silicon carbide epitaxial layer 2 a.
Example 7:
the schematic diagram of the cell structure of the diode device provided in this embodiment is shown in fig. 7, and the difference compared with embodiment 6 is that: the doping concentration of the top portion of the P + silicon carbide region 6 is greater than that of the semiconductor region below the top portion thereof, thereby forming a heavily doped P + silicon carbide region 6b and a lightly doped P + silicon carbide region 6 a.
Compared with embodiment 6, the present embodiment can protect the super barrier structure and the heterojunction above the N-pillar and the P-pillar better under the condition that the N-pillar and the P-pillar are fully depleted.
Example 8:
a manufacturing method of a diode device is characterized by comprising the following steps:
step 1: selecting a silicon carbide wafer with appropriate resistivity and thickness as the N-silicon carbide region epitaxial layer 2 and the N + silicon carbide substrate 3, as shown in fig. 12; wherein the doping concentration of the N + silicon carbide substrate 3 is 5e 18-9 e18/cm3The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide epitaxial layer 2 is 2e 15-8 e15/cm3The thickness is 5-8 μm, and the width is 0.5-2 μm;
step 2: performing aluminum ion implantation on the N-silicon carbide epitaxial layer 2 by a high-energy ion implantation process, wherein the implantation energy is about 1200-1500 keV, the thickness is about 0.3-0.4 μm, the width is about 0.2-0.4 μm, and the doping concentration is about 1e 16-1 e17/cm3The P-type silicon carbide schottky contact region 8 may also be prepared by epitaxy to form the P-type silicon carbide schottky contact region 8 as shown in fig. 13;
and step 3: by a groove etching process, a groove with the width of 0.3-0.5 μm and the depth of 1.1-2 μm is etched by using a Trench mask, as shown in FIG. 14;
and 4, step 4: depositing a P-type silicon carbide material at the bottom of the trench by deposition and etching processes, and removing unnecessary P-type silicon carbide semiconductor by etching to form a P-type silicon carbide semiconductor with a thickness of about 0.8-1.1 μm and a doping concentration of about 1e 19-7 e19/cm3A P + silicon carbide region 6 having a width of about 0.3 μm to about 0.5 μm, as shown in FIG. 15;
and 5: through deposition and etching processes, depositing polycrystalline silicon 5 on the bottom of the trench, namely the surface of the P + silicon carbide region 6, removing redundant polycrystalline silicon 5 through etching, and reserving a part of polycrystalline silicon 5 at the bottom of the trench, as shown in FIG. 16;
step 6: forming a dielectric layer 7 with a thickness of about 10nm to 50nm by a dry oxygen oxidation process at a temperature of 1100 ℃ to 1300 ℃, as shown in fig. 17;
and 7: selectively etching the dielectric layer 7 on the surface of the polysilicon 5 by an etching process, and leaving the dielectric layer 7 with the thickness of about 10 nm-50 nm on the side wall of the groove, as shown in FIG. 18;
and 8: depositing polycrystalline silicon 5 in the trench by deposition and etching processes, and removing redundant polycrystalline silicon 5 by etching to obtain polycrystalline silicon 56 with a width of about 0.3-0.5 μm and a thickness of about 0.8-1.6 μm, as shown in fig. 19;
and step 9: and forming a metal anode 1 and a metal cathode 4 with the thickness of 0.5-2.0 microns and the width of 0.5-2.0 microns by deposition, photoetching and etching processes, and finishing the manufacture of the device as shown in figure 20.
Further, in this embodiment, the narrow bandgap semiconductor deposited in step 5 and step 7 is polysilicon, and the polysilicon may be P-type polysilicon or N-type polysilicon. The method can also be realized by adopting monocrystalline silicon, and the monocrystalline silicon can be P-type monocrystalline silicon or N-type monocrystalline silicon.
Further, in this embodiment, the operations of forming the dielectric layer 7 and the polysilicon 5 in steps 6 and 7 may be replaced by the following operations: silicon nitride is deposited through the bottom of the trench and then thermal oxidation is performed. And then, etching the silicon nitride by using hot phosphoric acid, and finally forming the polycrystalline silicon in the groove by deposition and etching processes.
Further, in step 4 of this embodiment, after depositing the P + silicon carbide region 6, the step further includes making the width of the P + silicon carbide region 6 greater than the width of the trench through a thermal diffusion process, so as to obtain the device structure shown in fig. 5.
Further, the operation of forming the trench and the P + silicon carbide region 6 in the steps 3 and 4 may be replaced by the following operation: deepening the etching depth of the groove through multiple times of epitaxy, thermal diffusion and etching to ensure that the P + silicon carbide region 6 and the N-silicon carbide epitaxial layer 2 are in phase contact distribution, forming a super junction structure by controlling the width and the doping concentration of the P + silicon carbide region 6 and the N-silicon carbide epitaxial layer 2,
further, when the super junction structure is formed, after the N-silicon carbide epitaxial layer 2 is formed in step 3, a heavily doped N-silicon carbide epitaxial layer 2b is formed on the top of the N-silicon carbide epitaxial layer 2 through an ion implantation process, so that the device structure shown in fig. 6 can be obtained.
Further, when the superjunction structure is formed, after the P + silicon carbide region 6 is formed in step 4, forming a heavily doped P + silicon carbide region 6b on top of the P + silicon carbide region 6 by an ion implantation process, so as to obtain the device structure shown in fig. 7.
It should also be claimed that: as can be seen from the basic knowledge in the art, the wide bandgap semiconductor and the narrow bandgap semiconductor materials used in the diode device structure and the fabrication method of the diode device structure disclosed in the present invention are not limited to the silicon carbide and the silicon material disclosed in the present embodiment, and other combinations composed of the wide bandgap semiconductor material and the narrow bandgap semiconductor material are also suitable for the device structure provided in the present invention, and the present invention is not limited thereto; the dielectric layer may be formed of silicon dioxide (SiO2) or silicon nitride (Si)3N4) Hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) And the like, any suitable high-K dielectric material; meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
Claims (10)
1. A diode device comprises a cellular structure, a metal cathode (4), an N + wide bandgap semiconductor substrate (3), an N-wide bandgap semiconductor epitaxial layer (2) and a metal anode (1) which are sequentially stacked from bottom to top; two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer (2) are provided with groove structures, each groove structure comprises a P + wide bandgap semiconductor region (6) arranged at the bottom of each groove and a narrow bandgap semiconductor (5) arranged at the top of each groove, and the P + wide bandgap semiconductor region (6) is in direct contact with the narrow bandgap semiconductor (5); a P-type wide bandgap semiconductor Schottky contact region (8) is also arranged between the groove structures at the two sides of the top layer of the N-wide bandgap semiconductor epitaxial layer (2); the method is characterized in that: the P-type wide bandgap semiconductor Schottky contact region (8) and part of the N-wide bandgap semiconductor epitaxial layer (2) are in contact with the narrow bandgap semiconductor (5) through a dielectric layer (7) on the side wall of the groove; the narrow bandgap semiconductor (5), the dielectric layer (7) and the P-type wide bandgap semiconductor Schottky contact region (8) are in contact with the metal anode (1) above the narrow bandgap semiconductor; wherein: the narrow bandgap semiconductor (5), the dielectric layer (7), the P-type wide bandgap semiconductor Schottky contact region (8) and the N-wide bandgap semiconductor epitaxial layer (2) form a super barrier structure, the narrow bandgap semiconductor (5) and the N-wide bandgap semiconductor epitaxial layer (2) form a heterojunction at a contact interface, and the conduction type of the narrow bandgap semiconductor (5) is P type or N type.
2. A diode device according to claim 1, wherein: and a P-type wide bandgap semiconductor body region (9) is arranged below the P-type wide bandgap semiconductor Schottky contact region (8) and between the N-wide bandgap semiconductor epitaxial layer (2) and the dielectric layer (7).
3. A diode device according to claim 1, wherein: the width of the P + wide bandgap semiconductor region (6) is larger than that of the trench.
4. A diode device according to claim 1, wherein: the narrow-bandgap semiconductor (5) is further provided with a dielectric layer (7) which divides the narrow-bandgap semiconductor (5) into two mutually independent parts, the narrow-bandgap semiconductor (5) above the dielectric layer (7) is called a first narrow-bandgap semiconductor, the narrow-bandgap semiconductor (5) below the dielectric layer (7) is called a second narrow-bandgap semiconductor, and the second narrow-bandgap semiconductor is in short circuit with the metal anode (1) through ohmic contact.
5. A diode device according to claim 1, wherein: the P + wide bandgap semiconductor region (6) and the N-wide bandgap semiconductor epitaxial layer (2) form a super junction structure.
6. A diode device according to claim 5, wherein: the doping concentration of the top layer of the N-wide bandgap semiconductor epitaxial layer (2) is larger than that of the lower part of the top layer.
7. A diode device according to claim 5 or 6, wherein: the doping concentration of the top layer of the P + wide bandgap semiconductor region (6) is greater than the doping concentration below the top layer.
8. A diode device according to claim 1, wherein: the P + wide bandgap semiconductor region (6) is in short circuit with the metal anode (1) or the P + wide bandgap semiconductor region (6) is arranged in a floating mode.
9. A manufacturing method of a diode device is characterized by comprising the following steps:
step 1: selecting a wide bandgap semiconductor material as an N + wide bandgap semiconductor substrate (3) and an N-wide bandgap semiconductor epitaxial layer (2);
step 2: forming a P-type wide bandgap semiconductor Schottky contact region (8) positioned above the N-wide bandgap semiconductor epitaxial layer (2) through an ion implantation process or an epitaxial process;
and step 3: forming grooves on two sides of the N-wide bandgap semiconductor epitaxial layer (2) through a groove etching process;
and 4, step 4: depositing and etching process or ion implantation process on the bottom of the groove or implanting P-type wide bandgap semiconductor material below the groove to form a P + wide bandgap semiconductor region (6);
and 5: depositing a narrow-bandgap semiconductor material on the upper surface of the P + wide-bandgap semiconductor region (6) through deposition and etching processes, removing redundant narrow-bandgap semiconductor material through etching, and reserving a part of narrow-bandgap semiconductor material at the bottom of the groove to be used as a second narrow-bandgap semiconductor;
step 6: forming a dielectric layer (7) on the surface and the side wall of the narrow bandgap semiconductor through a dry oxygen oxidation or deposition process;
and 7: through deposition and etching processes, a narrow-bandgap semiconductor material is continuously deposited on the dielectric layer (7), redundant narrow-bandgap semiconductor material is removed through etching, a first narrow-bandgap semiconductor positioned on the dielectric layer (7) is formed, the first narrow-bandgap semiconductor and the second narrow-bandgap semiconductor form a narrow-bandgap semiconductor (5) separated by the dielectric layer (7), and the conduction type of the narrow-bandgap semiconductor (5) is P type or N type;
and 8: through deposition, photoetching and etching processes, a metal anode (1) is formed on the upper surfaces of a narrow bandgap semiconductor (5), a dielectric layer (7) and a P-type wide bandgap semiconductor Schottky contact region (8), and a metal cathode (4) is formed on the back surface of the turnover device, so that the manufacture of the device is completed.
10. The method of claim 9, wherein: the step 7 also comprises the following operations before: and selectively removing the dielectric layer (7) on the surface of the narrow-bandgap semiconductor through an etching process.
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