CN108682656A - A kind of compound silicon substrate and preparation method thereof, a kind of chip and a kind of electronic device - Google Patents
A kind of compound silicon substrate and preparation method thereof, a kind of chip and a kind of electronic device Download PDFInfo
- Publication number
- CN108682656A CN108682656A CN201810540939.5A CN201810540939A CN108682656A CN 108682656 A CN108682656 A CN 108682656A CN 201810540939 A CN201810540939 A CN 201810540939A CN 108682656 A CN108682656 A CN 108682656A
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- Prior art keywords
- silicon substrate
- compound
- layer
- preparation
- compound silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 79
- 239000010703 silicon Substances 0.000 title claims abstract description 79
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 150000001875 compounds Chemical class 0.000 title claims abstract description 40
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 230000000994 depressogenic effect Effects 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 229910017083 AlN Inorganic materials 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 4
- 230000008595 infiltration Effects 0.000 claims description 4
- 238000001764 infiltration Methods 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 238000000608 laser ablation Methods 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052593 corundum Inorganic materials 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims 1
- 238000001704 evaporation Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 239000004575 stone Substances 0.000 claims 1
- 238000004891 communication Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 56
- 239000011241 protective layer Substances 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000009413 insulation Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical group O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a kind of compound silicon substrate and preparation method thereof, a kind of chip and a kind of electronic devices, the compound silicon substrate includes silicon substrate, the surface of the silicon substrate has several depressed areas, and insulating buffer layer and third generation semiconductor material layer are covered with successively at least one depressed area.The compound silicon substrate of the present invention has two kinds of semiconductor material regions of silicon and third generation semi-conducting material simultaneously, can meet the needs of high speed communication and Fast Logical operation simultaneously, has preferable application prospect in field of electronic devices.
Description
Technical field
The present invention relates to display fields, more particularly, to a kind of compound silicon substrate and preparation method thereof, a kind of chip and one
Kind electronic device.
Background technology
Design circuit can only often be suitble to logic control on a silicon substrate in the prior art, and people are for semiconductor at present
The demand of substrate is not intended merely to it and disclosure satisfy that logic control, it is also desirable to which it can be suitable for high-frequency and height output transports work
Rate element, such as field-effect transistor (FET), it is therefore desirable to find a kind of suitable semiconductor substrate, can be suitble to simultaneously fast
The characteristics of fast logical operation and high speed communication.
Invention content
In view of the deficiencies of the prior art, the object of the present invention is to provide a kind of compound silicon substrate and preparation method thereof, one kind
Chip and a kind of display can meet the needs of Fast Logical operation and high speed communication simultaneously.
The technical solution used in the present invention is：
The present invention provides a kind of compound silicon substrate, including silicon substrate, and the surface of the silicon substrate has several depressed areas, until
It is covered with insulating buffer layer and third generation semiconductor material layer successively in a few depressed area.The present invention is according to reality in third
The position that the depressed area of compound silicon substrate is adjusted for the circuit designed on semiconductor material layer, to which the circuit for adapting to different is set
Meter demand.
The effect of insulating buffer layer in the present invention is interval silicon and third generation semiconductor material layer, is followed by being prepared
Play the role of protecting silicon in journey.
Preferably, the material of the insulating buffer layer is silicon nitride, SiON (Silicon Oxynitride), Al2O3In
It is at least one.
In certain embodiments, the preferably described silicon substrate is SOI silicon-on-insulators.
Further, the dielectric substrate in the SOI wafer is sapphire (Al2O3), at least one in aluminium nitride (AlN)
Kind.The energy gap ＞ 6ev of aluminium nitride belong to semi-conducting material but close to insulating materials, can be used as in this application exhausted
Edge substrate material uses.
Preferably, the material of the third generation semiconductor material layer is gallium nitride, silicon carbide, zinc oxide, diamond, nitridation
At least one of aluminium.
The present invention also provides a kind of preparation methods of above-mentioned compound silicon substrate, include the following steps：
(1) silicon substrate is taken, goes out depressed area in the surface etch of the silicon substrate；
(2) nitridation silicon buffer layer is prepared in the depressed area；
(3) third generation semiconductor material layer is prepared on the nitridation silicon buffer layer of the depressed area.
Preferably, using any one of yellow light processing procedure, laser ablation, dry etching, wet etching technique in step (1)
Etch depressed area.
Preferably, using chemical vapour deposition technique, the vapour deposition process of plasma enhanced chemical, vapor deposition in step (2)
Any one of technique, sputtering process technique prepares nitridation silicon buffer layer；
Preferably, third generation semi-conducting material is prepared using metallo-organic compound chemical vapor infiltration in step (3)
Layer.
The present invention also provides a kind of chips, include the preparation method system of above-mentioned compound silicon substrate or above-mentioned compound silicon substrate
The compound silicon substrate obtained.By designing different circuits in the different semiconductor material regions on above-mentioned compound silicon substrate,
The chip for meeting different circuit requirements is formed after encapsulated.
The present invention also provides a kind of electronic devices, including above-mentioned chip.
Further, the electronic device is light-emitting diode display, LCOS display, high electron mobility transistor (HEMT)
In it is any.
The beneficial effects of the invention are as follows：
Compared to the structure that traditional silicon and gallium nitride layer are sequentially overlapped, compound silicon substrate of the invention can be same
There are two kinds of semiconductor regions of silicon and third generation semiconductor material layer simultaneously in plane, design electricity in two kinds of semiconductor regions respectively
Road can be provided simultaneously with the characteristics of high speed communication and Fast Logical operation.The present invention compound silicon substrate and be based on the compound silicon substrate
The chip that plate is formed has preferable application prospect in fields such as LED, LCOS, HEMT.
Description of the drawings
Fig. 1 is the structural schematic diagram of the compound silicon substrate in the embodiment of the present invention 1；
Fig. 2 is the preparation flow figure of the compound silicon substrate in embodiment 1；
Fig. 3 is the preparation flow figure of compound silicon substrate in embodiment 2.
Specific implementation mode
The technique effect of design and the generation of the present invention is clearly and completely described below with reference to embodiment, with
It is completely understood by the purpose of the present invention, feature and effect.Obviously, described embodiment is that the part of the present invention is implemented
Example, rather than whole embodiments, based on the embodiment of the present invention, those skilled in the art is not before making the creative labor
Obtained other embodiment is put, the scope of protection of the invention is belonged to.
Embodiment 1
It is silicon substrate that the present embodiment selection dielectric substrate, which is sapphire SOI wafer (Silicon-On-Insulator),
And the structure and preparation method thereof of compound silicon substrate is specifically described as example.
Referring to Fig. 1, the present embodiment provides a kind of compound silicon substrate, including SOI wafer 11, the SOI wafer 11 includes exhausted
Edge substrate 111 and silicon layer 112,111 material of dielectric substrate is sapphire in the present embodiment, if the surface of the silicon layer 112 has
Dry depressed area, is covered with insulating buffer layer 13 and third generation semiconductor material layer 14 in the depressed area successively, in the present embodiment absolutely
The material of edge buffer layer 13 is silicon nitride, and the material of third generation semiconductor material layer 14 is gallium nitride (GaN).
Referring to Fig. 2, the present embodiment additionally provides a kind of preparation method of above-mentioned compound silicon substrate, includes the following steps：
(1) it includes dielectric substrate 111 and silicon layer 112 to take existing SOI wafer 11, the SOI wafer 11.Using yellow light system
Journey etches depressed area 12 on silicon layer 112, the specific steps are：One layer of photoresist is coated on the silicon layer 112, in the present embodiment
Photoresist is positivity photoresist, and by the protective layer 15 that exposed and developed step obtains having predetermined pattern, the protective layer 15 can
Silicon layer 112 under protection protective layer 15 covers is not etched, and etches depressed area 12 followed by RIE dry etching machines, finally
It performs etching and removes protective layer 15.
(2) one layer of buffer insulation is prepared on material prepared by step (1) using chemical vapor deposition method (CVD) technique
Layer of material 130, the material of buffer insulation layer of material is silicon nitride in the present embodiment, then in the buffer insulation layer material
One layer of photoresist 160 is coated on layer 130, photoresist 160 is positive photoresist in the present embodiment, it is roasting it is hard after through dry etching photoresist to exposing
Silicon nitride, so as to form protective layer 16, the silicon nitride under the protective layer 16 protects protective layer 16 to cover will not be etched, after
Continue dry etching silicon nitride to silicon layer 112 is exposed, to be formd in depressed area under protective layer 16 and protective layer 16
The insulating buffer layer 13 of covering finally performs etching and removes protective layer 16.
(3) is prepared on above-mentioned insulating buffer layer 13 using metallo-organic compound chemical vapor infiltration (MOCVD)
Three generations's semiconductor material layer 14, the material of insulating buffer layer 13 is silicon nitride, third generation semiconductor material layer 14 in the present embodiment
Material selection gallium nitride (GaN).
Circuit is designed on the compound silicon substrate obtained in the present embodiment, by chip, Neng Gouying are prepared after encapsulation
For fields such as LED, LCOS, and since the compound silicon substrate of the present invention exists simultaneously silicon and third generation semiconductor material layer two
Kind semiconductor regions, it is thus possible to meet the needs of high speed communication and Fast Logical operation, in light-emitting diode display, LCOS display
It has broad application prospects in high electron mobility transistor.
Embodiment 2
The present embodiment provides a kind of compound silicon substrate, including SOI wafer, the SOI wafer includes dielectric substrate and silicon layer,
Insulating substrate material is AlN in the present embodiment, and the surface of the silicon layer has depressed area, and the depressed area is covered with silicon nitride successively
Buffer layer and third generation semiconductor material layer, the material of third generation semiconductor material layer is aluminium nitride in the present embodiment.
Referring to Fig. 3, the present embodiment additionally provides a kind of preparation method of above-mentioned compound silicon substrate, includes the following steps：
(1) existing SOI wafer 21 is taken, the SOI wafer 21 includes dielectric substrate 211 and silicon layer 212, in the present embodiment
211 material of dielectric substrate is AlN.Laser mask plate 25 is placed above the SOI wafer 21, the laser mask plate 25 includes
Lightproof part 251 and light transmission part 252 etch the depressed area with predetermined pattern using laser ablation on silicon layer 212
22。
(2) utilize gas-phase deposition (PECVD) technique of plasma enhanced chemical on material prepared by step (1)
One layer of buffer insulation layer of material 230 is prepared, the material of buffer insulation layer of material 230 is SION (Silicon in the present embodiment
Oxynitride), one layer of photoresist 260 is then coated in the buffer insulation layer of material 230, photoresist 260 in the present embodiment
For positive photoresist, through dry etching photoresist to silicon nitride is exposed after baking firmly, so as to form protective layer 26, the protective layer 26 is protected
The lower silicon nitride of the shield covering of protective layer 26 will not be etched, the rear dry etching silicon nitride that continues to exposing silicon layer 212, thus
The insulating buffer layer 23 that the 26 times coverings of protective layer 26 and protective layer are formd in depressed area, finally performs etching removing protective layer
26.
(3) is prepared on above-mentioned insulating buffer layer 23 using metallo-organic compound chemical vapor infiltration (MOCVD)
Three generations's semiconductor material layer 24, the material of insulating buffer layer 23 is SION in the present embodiment, third generation semiconductor material layer 24
Material selection aluminium nitride.
Claims (12)
1. a kind of compound silicon substrate, which is characterized in that including silicon substrate, the surface of the silicon substrate has several depressed areas, until
It is covered with insulating buffer layer and third generation semiconductor material layer successively in a few depressed area.
2. compound silicon substrate according to claim 1, which is characterized in that the material of the insulating buffer layer be silicon nitride,
SiON、Al2O3At least one of.
3. compound silicon substrate according to claim 1, which is characterized in that the silicon substrate is SOI wafer.
4. compound silicon substrate according to claim 2, which is characterized in that the dielectric substrate in the SOI wafer is blue precious
At least one of stone, aluminium nitride.
5. according to the compound silicon substrate of claim 1-4 any one of them, which is characterized in that the third generation semiconductor material layer
Material be gallium nitride, silicon carbide, zinc oxide, diamond, at least one of aluminium nitride.
6. the preparation method of the compound silicon substrate of claim 1-5 any one of them, which is characterized in that include the following steps：
(1) silicon substrate is taken, goes out depressed area in the surface etch of the silicon substrate；
(2) nitridation silicon buffer layer is prepared in the depressed area；
(3) third generation semiconductor material layer is prepared on the nitridation silicon buffer layer of the depressed area.
7. the preparation method of compound silicon substrate according to claim 6, which is characterized in that use yellow light system in step (1)
Any one of journey, laser ablation, dry etching, wet etching technique etches depressed area.
8. the preparation method of compound silicon substrate according to claim 6, which is characterized in that using chemical gas in step (2)
Any one of phase sedimentation, the vapour deposition process of plasma enhanced chemical, evaporation process, sputtering process technique prepares nitridation
Silicon buffer layer.
9. the preparation method of compound silicon substrate according to claim 6, which is characterized in that had using metal in step (3)
Machine compound chemical vapor infiltration prepares third generation semiconductor material layer.
10. a kind of chip, which is characterized in that including the compound silicon substrate of claim 1-5 any one of them or claim 6-9
Compound silicon substrate made from the preparation method of the compound silicon substrate of any one.
11. a kind of electronic device, which is characterized in that including chip according to any one of claims 10.
12. electronic device according to claim 11, which is characterized in that the electronic device is light-emitting diode display, LCOS is aobvious
Show any in device, high electron mobility transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810540939.5A CN108682656B (en) | 2018-05-30 | 2018-05-30 | Composite silicon substrate, preparation method thereof, chip and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810540939.5A CN108682656B (en) | 2018-05-30 | 2018-05-30 | Composite silicon substrate, preparation method thereof, chip and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108682656A true CN108682656A (en) | 2018-10-19 |
| CN108682656B CN108682656B (en) | 2024-10-25 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109637971A (en) * | 2018-12-07 | 2019-04-16 | 合肥市华达半导体有限公司 | A kind of semiconductor devices with improvement performance |
| CN110349924A (en) * | 2019-06-23 | 2019-10-18 | 中国电子科技集团公司第五十五研究所 | A kind of lifting tab is embedded in the process of diamond gallium nitride transistor thermotransport ability |
| CN112311251A (en) * | 2020-09-18 | 2021-02-02 | 威海新佳电子有限公司 | Rectifier module |
| WO2022204913A1 (en) * | 2021-03-30 | 2022-10-06 | Innoscience (Suzhou) Technology Co., Ltd. | Iii nitride semiconductor devices on patterned substrates |
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| CN109637971A (en) * | 2018-12-07 | 2019-04-16 | 合肥市华达半导体有限公司 | A kind of semiconductor devices with improvement performance |
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| WO2022204913A1 (en) * | 2021-03-30 | 2022-10-06 | Innoscience (Suzhou) Technology Co., Ltd. | Iii nitride semiconductor devices on patterned substrates |
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| CN108682656B (en) | 2024-10-25 |
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