CN108649914B - LTCC laminated sheet type duplexer - Google Patents
LTCC laminated sheet type duplexer Download PDFInfo
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- CN108649914B CN108649914B CN201810243517.1A CN201810243517A CN108649914B CN 108649914 B CN108649914 B CN 108649914B CN 201810243517 A CN201810243517 A CN 201810243517A CN 108649914 B CN108649914 B CN 108649914B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/46—Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
- H03H7/463—Duplexers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
- H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
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Abstract
An LTCC laminated sheet type duplexer relates to a miniaturized LTCC laminated sheet type duplexer, and solves the technical defects that the existing LTCC laminated sheet type duplexer is large in size, large in loss of frequency division functions of low-frequency signals and high-frequency signals, poor in common-mode signal inhibition capability, high in cost and the like, and comprises a ceramic substrate, wherein a first grounding port (P1), a common port (P2), a third grounding port (P3), a high-frequency band-pass output port (P4), a fifth grounding port (P5) and a low-frequency band output port (P6) are arranged on the outer side wall of the ceramic substrate; a low-pass filter for separating low-frequency-band signals is arranged between the common port (P2) and the low-frequency-band output port (P6) in the ceramic substrate; a band-pass filter for separating out high-frequency band pass signals is arranged between the common port (P2) and the high-frequency band pass output port (P4) in the ceramic substrate; the ceramic substrate contains 11 ceramic dielectric circuit layers in a laminated structure, effectively realizes the frequency division function of low-frequency signals and high-frequency signals, and has the advantages of low loss, high isolation, high inhibition, high reliability, low cost, excellent consistency, suitability for large-scale production and the like.
Description
Technical Field
The invention relates to a miniaturized LTCC laminated sheet type duplexer which can be used in a 4G mobile communication system, a tablet computer and other various communication equipment.
Background
The LTCC technology is that Low Temperature sintered Ceramic powder is made into a green Ceramic tape with precise and compact thickness as a circuit substrate material, required circuit patterns are made on the green Ceramic tape by utilizing the processes of laser drilling, micropore grouting, precise conductor paste printing and the like, a plurality of passive elements are embedded in the green Ceramic tape, and then the green Ceramic tape and the passive elements are laminated together and sintered at 900 ℃ to make a passive integrated component of a three-dimensional circuit network. The radio frequency microwave element designed and produced based on the LTCC technology comprises a filter, a duplexer, an antenna, a coupler, a balun, a receiving front-end module, an antenna switch module and the like. Because of its advantages of good high frequency property, high speed transmission, high integration and the like, with the continuous development of miniaturization and high frequency of modern electronic devices, they have been applied to miniaturized electronic devices, especially to consumer electronic devices such as mobile phones, tablet computers, digital cameras, electronic readers and the like.
Information technology is continuously developed, more spectrum resources are needed, and in mobile phone design, a filter becomes an indispensable device, and a duplexer can be used for processing an input signal of a frequency band or be integrated in an Antenna Switch Module (ASM) or a mobile phone radio frequency Front End (FEM). The duplexer manufactured by the LTCC technology has the advantages of high reliability, low insertion loss, high selectivity, small volume, light weight, easiness in integration, low cost and the like, and is suitable for large-scale production. The market prospect is very considerable.
Disclosure of Invention
In summary, the present invention is directed to solve the technical deficiencies of the conventional LTCC stacked sheet duplexer, such as large volume, large loss of frequency division function of low-frequency signals and high-frequency signals, poor capability of suppressing common-mode signals, and high cost.
In order to solve the technical problems provided by the invention, the technical scheme is as follows:
an LTCC laminated sheet type duplexer is characterized by comprising a ceramic substrate, wherein a first grounding port (P1), a common port (P2), a third grounding port (P3), a high-frequency band-pass output port (P4), a fifth grounding port (P5) and a low-frequency band output port (P6) are arranged on the outer side wall of the ceramic substrate; a low-pass filter for separating low-frequency-band signals is arranged between the common port (P2) and the low-frequency-band output port (P6) in the ceramic substrate; a band-pass filter for separating out high-frequency band pass signals is arranged between the common port (P2) and the high-frequency band pass output port (P4) in the ceramic substrate; the ceramic substrate comprises 11 ceramic dielectric circuit layers in a laminated structure, wherein:
a first layer, wherein three mutually insulated metal plane conductors are printed on a ceramic dielectric substrate, and each plane conductor is composed of a first layer first capacitor substrate (1-C1), a first layer first internal end point (1A) for connecting the first layer first capacitor substrate (1-C1) with a first grounding port (P1), and a first layer fourth internal end point (1D) for connecting the first layer first capacitor substrate (1-C1) with a fifth grounding port (P5); the second planar conductor is composed of a first layer of a second capacitor substrate (1-C2), a first layer of a third capacitor substrate (1-C3) connected with the first layer of the second capacitor substrate (1-C2), and a first layer of a second inner terminal (1B) connected with the first layer of the second capacitor substrate (1-C2) and the common port (P2); the third planar conductor is formed of a first-layer dummy terminal (1C) connected to a third ground port (P3);
the second layer is printed with four mutually insulated metal plane conductors on the ceramic dielectric substrate, the first plane conductor is composed of a second layer of first capacitor substrate (2-C1), and the second layer of first capacitor substrate (2-C1) is also connected with an eighteenth point column (18); the second plane conductor is composed of a second layer of second capacitor substrate (2-C2), and the second layer of second capacitor substrate (2-C2) is also connected with a twenty-first point post (21); the third planar conductor is composed of a second layer of third capacitor substrate (2-C3), and a twenty-second contact column (22) is connected with the second layer of third capacitor substrate (2-C3); the fourth plane conductor is composed of a second layer of dummy leading-out terminals (2A) connected with the high-frequency band-pass output port (P4);
the third layer is printed with eight mutually insulated metal plane conductors on the ceramic dielectric substrate, the first plane conductor is composed of a third layer of a first capacitor substrate (3-C1) and a third layer of a fifth internal endpoint (3E), and the third layer of the fifth internal endpoint (3E) is connected with a low-frequency output port (P6); the second plane conductor is composed of a third layer of second capacitor substrate (3-C2) and a third layer of first inner terminal (3A), and the third layer of first inner terminal (3A) is connected with the first grounding port (P1); the third planar conductor is composed of a third layer of third capacitor substrate (3-C3) and a third layer of second inner terminal (3B), the third layer of second inner terminal (3B) is connected with the common port (P2); the fourth plane conductor is composed of a third layer of a fourth capacitor substrate (3-C4), and the third layer of the fourth capacitor substrate (3-C4) is also connected with a twenty-first point post (21); the fifth, sixth, seventh and eighth plane conductors are respectively composed of a third layer of first false leading-out terminal (3C), a third layer of second false leading-out terminal (3D), a third layer of first printing point column (18-1) and a third layer of second printing point column (22-1); the third layer first dummy lead-out terminal (3C) is connected with a third ground port (P3), and the third layer second dummy lead-out terminal (3D) is connected with a high-frequency band-pass output port (P4); the third layer of first printing dot columns (18-1) is a component of the eighteenth dot columns (18), and the third layer of second printing dot columns (22-1) is a component of the twenty-second dot columns (22);
a fourth layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a fourth layer of first capacitor substrate (4-C1) and a fourth layer of first internal end point (4A), and the fourth layer of first internal end point (4A) is connected with a fifth grounding port (P5); the second, third and fourth plane conductors are respectively composed of a fourth layer of first printing point column (18-2), a fourth layer of second printing point column (21-1) and a fourth layer of third printing point column (22-2); a fourth layer of first printing dot columns (18-2) is a component of the eighteenth dot column (18), a fourth layer of second printing dot columns (21-1) is a component of the twenty-first dot column (21), and a fourth layer of third printing dot columns (22-2) is a component of the twenty-second dot column (22);
a fifth layer, wherein three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor consists of a fifth layer first inductance coil (5-L1), and a fifth layer first inner end point (5A) and a fifth layer second inner end point (5B) which are respectively arranged at two ends of the fifth layer first inductance coil (5-L1); the second and the three plane conductors are respectively composed of a fifth layer first printing point pillar (21-3) and a fifth layer second printing point pillar (22-4); the fifth layer first internal end point (5A) and the fifth layer second internal end point (5B) are respectively connected with the eighteenth dot column (18) and the nineteenth dot column (19); a fifth layer of first printed dot columns (21-3) is a component of the twenty-first dot columns (21), and a fifth layer of second printed dot columns (22-4) is a component of the twenty-second dot columns (22);
a sixth layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, and the first plane conductor consists of a sixth layer of first inductance coil (6-L1), and a sixth layer of first internal end point (6A) and a sixth layer of second internal end point (6B) which are respectively arranged at two ends of the sixth layer of first inductance coil (6-L1); the first inner end point (6A) of the sixth layer is connected with the seventeenth point column (17), and the second inner end point (6B) of the sixth layer is connected with the nineteenth point column (19); the second plane conductor is composed of a sixth layer of second inductance coil (6-L2), a sixth layer of third inner end point (6C) and a sixth layer of fourth inner end point (6D) which are respectively arranged at two ends of the sixth layer of second inductance coil (6-L2); a sixth layer of third internal end points (6C) and a sixth layer of fourth internal end points (6D) are respectively connected with the twenty-second pointed columns (20) and the twenty-second pointed columns (22); the third and the fourth plane conductors are respectively composed of printed point columns (18-5) and printed point columns (21-5); the printing point column (18-5) is a component of the eighteenth point column (18), and the printing point column (21-5) is a component of the twenty-first point column (21);
a seventh layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a seventh layer first inductance coil (7-L1), and a seventh layer first internal endpoint (7A) and a seventh layer second internal endpoint (7B) which are respectively arranged at two ends of the seventh layer first inductance coil (7-L1), the seventh layer first internal endpoint (7A) is connected with the low-frequency-band output port (P6), and the seventh layer second internal endpoint (7B) is connected with the seventeenth point column (17); the second plane conductor comprises a seventh layer of second inductance coil (7-L2) and a seventh layer of fourth inner end point (7D) arranged at the tail end of the seventh layer of second inductance coil (7-L2), the seventh layer of fourth inner end point (7D) is connected with the high-frequency band-pass output port (P4), and the head end of the seventh layer of second inductance coil (7-L2) is connected with the twentieth post (20); the third and the fourth plane conductors are respectively composed of printing point columns (18-7) and printing point columns (21-7); the printing point column (18-7) is a component of the eighteenth point column (18), and the printing point column (21-7) is a component of the twenty-first point column (21);
an eighth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is formed by an eighth layer of first inductance coil (8-L1), and two ends of the eighth layer of first inductance coil (8-L1) are respectively connected with an eighteenth point column (18) and a sixteenth point column (16); the second plane conductor is composed of an eighth layer of second inductance coil (8-L2), and two ends of the eighth layer of second inductance coil (8-L2) are respectively connected with the twelfth point post (12) and the twenty-first point post (21);
a ninth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a ninth layer first inductance coil (9-L1), and a ninth layer first inner end point (9A) and a ninth layer second inner end point (9B) which are respectively arranged at two ends of the ninth layer first inductance coil (9-L1), and the ninth layer first inner end point (9A) and the ninth layer second inner end point (9B) are respectively connected with a sixteenth dot column (16) and a fifteenth dot column (15); the second plane conductor is composed of a ninth layer of second inductance coil (9-L2), a ninth layer of third inner end point (9C) and a ninth layer of fourth inner end point (9D) which are respectively arranged at two ends of the ninth layer of second inductance coil (9-L2), and the ninth layer of third inner end point (9C) and the ninth layer of fourth inner end point (9D) are respectively connected with the twelfth point column (12) and the twenty-third point column (23);
a tenth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor consists of a tenth layer of first inductance coil (10-L1), and a tenth layer of first inner end point (10A) and a tenth layer of second inner end point (10B) which are respectively arranged at two ends of the tenth layer of first inductance coil (10-L1), and the tenth layer of first inner end point (10A) and the tenth layer of second inner end point (10B) are respectively connected with a thirteenth point column (13) and a fifteenth point column (15); the second plane conductor is composed of a tenth layer of second inductance coil (10-L2), a tenth layer of third inner end point (10C) and a tenth layer of fourth inner end point (10D) which are respectively arranged at two ends of the tenth layer of second inductance coil (10-L2), and the tenth layer of third inner end point (10C) and the tenth layer of fourth inner end point (10D) are respectively connected with the fourteenth point column (14) and the twenty-third point column (23);
the first layer is formed by printing two mutually insulated metal plane conductors on a ceramic dielectric substrate, the first plane conductor consists of a first inductance coil (11-L1) of the first eleventh layer, and a first inner end point (11A) of the eleventh layer and a third inner end point (11C) of the eleventh layer which are respectively arranged at two ends of the first inductance coil (11-L1) of the eleventh layer, the first inner end point (11A) of the eleventh layer is connected with a common port (P2), and the third inner end point (11C) of the eleventh layer is connected with a thirteenth point column (13); the second plane conductor is composed of a eleventh layer second inductance coil (11-L2), a eleventh layer second inner end point (11B) and a eleventh layer fourth inner end point (11D) which are respectively arranged at two ends of the eleventh layer second inductance coil (11-L2), the eleventh layer second inner end point (11B) is connected with the fourteenth point column (14), and the eleventh layer fourth inner end point (11D) is connected with the fifth grounding port (P5).
The first grounding port (P1), the common port (P2) and the third grounding port (P3) are arranged on the front outer side wall of the ceramic substrate; the high-frequency band-pass output port (P4), the fifth grounding port (P5) and the low-frequency band output port (P6) are arranged on the rear outer side wall of the ceramic substrate.
The invention has the beneficial effects that: the invention is based on LTCC (low temperature co-fired ceramic) technology, and realizes the special electrical property requirement of a novel LTCC laminated sheet type duplexer by adopting lumped parameter model design. The invention effectively realizes the frequency division function of low-frequency signals and high-frequency signals, has the advantages of low loss, high isolation, high inhibition, high reliability, low cost, excellent consistency, suitability for large-scale production and the like, and is also suitable for the development trend of integration and miniaturization of new electronic elements.
Drawings
FIG. 1 is a schematic diagram of an equivalent circuit of an LTCC stacked chip duplexer in accordance with the present invention;
fig. 2 is a schematic perspective view of an LTCC stacked chip duplexer in accordance with the present invention;
fig. 3 is a schematic diagram of an internal structure of the LTCC stacked chip duplexer of the present invention;
FIG. 4 is a schematic plan view of a first circuit layer according to the present invention;
FIG. 5 is a schematic diagram of a second layer circuit structure according to the present invention;
FIG. 6 is a schematic diagram of a third layer circuit plane structure according to the present invention
FIG. 7 is a schematic diagram of a fourth layer circuit plan structure according to the present invention;
FIG. 8 is a schematic diagram of a fifth layer circuit plane structure according to the present invention
FIG. 9 is a schematic diagram of a sixth layer circuit plan structure according to the present invention;
FIG. 10 is a schematic diagram of a seventh layer circuit layout according to the present invention;
FIG. 11 is a schematic diagram of a circuit plan structure of an eighth layer according to the present invention;
FIG. 12 is a plan view of a ninth layer of circuit according to the present invention;
FIG. 13 is a schematic diagram of a tenth layer circuit plan structure according to the present invention;
fig. 14 is a schematic circuit plan structure diagram of the eleventh layer of the present invention.
Detailed Description
The structure of the present invention will be further described with reference to the accompanying drawings and preferred embodiments of the present invention.
Referring to fig. 1 to 3, the LTCC stacked chip duplexer of the present invention includes a ceramic substrate, and a first ground port P1, a common port P2, a third ground port P3, a high-frequency band-pass output port P4, a fifth ground port P5, and a low-frequency band output port P6 are disposed on an outer sidewall of the ceramic substrate; the first grounding port P1, the common port P2 and the third grounding port P3 are preferably arranged on the front outer side wall of the ceramic substrate; the high-frequency band-pass output port P4, the fifth ground port P5 and the low-frequency band output port P6 are arranged on the rear outer side wall of the ceramic substrate.
A low-pass filter for separating low-frequency signals is arranged between the common port P2 and the low-frequency output port P6 in the ceramic substrate; and a band-pass filter for separating out high-frequency band pass signals is arranged between the common port P2 and the high-frequency band pass output port P4 in the ceramic substrate. Referring to fig. 1, the signal input from the common port P2 is taken as an example to explain: after the signal is input from a public port P2, the signal is output from a low-frequency-band output port P6, and the link is a low-pass filter and divides a low-frequency-band signal; after the signal is input from the common port P2, the signal is output from the high-frequency band-pass output port P4, and the link is a band-pass filter and divides a high-frequency-band signal. The high-frequency band-pass filter is composed of a high-pass filter body and an inductor connected in series, wherein the high-pass filter body is composed of an inductor L1, a capacitor C1, a capacitor C2 and a capacitor C3, the capacitor C3 is a cross-over capacitor, the attenuation of a stop band of the high-frequency band-pass filter body in a low frequency band is effectively improved, the inductor L2 is connected in series, and the attenuation of the stop band of the high-frequency band-pass filter body in the high frequency band is effectively improved. The low-frequency band signal is divided by the low-pass filter, the low-pass filter is composed of an inductor L3, an inductor L4, a capacitor C4, a capacitor C5 and a capacitor C6, the inductor L4 and the capacitor C5 are connected in parallel and resonate to form a transmission zero, and therefore the stop band attenuation of the low-frequency band low-pass filter in the low-frequency band is effectively improved.
Referring to fig. 3 to 14, the ceramic substrate according to the present invention includes 11 ceramic dielectric circuit layers having a laminated structure, and each of the 11 ceramic dielectric circuit layers having a laminated structure has the following structure:
the first layer is printed with three mutually insulated metal plane conductors on the ceramic dielectric substrate, and the first plane conductor is composed of a first layer of first capacitor substrates 1-C1, a first layer of first internal end points 1A for connecting the first layer of first capacitor substrates 1-C1 and a first grounding port P1, and a first layer of fourth internal end points 1D for connecting the first layer of first capacitor substrates 1-C1 and a fifth grounding port P5; the second planar conductor is composed of a first layer of second capacitor substrates 1-C2, a first layer of third capacitor substrates 1-C3 connected to the first layer of second capacitor substrates 1-C2, and a first layer of second inner terminal 1B connected to the first layer of second capacitor substrates 1-C2 and the common port P2; the third planar conductor is constituted by the first-layer dummy terminal 1C connected to the third ground port P3;
the second layer, there are four pieces of mutual insulated metal plane conductors on the ceramic dielectric base plate, the first plane conductor is formed by the first capacitor substrate 2-C1 of the second layer, the said second layer first capacitor substrate 2-C1 connects with eighteenth some posts 18; the second plane conductor is composed of a second layer of second capacitor substrate 2-C2, and the second layer of second capacitor substrate 2-C2 is also connected with a twenty-first point post 21; the third planar conductor is formed by a second layer of third capacitor substrate 2-C3, the second layer of third capacitor substrate 2-C3 is also connected with a twenty-second contact 22; the fourth plane conductor is composed of a second layer of dummy leading-out terminals 2A connected with the high-frequency band-pass output port P4;
the ceramic dielectric substrate is printed with eight mutually insulated metal plane conductors, the first plane conductor consists of a third layer of first capacitor substrate 3-C1 and a third layer of fifth internal end point 3E, and the third layer of fifth internal end point 3E is connected with the low-frequency-band output port P6; the second plane conductor is composed of a third layer of second capacitor substrates 3-C2 and a third layer of first inner terminal 3A, and the third layer of first inner terminal 3A is connected with the first grounding port P1; the third planar conductor is composed of a third layer of third capacitor substrates 3-C3 and a third layer of second inner terminal 3B, the third layer of second inner terminal 3B is connected with the common port P2; the fourth plane conductor is composed of a third layer of a fourth capacitor substrate 3-C4, and the third layer of the fourth capacitor substrate 3-C4 is also connected with a twenty-first point post 21; the fifth, sixth, seventh and eighth plane conductors are respectively composed of a third layer of first false leading-out terminal 3C, a third layer of second false leading-out terminal 3D, a third layer of first printing dot column 18-1 and a third layer of second printing dot column 22-1; the third layer of the first dummy terminal 3C is connected with a third ground port P3, and the third layer of the second dummy terminal 3D is connected with a high-frequency band-pass output port P4; the third layer of first printing dot column 18-1 is a component of the eighteenth dot column 18, and the third layer of second printing dot column 22-1 is a component of the twenty-second dot column 22;
a fourth layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a fourth layer of first capacitor substrates 4-C1 and a fourth layer of first internal end point 4A, and the fourth layer of first internal end point 4A is connected with a fifth grounding port P5; the second, third and fourth plane conductors are respectively composed of a fourth layer of first printing point column 18-2, a fourth layer of second printing point column 21-1 and a fourth layer of third printing point column 22-2; a fourth layer of first printing dot columns 18-2 is a component of the eighteenth dot column 18, a fourth layer of second printing dot columns 21-1 is a component of the twenty-first dot column 21, and a fourth layer of third printing dot columns 22-2 is a component of the twenty-second dot column 22;
a fifth layer, wherein three mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, and the first plane conductor consists of a fifth layer first inductance coil 5-L1, a fifth layer first inner end point 5A and a fifth layer second inner end point 5B which are respectively arranged at two ends of the fifth layer first inductance coil 5-L1; the second and the three plane conductors are respectively composed of a fifth layer first printing dot column 21-3 and a fifth layer second printing dot column 22-4; the fifth layer first inner end 5A and the fifth layer second inner end 5B are respectively connected with the eighteenth dot column 18 and the nineteenth dot column 19; a fifth layer of first printed dot columns 21-3 is a component of the twenty-first dot columns 21, and a fifth layer of second printed dot columns 22-4 is a component of the twenty-second dot columns 22;
a sixth layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, and the first plane conductor consists of a sixth layer of first inductance coil 6-L1, and a sixth layer of first internal end point 6A and a sixth layer of second internal end point 6B which are respectively arranged at two ends of the sixth layer of first inductance coil 6-L1; the sixth layer first inner end point 6A is connected with the seventeenth point column 17, and the sixth layer second inner end point 6B is connected with the nineteenth point column 19; the second plane conductor is composed of a sixth layer of second inductance coils 6-L2, a sixth layer of third inner end points 6C and a sixth layer of fourth inner end points 6D which are respectively arranged at two ends of the sixth layer of second inductance coils 6-L2; the sixth layer of third internal end points 6C and the sixth layer of fourth internal end points 6D are connected with the twenty-second pointed posts 20 and 22, respectively; the third and the fourth plane conductors are respectively composed of printed point columns 18-5 and printed point columns 21-5; the printing dot column 18-5 is a component of the eighteenth dot column 18, and the printing dot column 21-5 is a component of the twenty-first dot column 21;
a seventh layer, wherein four mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a seventh layer of first inductance coil 7-L1, and a seventh layer of first internal endpoint 7A and a seventh layer of second internal endpoint 7B which are respectively arranged at two ends of the seventh layer of first inductance coil 7-L1, the seventh layer of first internal endpoint 7A is connected with the low-frequency output port P6, and the seventh layer of second internal endpoint 7B is connected with the seventeenth point post 17; the second plane conductor comprises a seventh layer of second inductance coil 7-L2 and a seventh layer of fourth inner end point 7D arranged at the tail end of the seventh layer of second inductance coil 7-L2, the seventh layer of fourth inner end point 7D is connected with the high-frequency band-pass output port P4, and the head end of the seventh layer of second inductance coil 7-L2 is connected with the twentieth post 20; the third and the fourth plane conductors are respectively composed of printed point columns 18-7 and printed point columns 21-7; the printing dot column 18-7 is a component of the eighteenth dot column 18, and the printing dot column 21-7 is a component of the twenty-first dot column 21;
an eighth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is formed by the eighth layer of the first inductance coil 8-L1, and two ends of the eighth layer of the first inductance coil 8-L1 are respectively connected with the eighteenth point column 18 and the sixteenth point column 16; the second plane conductor is composed of an eighth layer of second inductance coil 8-L2, and the two ends of the eighth layer of second inductance coil 8-L2 are respectively connected with the twelfth point post 12 and the twenty-first point post 21;
a ninth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a ninth layer of first inductance coil 9-L1, and a ninth layer of first inner end point 9A and a ninth layer of second inner end point 9B which are respectively arranged at two ends of the ninth layer of first inductance coil 9-L1, and the ninth layer of first inner end point 9A and the ninth layer of second inner end point 9B are respectively connected with the sixteenth point post 16 and the fifteenth point post 15; the second planar conductor is composed of a ninth layer of second inductance coils 9-L2, a ninth layer of third inner end point 9C and a ninth layer of fourth inner end point 9D which are respectively arranged at two ends of the ninth layer of second inductance coils 9-L2, and the ninth layer of third inner end point 9C and the ninth layer of fourth inner end point 9D are respectively connected with the twelfth point column 12 and the twenty-third point column 23;
a tenth layer, wherein two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, the first plane conductor is composed of a tenth layer of first inductance coil 10-L1, and a tenth layer of first inner end point 10A and a tenth layer of second inner end point 10B which are respectively arranged at two ends of the tenth layer of first inductance coil 10-L1, and the tenth layer of first inner end point 10A and the tenth layer of second inner end point 10B are respectively connected with the thirteenth point post 13 and the fifteenth point post 15; the second plane conductor is composed of a tenth layer of second inductance coil 10-L2, a tenth layer of third inner end point 10C and a tenth layer of fourth inner end point 10D which are respectively arranged at two ends of the tenth layer of second inductance coil 10-L2, and the tenth layer of third inner end point 10C and the tenth layer of fourth inner end point 10D are respectively connected with the fourteenth point column 14 and the twenty-third point column 23;
the first layer is formed by printing two mutually insulated metal plane conductors on a ceramic dielectric substrate, the first plane conductor consists of a first inductance coil 11-L1 of the first layer, and a first inner end point 11A of the eleventh layer and a third inner end point 11C of the eleventh layer which are respectively arranged at two ends of the first inductance coil 11-L1 of the eleventh layer, the first inner end point 11A of the eleventh layer is connected with a common port P2, and the third inner end point 11C of the eleventh layer is connected with a thirteenth point post 13; the second planar conductor is composed of a eleventh layer of second inductance coils 11-L2, a eleventh layer of second inner end point 11B and a eleventh layer of fourth inner end point 11D which are respectively arranged at two ends of the eleventh layer of second inductance coils 11-L2, the eleventh layer of second inner end point 11B is connected with the fourteenth point column 14, and the eleventh layer of fourth inner end point 11D is connected with the fifth grounding port P5.
The duplexer adopts a special structure designed by lumped parameters and is formed by combining a low-pass filter and a band-pass filter, wherein the low-pass filter mainly separates out low-frequency band signals, and the band-pass filter mainly separates out high-frequency band signals.
Claims (2)
1. An LTCC laminated sheet type duplexer is characterized by comprising a ceramic substrate, wherein a first grounding port (P1), a common port (P2), a third grounding port (P3), a high-frequency band-pass output port (P4), a fifth grounding port (P5) and a low-frequency band output port (P6) are arranged on the outer side wall of the ceramic substrate; a low-pass filter for separating low-frequency-band signals is arranged between the common port (P2) and the low-frequency-band output port (P6) in the ceramic substrate; a band-pass filter for separating out high-frequency band pass signals is arranged between the common port (P2) and the high-frequency band pass output port (P4) in the ceramic substrate; the ceramic substrate comprises 11 ceramic dielectric circuit layers in a laminated structure, wherein:
a first layer on which three mutually insulated metal planar conductors are printed, the first planar conductor being composed of a first layer of a first capacitor substrate (1-C1), a first layer of a first internal terminal (1A) connecting the first layer of the first capacitor substrate (1-C1) with a first ground port (P1), and a first layer of a fourth internal terminal (1D) connecting the first layer of the first capacitor substrate (1-C1) with a fifth ground port (P5); the second planar conductor is composed of a first layer of a second capacitor substrate (1-C2), a first layer of a third capacitor substrate (1-C3) connected with the first layer of the second capacitor substrate (1-C2), and a first layer of a second inner terminal (1B) connected with the first layer of the second capacitor substrate (1-C2) and the common port (P2); the third planar conductor is formed of a first-layer dummy terminal (1C) connected to a third ground port (P3);
the second layer, there are four mutual insulated metal plane conductors on the second ceramic dielectric base plate, the first plane conductor is formed by the first capacitor substrate (2-C1) of the second layer, the said second layer first capacitor substrate (2-C1) is still connected with the eighteenth point post (18); the second plane conductor is composed of a second layer of second capacitor substrate (2-C2), and the second layer of second capacitor substrate (2-C2) is also connected with a twenty-first point post (21); the third planar conductor is composed of a second layer of third capacitor substrate (2-C3), and a twenty-second contact column (22) is connected with the second layer of third capacitor substrate (2-C3); the fourth plane conductor is composed of a second layer of dummy leading-out terminals (2A) connected with the high-frequency band-pass output port (P4);
the third layer is printed with eight mutually insulated metal plane conductors on a third ceramic dielectric substrate, the first plane conductor is composed of a third layer first capacitor substrate (3-C1) and a third layer fifth internal end point (3E), and the third layer fifth internal end point (3E) is connected with a low-frequency-band output port (P6); the second plane conductor is composed of a third layer of second capacitor substrate (3-C2) and a third layer of first inner terminal (3A), and the third layer of first inner terminal (3A) is connected with the first grounding port (P1); the third planar conductor is composed of a third layer of third capacitor substrate (3-C3) and a third layer of second inner terminal (3B), the third layer of second inner terminal (3B) is connected with the common port (P2); the fourth plane conductor is composed of a third layer of a fourth capacitor substrate (3-C4), and the third layer of the fourth capacitor substrate (3-C4) is also connected with a twenty-first point post (21); the fifth, sixth, seventh and eighth plane conductors are respectively composed of a third layer of first false leading-out terminal (3C), a third layer of second false leading-out terminal (3D), a third layer of first printing point column (18-1) and a third layer of second printing point column (22-1); the third layer first dummy lead-out terminal (3C) is connected with a third ground port (P3), and the third layer second dummy lead-out terminal (3D) is connected with a high-frequency band-pass output port (P4); the third layer of first printing dot columns (18-1) is a component of the eighteenth dot columns (18), and the third layer of second printing dot columns (22-1) is a component of the twenty-second dot columns (22);
a fourth layer, four mutually insulated metal plane conductors are printed on a fourth ceramic dielectric substrate, the first plane conductor is composed of a fourth layer first capacitor substrate (4-C1) and a fourth layer first inner end point (4A), and the fourth layer first inner end point (4A) is connected with a fifth grounding port (P5); the second, third and fourth plane conductors are respectively composed of a fourth layer of first printing point column (18-2), a fourth layer of second printing point column (21-1) and a fourth layer of third printing point column (22-2); a fourth layer of first printing dot columns (18-2) is a component of the eighteenth dot column (18), a fourth layer of second printing dot columns (21-1) is a component of the twenty-first dot column (21), and a fourth layer of third printing dot columns (22-2) is a component of the twenty-second dot column (22);
a fifth layer, wherein three mutually insulated metal plane conductors are printed on a fifth ceramic dielectric substrate, the first plane conductor is composed of a fifth layer first inductance coil (5-L1), and a fifth layer first internal end point (5A) and a fifth layer second internal end point (5B) which are respectively arranged at two ends of the fifth layer first inductance coil (5-L1); the second and the three plane conductors are respectively composed of a fifth layer first printing point pillar (21-3) and a fifth layer second printing point pillar (22-4); the fifth layer first internal end point (5A) and the fifth layer second internal end point (5B) are respectively connected with the eighteenth dot column (18) and the nineteenth dot column (19); a fifth layer of first printed dot columns (21-3) is a component of the twenty-first dot columns (21), and a fifth layer of second printed dot columns (22-4) is a component of the twenty-second dot columns (22);
a sixth layer, wherein four mutually insulated metal plane conductors are printed on a sixth ceramic dielectric substrate, and the first plane conductor consists of a sixth layer of first inductance coil (6-L1), and a sixth layer of first internal end point (6A) and a sixth layer of second internal end point (6B) which are respectively arranged at two ends of the sixth layer of first inductance coil (6-L1); the first inner end point (6A) of the sixth layer is connected with the seventeenth point column (17), and the second inner end point (6B) of the sixth layer is connected with the nineteenth point column (19); the second plane conductor is composed of a sixth layer of second inductance coil (6-L2), a sixth layer of third inner end point (6C) and a sixth layer of fourth inner end point (6D) which are respectively arranged at two ends of the sixth layer of second inductance coil (6-L2); a sixth layer of third internal end points (6C) and a sixth layer of fourth internal end points (6D) are respectively connected with the twenty-second pointed columns (20) and the twenty-second pointed columns (22); the third and the fourth plane conductors are respectively composed of a fourth printing point column (18-5) and a fifth printing point column (21-5); a fourth printed dot column (18-5) is a component of the eighteenth dot column (18), and a fifth printed dot column (21-5) is a component of the twenty-first dot column (21);
a seventh layer, wherein four mutually insulated metal plane conductors are printed on a seventh ceramic dielectric substrate, the first plane conductor is composed of a seventh layer first inductance coil (7-L1), and a seventh layer first internal endpoint (7A) and a seventh layer second internal endpoint (7B) which are respectively arranged at two ends of the seventh layer first inductance coil (7-L1), the seventh layer first internal endpoint (7A) is connected with a low-frequency-band output port (P6), and the seventh layer second internal endpoint (7B) is connected with a seventeenth point column (17); the second plane conductor is composed of a seventh layer of second inductance coil (7-L2) and a seventh layer of fourth inner end point (7D) arranged at the tail end of the seventh layer of second inductance coil (7-L2), the seventh layer of fourth inner end point (7D) is connected with a high-frequency band-pass output port (P4), and the head end of the seventh layer of second inductance coil (7-L2) is connected with a twentieth post (20); the third and the fourth plane conductors are respectively composed of a sixth printing point column (18-7) and a seventh printing point column (21-7); a sixth printed dot column (18-7) is a component of the eighteenth dot column (18), and a seventh printed dot column (21-7) is a component of the twenty-first dot column (21);
an eighth layer, wherein two mutually insulated metal plane conductors are printed on an eighth ceramic dielectric substrate, the first plane conductor is formed by an eighth layer of first inductance coil (8-L1), and two ends of the eighth layer of first inductance coil (8-L1) are respectively connected with an eighteenth point column (18) and a sixteenth point column (16); the second plane conductor is composed of an eighth layer of second inductance coil (8-L2), and two ends of the eighth layer of second inductance coil (8-L2) are respectively connected with the twelfth point post (12) and the twenty-first point post (21);
a ninth layer, wherein two mutually insulated metal plane conductors are printed on a ninth ceramic dielectric substrate, the first plane conductor is composed of a ninth layer of first inductance coil (9-L1), and a ninth layer of first inner end point (9A) and a ninth layer of second inner end point (9B) which are respectively arranged at two ends of the ninth layer of first inductance coil (9-L1), and the ninth layer of first inner end point (9A) and the ninth layer of second inner end point (9B) are respectively connected with a sixteenth dot column (16) and a fifteenth dot column (15); the second plane conductor is composed of a ninth layer of second inductance coil (9-L2), a ninth layer of third inner end point (9C) and a ninth layer of fourth inner end point (9D) which are respectively arranged at two ends of the ninth layer of second inductance coil (9-L2), and the ninth layer of third inner end point (9C) and the ninth layer of fourth inner end point (9D) are respectively connected with the twelfth point column (12) and the twenty-third point column (23);
a tenth layer, wherein two mutually insulated metal plane conductors are printed on a tenth ceramic dielectric substrate, the first plane conductor consists of a tenth layer of first inductance coil (10-L1), and a tenth layer of first inner end point (10A) and a tenth layer of second inner end point (10B) which are respectively arranged at two ends of the tenth layer of first inductance coil (10-L1), and the tenth layer of first inner end point (10A) and the tenth layer of second inner end point (10B) are respectively connected with a thirteenth point column (13) and a fifteenth point column (15); the second plane conductor is composed of a tenth layer of second inductance coil (10-L2), a tenth layer of third inner end point (10C) and a tenth layer of fourth inner end point (10D) which are respectively arranged at two ends of the tenth layer of second inductance coil (10-L2), and the tenth layer of third inner end point (10C) and the tenth layer of fourth inner end point (10D) are respectively connected with the fourteenth point column (14) and the twenty-third point column (23);
the eleventh layer is printed with two mutually insulated metal planar conductors on the eleventh ceramic dielectric substrate, the first planar conductor consists of a eleventh layer first inductance coil (11-L1), and a eleventh layer first inner end point (11A) and a eleventh layer third inner end point (11C) which are respectively arranged at two ends of the eleventh layer first inductance coil (11-L1), the eleventh layer first inner end point (11A) is connected with a common port (P2), and the eleventh layer third inner end point (11C) is connected with a thirteenth point column (13); the second plane conductor is composed of a eleventh layer second inductance coil (11-L2), a eleventh layer second inner end point (11B) and a eleventh layer fourth inner end point (11D) which are respectively arranged at two ends of the eleventh layer second inductance coil (11-L2), the eleventh layer second inner end point (11B) is connected with the fourteenth point column (14), and the eleventh layer fourth inner end point (11D) is connected with the fifth grounding port (P5).
2. The LTCC stacked chip duplexer of claim 1, wherein: the first grounding port (P1), the common port (P2) and the third grounding port (P3) are arranged on the front outer side wall of the ceramic substrate; the high-frequency band-pass output port (P4), the fifth grounding port (P5) and the low-frequency band output port (P6) are arranged on the rear outer side wall of the ceramic substrate.
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| CN110544822B (en) * | 2018-11-16 | 2020-08-25 | 西安电子科技大学 | Ka-band miniaturized filtering antenna based on SIW structure |
| CN109286383B (en) * | 2018-12-11 | 2023-11-17 | 深圳市麦捷微电子科技股份有限公司 | Novel dielectric ceramic low-pass filter |
| CN110768640B (en) * | 2019-12-11 | 2024-09-13 | 深圳市麦捷微电子科技股份有限公司 | Multilayer ceramic dielectric sheet type duplexer |
| CN111010106B (en) * | 2019-12-20 | 2023-02-28 | 深圳市麦捷微电子科技股份有限公司 | Miniaturized lamination formula low pass filter |
| CN111010107B (en) * | 2019-12-23 | 2023-07-21 | 深圳市麦捷微电子科技股份有限公司 | Miniaturized lamination sheet type coupling band-pass filter |
| CN111130480B (en) * | 2019-12-27 | 2024-06-21 | 深圳市麦捷微电子科技股份有限公司 | Laminated low-pass filter |
| CN111525904B (en) * | 2020-03-12 | 2023-09-01 | 深圳市麦捷微电子科技股份有限公司 | Laminated high-pass filter |
| CN112272014B (en) * | 2020-11-02 | 2023-04-25 | 电子科技大学 | Mixed medium frequency divider |
| CN114362707A (en) * | 2021-12-09 | 2022-04-15 | 电子科技大学长三角研究院(湖州) | LTCC miniaturized duplexer |
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