CN108633175B

CN108633175B - Circuit board stacking structure and manufacturing method thereof

Info

Publication number: CN108633175B
Application number: CN201710177173.4A
Authority: CN
Inventors: 杨凯铭; 李建财; 柯正达
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2017-03-23
Filing date: 2017-03-23
Publication date: 2020-08-28
Anticipated expiration: 2037-03-23
Also published as: CN108633175A

Abstract

The invention discloses a circuit board stacking structure and a manufacturing method thereof. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer, wherein the second circuit layer is made of copper. The via hole is arranged in the first dielectric layer, wherein the via hole is connected with the first circuit layer and the second circuit layer. The second dielectric layer is arranged on the first dielectric layer and the second circuit layer, wherein the second dielectric layer is provided with a plurality of openings, a plurality of convex parts and a flat part, the openings expose part of the second circuit layer, and the convex parts are connected with the flat part and respectively surround the openings. The patterned seed layer is disposed on the protruding portion, wherein the patterned seed layer is made of copper. The temperature and pressure required by the invention during the bonding process can be effectively reduced, thereby increasing the stability of the whole structure.

Description

Circuit board stacking structure and manufacturing method thereof

Technical Field

The invention relates to a circuit board stacking structure and a manufacturing method thereof.

Background

With the rapid development of the electronic industry, electronic products gradually enter into the direction of multi-functional and high-performance research and development. To meet the requirements of high Integration and Miniaturization of semiconductor devices, the requirements of circuit boards are increasing. For example, the Trace Pitch (Pitch) on the circuit board is required to be smaller and thinner. When the lead spacing and the thickness of the circuit board are smaller and smaller, the process yield is easily interfered by various external factors. For example, if the circuit board is subjected to high temperatures during the manufacturing process, the structural stability may be affected due to the different thermal expansion coefficients of the various layers.

In order to further improve various characteristics of the circuit board, the related art is not developed at all. How to provide a circuit board with better characteristics belongs to one of the important research and development issues, and becomes the object of the related field needing to be improved.

Disclosure of Invention

An objective of the present invention is to provide a stacked structure and a method for fabricating the same, so as to increase the overall structural stability.

According to an embodiment of the present invention, a circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of vias, a second dielectric layer, and a patterned seed layer. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer, wherein the second circuit layer is made of copper. The via hole is arranged in the first dielectric layer, wherein the via hole is connected with the first circuit layer and the second circuit layer. The second dielectric layer is arranged on the first dielectric layer and the second circuit layer, wherein the second dielectric layer is provided with a plurality of openings, a plurality of convex parts and a flat part, the openings expose part of the second circuit layer, and the convex parts are connected with the flat part and respectively surround the openings. The patterned seed layer is disposed on the protruding portion, wherein the patterned seed layer is made of copper.

In one or more embodiments of the present invention, the patterned seed layer is further disposed on the sidewalls of the opening.

In one or more embodiments of the present invention, the wiring board further comprises an auxiliary bonding layer. The auxiliary bonding layer is arranged on the patterned seed layer, wherein the auxiliary bonding layer is made of copper.

In one or more embodiments of the present invention, the material of the second dielectric layer is polyimide, but not limited thereto.

In one or more embodiments of the present invention, the convex portions each have an arc-shaped top surface.

According to another embodiment of the present invention, a stacked structure includes the circuit board and the chip module. The chip module comprises a body and a plurality of bumps. The bump is arranged on the body, wherein the bump is made of copper, and the bump, the second circuit layer and the patterned seed layer are mutually connected to form a plurality of integral structures.

In one or more embodiments of the present invention, the height of the bump is greater than or equal to the maximum height of the convex portion.

In one or more embodiments of the invention, the width of the portion of the unitary structure disposed within the opening is less than the width of the portion of the unitary structure disposed outside of the opening.

According to another embodiment of the present invention, a method for manufacturing a circuit board includes the following steps. Firstly, a first circuit layer, a second circuit layer, a plurality of via holes and a first dielectric layer are respectively formed, wherein the first circuit layer is arranged in the first dielectric layer, the second circuit layer is arranged on the first dielectric layer, the via holes are arranged in the first dielectric layer, the via holes are connected with the first circuit layer and the second circuit layer, and the second circuit layer is made of copper. Then, a second dielectric layer is formed on the first dielectric layer and on the second circuit layer. Then, a plurality of openings are formed in the second dielectric layer to expose a portion of the second circuit layer. And finally, baking the second dielectric layer to enable the second dielectric layer to form a plurality of protruding parts and flat parts, wherein the protruding parts are connected with the flat parts and respectively surround the openings. And finally, forming a patterned seed layer on the raised parts, wherein the material of the patterned seed layer is copper.

In one or more embodiments of the present invention, the method for manufacturing a circuit board further includes forming an auxiliary bonding layer on the patterned seed layer, where the auxiliary bonding layer is made of copper.

By using the bump, the patterned seed layer and the second circuit layer made of the same copper as the bonding material, the bump, the patterned seed layer and the second circuit layer are not cracked due to the difference of the thermal expansion degree because the thermal expansion coefficients of the bump, the patterned seed layer and the second circuit layer are not different. Furthermore, when the bump and the patterned seed layer are bonded, the bump will press the patterned seed layer, thereby generating a driving force, so that the diffusion speed of the copper atoms in the bump and the patterned seed layer can be effectively increased.

In addition, when the bump enters the opening, because the maximum width of the bump is smaller than that of the opening, high stress is generated at the joint, so that the bump, the patterned seed layer and the circuit layer at the joint are softened due to temperature rise, and then crystal lattices are diffused again to be aligned and jointed. Thus, the temperature and pressure required to be applied during the bonding process can be effectively reduced. Meanwhile, the stacked structure does not need to bear higher temperature and pressure, so the overall structural stability of the stacked structure can be effectively improved.

Finally, by using the above-mentioned method for bonding, surface planarization and complex surface treatment are not required, so that the contact resistance and impedance can be reduced, and the reliability and bonding strength of the contact can be increased.

Drawings

Fig. 1A to fig. 1H are schematic cross-sectional views illustrating steps of a circuit board manufacturing process according to an embodiment of the invention.

Fig. 1I and 1J are schematic cross-sectional views illustrating steps in a process of forming a stacked structure according to an embodiment of the invention.

Fig. 2A to 2C are schematic cross-sectional views illustrating a step in a process of manufacturing a circuit board according to another embodiment of the invention.

Detailed Description

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. Relative terms are used to describe different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements will be described as being "on" other elements would then be oriented "on" other elements. The exemplary word "lower" may encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary words "below" or "beneath" may encompass both an orientation of "above" and "below".

Fig. 1A to fig. 1H are schematic cross-sectional views illustrating steps of a process of a circuit board 100 according to an embodiment of the invention. First, as shown in fig. 1A, a carrier 101 is provided.

As shown in fig. 1B, a bonding metal layer 102 is formed on the carrier 101. Then, a pad layer 103 is formed on the bonding metal layer 102. Finally, the pad layer 103 is patterned to form a plurality of pads 104. Specifically, the bonding metal layer 102 may be made of titanium, and the pad layer 103 may be made of copper. The bonding metal layer 102 and the pad layer 103 may be formed by sputtering.

As shown in fig. 1C,

dielectric layers

111, 112, 113, circuit layers 121, 122, 123 and a plurality of via

holes

131, 132 are formed respectively. The dielectric layer 111 is disposed on the bonding metal layer 102. The pads 104 are disposed in the dielectric layer 111. The circuit layer 121 is disposed on the dielectric layer 111 and in the dielectric layer 112, and the circuit layer 121 is connected to the pad 104. The dielectric layer 112 is disposed on the dielectric layer 111 and the circuit layer 121. The circuit layer 122 is disposed on the dielectric layer 112 and in the dielectric layer 113. The via hole 131 is disposed in the dielectric layer 112, and the via hole 131 connects the circuit layers 121 and 122. The dielectric layer 113 is disposed on the dielectric layer 112 and the circuit layer 122. The circuit layer 123 is disposed on the dielectric layer 113. The via hole 132 is disposed in the dielectric layer 113, and the via hole 132 connects the circuit layers 122 and 123. Specifically, the material of the circuit layers 121, 122, 123 and the

vias

131, 132 may be copper.

As shown in fig. 1D, a dielectric layer 114, a circuit layer 124 and a plurality of via holes 133 are formed respectively. The dielectric layer 114 is disposed on the dielectric layer 113 and the circuit layer 123. The circuit layer 124 is disposed on the dielectric layer 114, the via 133 is disposed in the dielectric layer 114, and the via 133 connects the circuit layer 123 and the circuit layer 124. Specifically, the material of the circuit layer 124 and the via 133 may be copper.

As shown in fig. 1E, a dielectric layer 115 is formed on the dielectric layer 114 and the circuit layer 124. Then, a plurality of openings 115o are formed in the dielectric layer 115 to expose a portion of the circuit layer 124. The forming method of the opening 115o may be laser drilling.

Then, the dielectric layer 115 is baked to form a plurality of raised portions 115r and flat portions 115f on the dielectric layer 115, wherein the raised portions 115r connect the flat portions 115f and surround the openings 115 o. Specifically, the convex portions 115r have arc-shaped top surfaces 115rt, respectively.

As shown in fig. 1F, a seed layer 141 is formed on the exposed circuit layer 124, the sidewalls of the opening 115o, and the top surface of the dielectric layer 115 (i.e., on the exposed circuit layer 124 and the flat portion 115F and the raised portion 115r of the dielectric layer 115). Specifically, the seed layer 141 is at least partially formed on the arc-shaped top surface 115 rt. In addition, the material of the seed layer 141 may be copper.

As shown in fig. 1G, a photoresist 901 is formed over the opening 115o and over the raised portion 115r (on the seed layer 141). Specifically, the photoresist 901 covers the opening 115o and the seed layer 141 disposed on the convex portion 115r, and the photoresist 901 exposes the seed layer 141 disposed on the flat portion 115 f.

As shown in fig. 1G and fig. 1H, the seed layer 141 not covered by the photoresist 901 is removed, thereby forming the patterned seed layer 142. Then, the photoresist 901 is removed.

Fig. 1I and 1J are schematic cross-sectional views illustrating steps in the process of fabricating a stacked structure 300 according to an embodiment of the invention. As shown in fig. 1I, the circuit board 100 and the chip module 200 are provided, wherein the bumps 201 of the chip module 200 may be made of copper.

As shown in fig. 1I and 1J, the bump 201 is bonded to the patterned seed layer 142 and the circuit layer 124, such that the bump 201, the circuit layer 124 and the patterned seed layer 142 are bonded to each other to form an integral structure 191.

The bump 201, the patterned seed layer 142, and the circuit layer 124, which are both copper, are bonded by bonding the wiring board 100 and the wafer module 200, and a stacked structure 300 is formed. Therefore, since the thermal expansion coefficients of the bump 201, the patterned seed layer 142 and the circuit layer 124 are not different, when the stacked structure 300 has different temperatures, the bump 201, the patterned seed layer 142 and the circuit layer 124 are not cracked due to the difference of the thermal expansion degrees, and the structural stability of the stacked structure 300 can be effectively increased.

Further, when the bump 201 and the patterned seed layer 142 are bonded, the bump 201 will press the patterned seed layer 142, so as to generate a driving force, such that the diffusion speed of the copper atoms in the bump 201 and the patterned seed layer 142 can be effectively increased, and thus the bump 201 and the patterned seed layer 142 form an integral structure after contacting and exchanging the copper atoms with each other. Furthermore, the bump 201, the circuit layer 124 and the patterned seed layer 142 are bonded to form the whole structure 191.

Specifically, the maximum width of the bump 201 is smaller than the maximum width of the opening 115 o. Therefore, it is ensured that the bump 201 can be pressed against the inclined surface of the patterned seed layer 142 during bonding, so as to effectively increase the diffusion rate of copper atoms. Further, when the bump 201 enters the opening 115o, since the maximum width of the bump 201 is smaller than the maximum width of the opening 115o, high stress is generated at the joint, so that the bump 201, the patterned seed layer 142 and the circuit layer 124 at the joint are softened by the temperature rise, and the crystal lattice is re-diffused to align and join. Thus, the temperature and pressure required to be applied during the bonding process can be effectively reduced. At the same time, since the stacked structure 300 does not need to withstand higher temperature and pressure, the overall structural stability of the stacked structure 300 can be effectively improved.

In addition, the bonding method does not need surface planarization and complex surface treatment, thereby reducing contact resistance and impedance and increasing contact reliability and bonding strength.

Specifically, the temperature required for the bonding process may be 120 to 250 degrees celsius, and the pressure required for the bonding process may be 3 to 9 Mpa. In some embodiments, the temperature required for the bonding process may be 160 to 200 degrees celsius, and the pressure required for the bonding process may be about 6 Mpa.

Fig. 2A to 2C are schematic cross-sectional views illustrating one step of a process of manufacturing the circuit board 100 according to another embodiment of the invention. As shown in fig. 2A to 2C, the present embodiment is basically the same as the previous embodiment, and the differences are mainly described below.

As shown in fig. 2A, a photoresist 901 is formed over the flat portion 115f (on the seed layer 141). Thus, the photoresist 901 exposes the opening 115o and the seed layer 141 disposed on the convex portion 115r, and the photoresist 901 covers the seed layer 141 disposed on the flat portion 115 f.

As shown in fig. 2B, an auxiliary bonding layer 151 is formed on the exposed seed layer 141, wherein the auxiliary bonding layer 151 is made of copper.

As shown in fig. 2B and 2C, the photoresist 901 is removed. Then, the seed layer 141 not covered by the auxiliary bonding layer 151 is removed, thereby forming the patterned seed layer 142 (the patterned seed layer 142 is disposed on the arc-shaped top surface 115rt of the convex portion 115 r). Thus, the auxiliary bonding layer 151 is formed on the patterned seed layer 142.

When bonding the bump 201 (see fig. 1I) to the patterned seed layer 142, high stress may be generated at the bond because the bump 201 will press against the patterned seed layer 142. By forming the auxiliary bonding layer 151 on the patterned seed layer 142, the structure of the joint can be strengthened, thereby avoiding high stress damage to the joint structure and its surrounding structures (e.g., adjacent dielectric layer 115).

Specifically, the

dielectric layers

111, 112, 113, 114, 115 may be formed by means of pressing. In some embodiments, the

dielectric layers

111, 112, 113, 114, and 115 are made of polyimide, but not limited thereto.

Specifically, the circuit layers 121, 122, 123, and 124 may be formed by first forming a photoresist layer (not shown) such as a dry film on the

dielectric layers

111, 112, 113, and 114, patterning the photoresist layer by a photolithography process to expose a portion of the

dielectric layers

111, 112, 113, and 114, and then performing an electroplating process and a photoresist layer removal process. Forming the via holes 131, 132, 133 may be forming blind holes (which may be formed by laser drilling) in the

dielectric layers

112, 113, 114 before forming the line layers 122, 123, 124, and then forming the via holes 131, 132, 133 by electroplating while forming the line layers 122, 123, 124.

It should be noted here that the number of the dielectric layers and the circuit layers may vary according to the actual requirements of the circuit board 100, and is not necessarily limited to the description of the foregoing embodiments.

Another embodiment of the present invention provides a circuit board 100. As shown in fig. 1H, the circuit board 100 includes a carrier 101, a bonding metal layer 102, a plurality of pads 104,

dielectric layers

111, 112, 113, 114, 115, circuit layers 121, 122, 123, 124, a plurality of via holes 131, a plurality of via holes 132, a plurality of via holes 133, and a patterned seed layer 142.

The bonding metal layer 102 is disposed on the carrier 101. The dielectric layer 111 is disposed on the bonding metal layer 102. The pad 104 is disposed on the bonding metal layer 102 and in the dielectric layer 111. The dielectric layer 112 is disposed on the dielectric layer 111 and the circuit layer 121. The circuit layer 121 is disposed in the dielectric layer 112 and on the dielectric layer 111. The dielectric layer 113 is disposed on the dielectric layer 112 and the circuit layer 122. The circuit layer 122 is disposed in the dielectric layer 113 and on the dielectric layer 112. The via hole 131 is disposed in the dielectric layer 112, wherein the via hole 131 connects the circuit layer 121 and the circuit layer 122. The dielectric layer 114 is disposed on the dielectric layer 113 and the circuit layer 123. The circuit layer 123 is disposed in the dielectric layer 114 and on the dielectric layer 113. The via hole 132 is disposed in the dielectric layer 113, wherein the via hole 132 connects the circuit layer 122 and the circuit layer 123. Dielectric layer 115 is disposed on dielectric layer 114 and on circuit layer 124. The circuit layer 124 is disposed in the dielectric layer 115 and on the dielectric layer 114, wherein the circuit layer 124 is made of copper. The via hole 133 is disposed in the dielectric layer 114, wherein the via hole 133 connects the circuit layer 123 and the circuit layer 124. The dielectric layer 115 has a plurality of openings 115o, a plurality of raised portions 115r, and a flat portion 115 f. The opening 115o exposes a portion of the wiring layer 124. The convex portions 115r connect the flat portions 115f and surround the openings 115o, respectively. The patterned seed layer 142 is disposed on the raised portions 115r, wherein the patterned seed layer 142 is made of copper.

Specifically, the patterned seed layer 142 is also disposed on the sidewalls of the opening 115 o. It should be understood that the above-mentioned embodiments of the patterned seed layer 142 are only examples and are not intended to limit the present invention, and those skilled in the art should be able to flexibly select the embodiments of the patterned seed layer 142 according to the actual requirements.

Specifically, the convex portions 115r have arc-shaped top surfaces 115rt, respectively, and the arc-shaped top surfaces 115rt are not coplanar with the top surfaces 115ft of the flat portions 115 f. Further, an included angle is formed between the top surface 115ft and the arc-shaped top surface 115rt, and the included angle is larger than 90 degrees. In addition, the set height of the arc-shaped top surface 115rt is substantially greater than the set height of the top surface 115 ft.

The patterned seed layer 142 is disposed on the raised portions 115 r. It should be understood that the above embodiments of the raised portions 115r and the patterned seed layer 142 are only exemplary and not intended to limit the present invention, and those skilled in the art can flexibly select the embodiments of the raised portions 115r and the patterned seed layer 142 according to the actual requirements.

Yet another embodiment of the present invention provides a stacked structure 300. As shown in fig. 1I and 1J, the stacked structure 300 includes a circuit board 100 and a chip module 200. The wafer module 200 includes a body 202 and a plurality of bumps 201. The bump 201 is disposed on the body 202, wherein the bump 201 is made of copper. The bump 201, the circuit layer 124 and the patterned seed layer 142 are bonded to each other to form a plurality of integrated structures 191.

Specifically, the height of the bump 201 is greater than or equal to the maximum height of the convex portion 115 r. In some embodiments, the height of bumps 201 is about 6 microns.

Specifically, the width of the portion of the integrated structure 191 disposed in the opening 115o is smaller than the width of the portion of the integrated structure 191 disposed outside the opening 115 o.

Yet another embodiment of the present invention provides a circuit board 100. As shown in fig. 2C, the circuit board 100 of the present embodiment is substantially the same as the circuit board 100 of fig. 1H, and the main difference is that the circuit board 100 further includes an auxiliary bonding layer 151. The auxiliary bonding layer 151 is disposed on the patterned seed layer 142, wherein the auxiliary bonding layer 151 is made of copper.

By bonding the bump 201, the patterned seed layer 142 and the circuit layer 124, which are made of copper, the bump 201, the patterned seed layer 142 and the circuit layer 124 do not have different thermal expansion coefficients, and thus the bump 201, the patterned seed layer 142 and the circuit layer 124 are not cracked due to the difference in thermal expansion degree. Further, when the bump 201 and the patterned seed layer 142 are bonded, the bump 201 will press against the patterned seed layer 142, thereby generating a driving force, so that the diffusion speed of the copper atoms in the bump 201 and the patterned seed layer 142 can be effectively increased.

In addition, when the bump 201 enters the opening 115o, since the maximum width of the bump 201 is smaller than the maximum width of the opening 115o, high stress is generated at the junction, so that the bump 201, the patterned seed layer 142 and the circuit layer 124 at the junction are softened by the temperature rise, and the crystal lattice is re-diffused to be aligned and bonded. Thus, the temperature and pressure required to be applied during the bonding process can be effectively reduced. At the same time, since the stacked structure 300 does not need to withstand higher temperature and pressure, the overall structural stability of the stacked structure 300 can be effectively improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A circuit board, comprising:

a first dielectric layer;

a first circuit layer disposed in the first dielectric layer;

a second circuit layer disposed on the first dielectric layer, wherein the second circuit layer is made of copper;

a plurality of via holes disposed in the first dielectric layer, wherein the plurality of via holes connect the first circuit layer and the second circuit layer;

a second dielectric layer disposed on the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a plurality of openings, a plurality of protruding portions and a flat portion, the plurality of openings expose a portion of the second circuit layer, the plurality of protruding portions connect the flat portion, and the plurality of protruding portions surround the plurality of openings respectively; and

and the patterned seed layer is arranged on the plurality of convex parts, and the material of the patterned seed layer is copper.

2. The wiring board of claim 1, wherein the patterned seed layer is further disposed on sidewalls of the plurality of openings.

3. The wiring board of claim 1, further comprising:

and the auxiliary bonding layer is arranged on the patterned seed layer, and the auxiliary bonding layer is made of copper.

4. The wiring board of claim 1, wherein the second dielectric layer is made of polyimide.

5. The wiring board of claim 1, wherein each of the plurality of raised portions has an arc-shaped top surface.

6. A stacked structure, comprising:

the wiring board of claim 1; and

a wafer module, comprising:

a body; and

and a plurality of bumps disposed on the body, wherein the bumps are made of copper, and the bumps, the second circuit layer and the patterned seed layer are bonded to each other to form a plurality of integral structures.

7. The stack structure of claim 6, wherein a height of the plurality of bumps is greater than or equal to a maximum height of the plurality of raised portions.

8. The stack structure of claim 6, wherein a width of a portion of the plurality of unitary structures disposed in the plurality of openings is less than a width of a portion of the plurality of unitary structures disposed outside the plurality of openings.

9. A method of making a circuit board, comprising:

respectively forming a first circuit layer, a second circuit layer, a plurality of via holes and a first dielectric layer, wherein the first circuit layer is arranged in the first dielectric layer, the second circuit layer is arranged on the first dielectric layer, the via holes are arranged in the first dielectric layer, the via holes are connected with the first circuit layer and the second circuit layer, and the second circuit layer is made of copper;

forming a second dielectric layer on the first dielectric layer and on the second circuit layer;

forming a plurality of openings in the second dielectric layer to expose portions of the second circuit layer;

baking the second dielectric layer to enable the second dielectric layer to form a plurality of protruding portions and a flat portion, wherein the protruding portions are connected with the flat portion, and the protruding portions respectively surround the openings; and

and forming a patterned seed layer on the plurality of raised parts, wherein the material of the patterned seed layer is copper.

10. The method of manufacturing a wiring board of claim 9, further comprising:

and forming an auxiliary bonding layer on the patterned seed layer, wherein the auxiliary bonding layer is made of copper.