CN108633175B - Circuit board stacking structure and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a circuit board stacking structure and a manufacturing method thereof, wherein the circuit board comprises a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of vias, a second dielectric layer and a patterned seed layer. The first circuit layer is arranged in the first dielectric layer. The second circuit layer is arranged on the first dielectric layer, wherein the material of the second circuit layer is copper. The via is arranged in the first dielectric layer, wherein the via connects the first circuit layer and the second circuit layer. The second dielectric layer is arranged on the first dielectric layer and on the second circuit layer, wherein the second dielectric layer has a plurality of openings, a plurality of raised portions and a flat portion, wherein the opening exposes a portion of the second circuit layer, and the raised portion connects the flat portion and surrounds the opening respectively. The patterned seed layer is arranged on the raised portion, wherein the material of the patterned seed layer is copper. The temperature and pressure required for the bonding process of the present invention can be effectively reduced, thereby increasing the overall structural stability thereof.

Description

Circuit board stacking structure and manufacturing method thereof

technical field

The present invention relates to a circuit board stack structure and a manufacturing method thereof.

Background technique

With the vigorous development of the electronic industry, electronic products have gradually entered the research and development direction of multi-functional and high-performance. In order to meet the requirements of high integration and miniaturization of semiconductor components, various requirements of circuit boards are also getting higher and higher. For example, the wire (Trace) pitch (Pitch) on the circuit board is required to be smaller and smaller, and the thickness of the circuit board is required to be thinner and thinner. At the same time as the wire spacing and thickness of the circuit board are getting smaller and smaller, the process qualification rate is also more easily disturbed by various external factors. For example, if the circuit board is subjected to high temperatures during the process, the structural stability may be affected due to the different thermal expansion coefficients of the various layers.

In order to further improve the characteristics of the circuit board, the related fields have made great efforts to develop. How to provide a circuit board with better characteristics is one of the important research and development issues at present, and it has also become an urgent need for improvement in the current related fields.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a stacked structure and a manufacturing method thereof to increase the overall structural stability thereof.

According to an embodiment of the present invention, a circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of vias, a second dielectric layer, and a patterned seed layer. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer, wherein the material of the second circuit layer is copper. The via hole is disposed in the first dielectric layer, wherein the via hole connects the first circuit layer and the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a plurality of openings, a plurality of protruding parts and a flat part, the openings expose a part of the second circuit layer, and the protruding parts are Parts connect the flat parts and surround the openings, respectively. The patterned seed layer is disposed on the raised portion, wherein the material of the patterned seed layer is copper.

In one or more embodiments of the present invention, the patterned seed layer is also disposed on the sidewall of the opening.

In one or more embodiments of the present invention, the circuit board further includes an auxiliary bonding layer. The auxiliary bonding layer is disposed on the patterned seed layer, wherein the material of the auxiliary bonding layer is copper.

In one or more embodiments of the present invention, the material of the second dielectric layer is polyimide, which is not limited thereto.

In one or more embodiments of the present invention, the raised portions have arcuate top surfaces, respectively.

According to another embodiment of the present invention, a stacked structure includes the aforementioned circuit board and chip module. The chip module includes a body and a plurality of bumps. The bumps are arranged on the body, wherein the bumps are made of copper, and the bumps, the second circuit layer and the patterned seed layer are bonded to each other to form a plurality of integral structures.

In one or more embodiments of the present invention, the height of the bump is greater than or equal to the maximum height of the raised portion.

In one or more embodiments of the invention, the width of the portion of the monolithic structure disposed in the opening is smaller than the width of the portion of the monolithic structure disposed outside the opening.

According to yet another embodiment of the present invention, a manufacturing method of a circuit board includes the following steps. First, a first circuit layer, a second circuit layer, a plurality of via holes and a first dielectric layer are respectively formed, wherein the first circuit layer is disposed in the first dielectric layer, and the second circuit layer is disposed in the first dielectric layer On the layer, the via hole is arranged in the first dielectric layer, wherein the via hole connects the first circuit layer and the second circuit layer, and the material of the second circuit layer is copper. Then, a second dielectric layer is formed on the first dielectric layer and the second wiring layer. Next, a plurality of openings are formed in the second dielectric layer to expose part of the second circuit layer. Afterwards, the second dielectric layer is baked, so that the second dielectric layer forms a plurality of raised portions and flat portions, the raised portions are connected to the flat portions and respectively surround the openings. Finally, a patterned seed layer is formed on the raised portion, wherein the material of the patterned seed layer is copper.

In one or more embodiments of the present invention, the manufacturing method of the circuit board further includes forming an auxiliary bonding layer on the patterned seed layer, wherein the material of the auxiliary bonding layer is copper.

By bonding the bumps, the patterned seed layer and the second circuit layer with the same copper material, because the thermal expansion coefficients of the bumps, the patterned seed layer and the second circuit layer are not different, the bumps, the patterned seed layer and the second circuit layer are not different. The second circuit layers do not break due to differences in the degree of thermal expansion. Further, when the bumps and the patterned seed layer are joined together, the bumps will press the patterned seed layer, thereby generating a driving force, so that the diffusion speed of the copper atoms in the bumps and the patterned seed layer can be effectively increased.

In addition, when the bump enters the opening, because the maximum width of the bump is smaller than the maximum width of the opening, high stress will be generated at the joint, thus causing the bump, patterned seed layer and circuit layer at the joint to be heated due to heating. It softens, and the lattice is re-diffused to align and join. Therefore, the external temperature and pressure required for the bonding process can be effectively reduced. At the same time, because the stacked structure does not need to withstand high temperature and pressure, the overall structural stability of the stacked structure can be effectively improved.

Finally, by using the above-mentioned bonding method, surface planarization and complicated surface treatment will not be required, so the contact resistance and resistance will be reduced, and the contact reliability and bonding strength will be increased at the same time.

Description of drawings

1A to 1H are schematic cross-sectional views illustrating various steps of a circuit board process according to an embodiment of the present invention.

FIG. 1I and FIG. 1J are schematic cross-sectional views of each process step of the stacked structure according to an embodiment of the present invention.

2A to 2C are schematic cross-sectional views illustrating one step of a process of a circuit board according to another embodiment of the present invention.

Detailed ways

Various embodiments of the present invention will be disclosed below with accompanying drawings, and for the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the invention, these practical details are unnecessary. In addition, for the purpose of simplifying the drawings, some well-known and conventional structures and elements are shown in a simplified and schematic manner in the drawings.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," are used to describe one element's relationship to another element as illustrated herein in the figures. It will be understood that relative terms are used to describe different orientations of the device than those depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of the other elements would then be oriented on the "upper" side of the other elements. The exemplary word "lower" may encompass both "lower" and "upper" orientations depending on the particular orientation of the drawings. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary word "below" or "below" can encompass both an orientation of "above" and "below."

1A to 1H are schematic cross-sectional views illustrating various steps of the process of the circuit board 100 according to an embodiment of the present invention. First, as shown in FIG. 1A , a carrier board 101 is provided.

As shown in FIG. 1B , a bonding metal layer 102 is formed on the carrier board 101 . Then, a pad layer 103 is formed on the bonding metal layer 102 . Finally, the pad layer 103 is patterned to form a plurality of pads 104 . Specifically, the material of the bonding metal layer 102 may be titanium, and the material of the pad layer 103 may be copper. A method for forming the bonding metal layer 102 and the pad layer 103 may be sputtering.

As shown in FIG. 1C , dielectric layers 111 , 112 , 113 , circuit layers 121 , 122 , 123 and a plurality of vias 131 , 132 are respectively formed. The dielectric layer 111 is disposed on the bonding metal layer 102 . The pads 104 are disposed in the dielectric layer 111 . The circuit layer 121 is disposed on the dielectric layer 111 and in the dielectric layer 112 , and the circuit layer 121 is connected to the pads 104 . The dielectric layer 112 is disposed on the dielectric layer 111 and the circuit layer 121 . The wiring layer 122 is disposed on the dielectric layer 112 and in the dielectric layer 113 . The via hole 131 is disposed in the dielectric layer 112 , and the via hole 131 is connected to the circuit layers 121 and 122 . The dielectric layer 113 is disposed on the dielectric layer 112 and the circuit layer 122 . The wiring layer 123 is disposed on the dielectric layer 113 . The via hole 132 is disposed in the dielectric layer 113 , and the via hole 132 is connected to the circuit layers 122 and 123 . Specifically, the material of the circuit layers 121 , 122 , 123 and the via holes 131 , 132 may be copper.

As shown in FIG. 1D , a dielectric layer 114 , a circuit layer 124 and a plurality of vias 133 are respectively formed. The dielectric layer 114 is disposed on the dielectric layer 113 and the circuit layer 123 . The circuit layer 124 is disposed on the dielectric layer 114 , the via hole 133 is disposed in the dielectric layer 114 , and the via hole 133 connects the circuit layer 123 and the circuit layer 124 . Specifically, the material of the circuit layer 124 and the via hole 133 may be copper.

As shown in FIG. 1E , a dielectric layer 115 is formed on the dielectric layer 114 and the wiring layer 124 . Then, a plurality of openings 115o are formed in the dielectric layer 115 to expose part of the circuit layer 124 . A method of forming the opening 115o may be laser drilling.

Then, the dielectric layer 115 is baked, so that the dielectric layer 115 forms a plurality of raised portions 115r and flat portions 115f, the raised portions 115r are connected to the flat portions 115f and respectively surround the openings 115o. Specifically, the convex portions 115r have arc-shaped top surfaces 115rt, respectively.

As shown in FIG. 1F , on the exposed circuit layer 124 , the sidewalls of the opening 115o and the top surface of the dielectric layer 115 (ie, the exposed circuit layer 124 and the flat portion 115f and the convex portion of the dielectric layer 115 ) 115r) to form a seed layer 141. Specifically, the seed layer 141 is formed at least partially on the arc-shaped top surface 115rt. In addition, the material of the seed layer 141 may be copper.

As shown in FIG. 1G, a photoresist 901 is formed over the opening 115o and over the raised portion 115r (on the seed layer 141). Specifically, the photoresist 901 covers the opening 115o and the seed layer 141 disposed on the convex portion 115r, and the photoresist 901 exposes the seed layer 141 disposed on the flat portion 115f.

As shown in FIGS. 1G and 1H , the seed layer 141 not covered by the photoresist 901 is removed, thereby forming a patterned seed layer 142 . Then, the photoresist 901 is removed.

FIG. 1I and FIG. 1J are schematic cross-sectional views of each process step of the stacked structure 300 according to an embodiment of the present invention. As shown in FIG. 1I , the aforementioned circuit board 100 and the chip module 200 are provided, wherein the material of the plurality of bumps 201 of the chip module 200 can be copper.

As shown in FIGS. 1I and 1J , the bumps 201 are bonded to the patterned seed layer 142 and the circuit layer 124 , so that the bumps 201 , the circuit layer 124 and the patterned seed layer 142 are bonded to each other to form the overall structure 191 .

The circuit board 100 and the chip module 200 are bonded to form the stacked structure 300 by bonding the bumps 201 , the patterned seed layer 142 and the circuit layer 124 with the same copper material. Therefore, since the thermal expansion coefficients of the bumps 201 , the patterned seed layer 142 and the wiring layer 124 are not different, when the stacked structure 300 has different temperatures, the bumps 201 , the patterned seed layer 142 and the wiring layer 124 are not separated from each other. The phenomenon of fracture will not occur due to the difference in the degree of thermal expansion, so the structural stability of the stacked structure 300 can be effectively increased.

Further, when the bumps 201 and the patterned seed layer 142 are joined together, the bumps 201 will press the patterned seed layer 142 , thereby generating a driving force, so that the copper atoms in the bumps 201 and the patterned seed layer 142 are in contact with each other. The diffusion speed can be effectively increased, so that the bumps 201 and the patterned seed layer 142 form an integral structure after contacting and exchanging copper atoms with each other. Furthermore, the bumps 201 , the circuit layer 124 and the patterned seed layer 142 will be bonded to each other to form the overall structure 191 .

Specifically, the maximum width of the bump 201 is smaller than the maximum width of the opening 115o. In this way, it can be ensured that the bumps 201 can be pressed against the slope of the patterned seed layer 142 during bonding, so as to effectively increase the diffusion speed of copper atoms. Further, when the bumps 201 enter the openings 115o, since the maximum width of the bumps 201 is smaller than the maximum width of the openings 115o, high stress will be generated at the joints, so that the bumps 201 and patterned seeds at the joints will be generated. The layer 142 and the wiring layer 124 are softened due to the temperature increase, and the lattice is re-diffused and aligned and bonded. Therefore, the external temperature and pressure required for the bonding process can be effectively reduced. At the same time, because the stacked structure 300 does not need to withstand high temperature and pressure, the overall structural stability of the stacked structure 300 can be effectively improved.

In addition, by using the above-mentioned bonding method, surface planarization and complicated surface treatment will not be required, so the contact resistance and resistance will be reduced, and the reliability of the contact and the bonding strength will be increased at the same time.

Specifically, the temperature required for the bonding process may be 120 degrees Celsius to 250 degrees Celsius, and the pressure required for the bonding process may be 3 Mpa to 9 Mpa. In some embodiments, the temperature required for the bonding process may be 160 to 200 degrees Celsius, and the pressure required for the bonding process may be about 6 MPa.

2A to 2C are schematic cross-sectional views illustrating one step of the process of the circuit board 100 according to another embodiment of the present invention. As shown in FIGS. 2A to 2C , this embodiment is basically the same as the previous embodiment, and the differences are mainly described below.

As shown in FIG. 2A, a photoresist 901 is instead formed over the flat portion 115f (on the seed layer 141). Thus, the photoresist 901 exposes the opening 115o and the seed layer 141 disposed on the convex portion 115r, and the photoresist 901 covers the seed layer 141 disposed on the flat portion 115f.

As shown in FIG. 2B , an auxiliary bonding layer 151 is formed on the exposed seed layer 141 , wherein the material of the auxiliary bonding layer 151 is copper.

As shown in FIGS. 2B and 2C, the photoresist 901 is removed. Then, the seed layer 141 not covered by the auxiliary bonding layer 151 is removed, thereby forming a patterned seed layer 142 (the patterned seed layer 142 is disposed on the arc-shaped top surface 115rt of the convex portion 115r). Therefore, the auxiliary bonding layer 151 is formed on the patterned seed layer 142 .

When bonding the bumps 201 (see FIG. 1I ) and the patterned seed layer 142 , high stress is generated at the joints because the bumps 201 will press the patterned seed layer 142 . By forming the auxiliary bonding layer 151 on the patterned seed layer 142, the structure of the junction can be strengthened, thereby avoiding the occurrence of high stress damage to the junction structure and its surrounding structures (eg, the adjacent dielectric layer 115).

Specifically, the dielectric layers 111 , 112 , 113 , 114 and 115 may be formed by pressing. In addition, in some embodiments, the dielectric layers 111 , 112 , 113 , 114 , and 115 are made of polyimide, which is not limited thereto.

Specifically, the method for forming the circuit layers 121 , 122 , 123 and 124 is to form a photoresist layer (not shown) such as a dry film on the dielectric layers 111 , 112 , 113 and 114 Partially exposed dielectric layers 111 , 112 , 113 , 114 are patterned by a lithography process, and then formed by an electroplating process and a photoresist layer removal process. The via holes 131, 132, 133 are formed by forming blind vias (which can be formed by laser drilling) in the dielectric layers 112, 113, 114 before forming the circuit layers 122, 123, 124, and then forming the circuit layers The via holes 131 , 132 and 133 are formed by simultaneous electroplating of 122 , 123 and 124 .

It should be noted here that the numbers of the dielectric layers and the circuit layers can be changed according to the actual requirements of the circuit board 100 , and are not necessarily limited to the descriptions of the foregoing embodiments.

Another embodiment of the present invention provides a circuit board 100 . As shown in FIG. 1H , the circuit board 100 includes a carrier board 101 , a bonding metal layer 102 , a plurality of pads 104 , dielectric layers 111 , 112 , 113 , 114 , 115 , circuit layers 121 , 122 , 123 , 124 , and many more. A plurality of via holes 131 , a plurality of via holes 132 , a plurality of via holes 133 , and a patterned seed layer 142 .

The bonding metal layer 102 is disposed on the carrier board 101 . The dielectric layer 111 is disposed on the bonding metal layer 102 . The pads 104 are disposed on the bonding metal layer 102 and in the dielectric layer 111 . The dielectric layer 112 is disposed on the dielectric layer 111 and the circuit layer 121 . The wiring layer 121 is disposed in the dielectric layer 112 and on the dielectric layer 111 . The dielectric layer 113 is disposed on the dielectric layer 112 and the circuit layer 122 . The wiring layer 122 is disposed in the dielectric layer 113 and on the dielectric layer 112 . The via hole 131 is disposed in the dielectric layer 112 , wherein the via hole 131 connects the circuit layer 121 and the circuit layer 122 . The dielectric layer 114 is disposed on the dielectric layer 113 and the circuit layer 123 . The wiring layer 123 is disposed in the dielectric layer 114 and on the dielectric layer 113 . The via hole 132 is disposed in the dielectric layer 113 , wherein the via hole 132 connects the circuit layer 122 and the circuit layer 123 . The dielectric layer 115 is disposed on the dielectric layer 114 and the circuit layer 124 . The circuit layer 124 is disposed in the dielectric layer 115 and on the dielectric layer 114 , wherein the material of the circuit layer 124 is copper. The via hole 133 is disposed in the dielectric layer 114 , wherein the via hole 133 connects the wiring layer 123 and the wiring layer 124 . The dielectric layer 115 has a plurality of openings 115o, a plurality of raised portions 115r, and a flat portion 115f. The opening 115o exposes part of the circuit layer 124 . The raised portions 115r connect the flat portions 115f and surround the openings 115o, respectively. The patterned seed layer 142 is disposed on the raised portion 115r, wherein the material of the patterned seed layer 142 is copper.

Specifically, the patterned seed layer 142 is also disposed on the sidewall of the opening 115o. It should be understood that the above-mentioned specific embodiments of the patterned seed layer 142 are only examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should flexibly select the patterned seed layer 142 according to actual needs. Detailed ways.

Specifically, the convex portions 115r respectively have arc-shaped top surfaces 115rt, and the arc-shaped top surfaces 115rt and the top surface 115ft of the flat portion 115f are not coplanar. Further, there is an included angle between the top surface 115ft and the arc-shaped top surface 115rt, and the angle of the included angle is greater than 90 degrees. In addition, the setting height of the arc top surface 115rt is substantially larger than the setting height of the top surface 115ft.

The patterned seed layer 142 is disposed on the raised portion 115r. It should be understood that the specific embodiments of the protruding portion 115r and the patterned seed layer 142 mentioned above are only examples, and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should flexibly select the protruding portion according to actual needs. A specific embodiment of the raised portion 115r and the patterned seed layer 142 is shown.

Yet another embodiment of the present invention provides a stack structure 300 . As shown in FIGS. 1I and 1J , the stacked structure 300 includes the circuit board 100 and the chip module 200 . The chip module 200 includes a body 202 and a plurality of bumps 201 . The bump 201 is disposed on the body 202 , wherein the material of the bump 201 is copper. The bumps 201 , the circuit layer 124 and the patterned seed layer 142 are bonded to each other to form a plurality of integral structures 191 .

Specifically, the height of the bump 201 is greater than or equal to the maximum height of the raised portion 115r. In some embodiments, the height of the bumps 201 is about 6 microns.

Specifically, the width of the portion of the integral structure 191 disposed in the opening 115o is smaller than the width of the portion of the integral structure 191 disposed outside the opening 115o.

Yet another embodiment of the present invention provides a circuit board 100 . As shown in FIG. 2C , the circuit board 100 of this embodiment is substantially the same as the circuit board 100 of FIG. 1H , and the main difference is that the circuit board 100 further includes an auxiliary bonding layer 151 . The auxiliary bonding layer 151 is disposed on the patterned seed layer 142 , wherein the material of the auxiliary bonding layer 151 is copper.

By bonding the bumps 201 , the patterned seed layer 142 and the circuit layer 124 whose materials are all copper, because the thermal expansion coefficients of the bumps 201 , the patterned seed layer 142 and the circuit layer 124 are not different, the bumps 201 , the patterned There is no fracture phenomenon between the seed layer 142 and the circuit layer 124 due to the difference in the degree of thermal expansion. Further, when the bumps 201 and the patterned seed layer 142 are joined together, the bumps 201 will press the patterned seed layer 142 , thereby generating a driving force, so that the copper atoms in the bumps 201 and the patterned seed layer 142 are in contact with each other. Diffusion speed can be effectively increased.

In addition, when the bumps 201 enter the openings 115o, since the maximum width of the bumps 201 is smaller than the maximum width of the openings 115o, high stress will be generated at the joints, so that the bumps 201 and the patterned seed layer 142 at the joints will be damaged. The wiring layer 124 is softened due to the temperature rise, and the lattice is re-diffused to form an alignment and bonding. Therefore, the external temperature and pressure required for the bonding process can be effectively reduced. At the same time, because the stacked structure 300 does not need to withstand high temperature and pressure, the overall structural stability of the stacked structure 300 can be effectively improved.

Finally, by using the above-mentioned bonding method, surface planarization and complicated surface treatment will not be required, so the contact resistance and resistance will be reduced, and the contact reliability and bonding strength will be increased at the same time.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention should be determined by the claims.

Claims (10)

1. A circuit board, comprising:

a first dielectric layer;

a first circuit layer disposed in the first dielectric layer;

a second circuit layer disposed on the first dielectric layer, wherein the second circuit layer is made of copper;

a plurality of via holes disposed in the first dielectric layer, wherein the plurality of via holes connect the first circuit layer and the second circuit layer;

a second dielectric layer disposed on the first dielectric layer and the second circuit layer, wherein the second dielectric layer has a plurality of openings, a plurality of protruding portions and a flat portion, the plurality of openings expose a portion of the second circuit layer, the plurality of protruding portions connect the flat portion, and the plurality of protruding portions surround the plurality of openings respectively; and

and the patterned seed layer is arranged on the plurality of convex parts, and the material of the patterned seed layer is copper.

2. The wiring board of claim 1, wherein the patterned seed layer is further disposed on sidewalls of the plurality of openings.

3. The wiring board of claim 1, further comprising:

and the auxiliary bonding layer is arranged on the patterned seed layer, and the auxiliary bonding layer is made of copper.

4. The wiring board of claim 1, wherein the second dielectric layer is made of polyimide.

5. The wiring board of claim 1, wherein each of the plurality of raised portions has an arc-shaped top surface.

6. A stacked structure, comprising:

the wiring board of claim 1; and

a wafer module, comprising:

a body; and

and a plurality of bumps disposed on the body, wherein the bumps are made of copper, and the bumps, the second circuit layer and the patterned seed layer are bonded to each other to form a plurality of integral structures.

7. The stack structure of claim 6, wherein a height of the plurality of bumps is greater than or equal to a maximum height of the plurality of raised portions.

8. The stack structure of claim 6, wherein a width of a portion of the plurality of unitary structures disposed in the plurality of openings is less than a width of a portion of the plurality of unitary structures disposed outside the plurality of openings.

9. A method of making a circuit board, comprising:

respectively forming a first circuit layer, a second circuit layer, a plurality of via holes and a first dielectric layer, wherein the first circuit layer is arranged in the first dielectric layer, the second circuit layer is arranged on the first dielectric layer, the via holes are arranged in the first dielectric layer, the via holes are connected with the first circuit layer and the second circuit layer, and the second circuit layer is made of copper;

forming a second dielectric layer on the first dielectric layer and on the second circuit layer;

forming a plurality of openings in the second dielectric layer to expose portions of the second circuit layer;

baking the second dielectric layer to enable the second dielectric layer to form a plurality of protruding portions and a flat portion, wherein the protruding portions are connected with the flat portion, and the protruding portions respectively surround the openings; and

and forming a patterned seed layer on the plurality of raised parts, wherein the material of the patterned seed layer is copper.

10. The method of manufacturing a wiring board of claim 9, further comprising:

and forming an auxiliary bonding layer on the patterned seed layer, wherein the auxiliary bonding layer is made of copper.

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