CN108630720B

CN108630720B - Light emitting diode array

Info

Publication number: CN108630720B
Application number: CN201810358864.9A
Authority: CN
Inventors: 杨宗宪; 巫汉敏; 王志贤; 陈怡名; 徐子杰
Original assignee: Epistar Corp
Current assignee: Epistar Corp
Priority date: 2012-09-06
Filing date: 2012-09-06
Publication date: 2023-01-03
Anticipated expiration: 2032-09-06
Also published as: CN103681724B; CN103681724A; CN108630720A

Abstract

The invention provides a light emitting diode array, which comprises a first light emitting diode, a second light emitting diode and a second isolation channel; the first light-emitting diode comprises a first area, a second area, a first isolation channel and an electrode connecting layer; the first isolation channel is positioned between the first area and the second area and comprises an electrode insulating layer; the electrode connecting layer coats the first region; the second light emitting diode comprises a semiconductor lamination and a second electric welding pad; the second electrical bonding pad is positioned on the semiconductor lamination; the second isolation channel is located between the first light emitting diode and the second light emitting diode and comprises an electrical connection structure which is electrically connected with the first light emitting diode and the second light emitting diode.

Description

Light emitting diode array

The invention relates to a divisional application of a Chinese invention patent application (application number: 201210328231.6, application date: 2012, 9 and 6, and the name of the invention: a light emitting diode array).

Technical Field

The invention relates to a light emitting diode array.

Background

Light emitting diodes are a widely used light source in semiconductor devices. Compared with the traditional incandescent bulb or fluorescent tube, the light emitting diode has the characteristics of power saving and longer service life, so the light emitting diode is gradually substituted for the traditional light source to be applied to various fields, such as industries of traffic signs, backlight modules, street lamp illumination, medical equipment and the like.

With the increasing demand for brightness in the application and development of led light sources, how to increase the luminous efficiency of led light sources to increase the brightness thereof becomes an important direction of the common efforts in the industry.

Fig. 14 depicts a prior art LED package 300 for a semiconductor light emitting element: including a semiconductor LED chip 2 encapsulated by a package structure 1, wherein the semiconductor LED chip 2 has a p-n junction 3, the package structure 1 is typically a thermosetting material, such as epoxy or thermal plastic. The semiconductor LED chip 2 is connected to two conductive supports 5, 6 through a bonding wire (wire) 4. Since epoxy resin (epoxy) is easily degraded at high temperature and easily causes a leakage phenomenon, it can be operated only in a low temperature environment. In addition, epoxy resin (epoxy) has high thermal resistance (thermal resistance), so that the structure of fig. 14 only provides a high-resistance thermal dissipation path for the semiconductor LED chip 2, which limits the low-power applications of the LED package 1.

Disclosure of Invention

In view of the above, the present invention provides a light emitting diode array capable of improving a leakage phenomenon.

The invention provides a light emitting diode array, which comprises a first light emitting diode, a second light emitting diode and a second isolation channel; the first light emitting diode comprises a first area, a second area, a first isolation channel and an electrode connecting layer; the first isolation channel is positioned between the first area and the second area and comprises an electrode insulating layer; the electrode connecting layer coats the first region; the second light emitting diode comprises a semiconductor lamination and a second electric welding pad; the second electrical bonding pad is positioned on the semiconductor lamination; the second isolation channel is located between the first light emitting diode and the second light emitting diode and comprises an electrical connection structure which is electrically connected with the first light emitting diode and the second light emitting diode.

In addition, the invention also provides a light-emitting diode array, which comprises a substrate, a plurality of light-emitting diodes, a plurality of conductive wiring structures, two electrical welding pads and an isolation channel; the substrate has a first surface; the plurality of light emitting diodes are positioned on the first surface; the plurality of conductive wiring structures are arranged on the first surface and electrically connected with the light-emitting diodes; the two electric welding pads are positioned on the first surface; the isolation channel is located between any one of the electrical bonding pads and any one of the light emitting diodes, wherein the distance between the electrical bonding pad and the light emitting diode is not less than 25 μm.

Drawings

Fig. 1 to 12 are schematic cross-sectional views of a light emitting diode array structure according to a first embodiment of the invention.

Fig. 13 is a top view of a second embodiment of the light emitting diode array of the present invention.

Fig. 14 is a structural view of a conventional light emitting element.

Detailed Description

In order to make the description of the present invention more detailed and complete, please refer to the following description in conjunction with fig. 1-13. The steps of manufacturing the led array 1000 according to the first embodiment of the invention are as follows:

referring to fig. 1, a growth substrate 10, such as a gaas substrate, is provided; a plurality of light emitting diodes are epitaxially grown directly on the substrate. In the present embodiment, the number of the led units is 100 and 200, but the number is not limited thereto. Each of the light emitting diodes includes a first conductive type contact layer 11, a first conductive type semiconductor layer 12, an active layer 13, and a second conductive type semiconductor layer 14, as shown in fig. 2. Wherein the first conductive type contact layer 11 may be n-type gallium arsenide (n-GaAs); the materials of the first conductive type semiconductor layer 12, the active layer 13, and the second conductive type semiconductor layer 14 respectively include one or more of the following elements: gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and silicon (Si); for example, gallium phosphide (GaP) or aluminum gallium indium phosphide (AlGaInP).

On the second conductive type semiconductor layer 14, electrode structures are formed in selective regions by evaporation, for example: at least one second electrical electrode 15b and a plurality of second electrical extension electrodes 15c. After a temporary substrate 16 is bonded to the electrodes, the growth substrate 10 is removed, as shown in FIGS. 3 and 4; wherein the temporary substrate 16 may be glass. The first conductive type contact layer 11 is partially removed by photolithography and etching processes to form a plurality of dot structures and expose a portion of the lower surface 12a of the first conductive type semiconductor layer 12, and then an electrical connection layer 17 is formed under the portion of the lower surface 12a and the plurality of dot structures of the first conductive type contact layer 11, as shown in fig. 5. The second conductive electrodes 15b and the second conductive extension electrodes 15c may be made of materials selected from: chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), tungsten (W), tin (Sn), or silver (Ag). The material of the electrical connection layer 17 may be germanium/gold.

The lower surface 12a of the first conductive type semiconductor layer 12 is etched to a rough plane by wet etching, as shown in fig. 6. Additionally providing a permanent substrate 18, such as an alumina substrate; and a bonding layer 19 is formed on the substrate to form the structure shown in FIG. 7; or forming a bonding layer 19 (not shown) on the lower surface 12a of the first conductive type semiconductor layer 12, bonding the permanent substrate 18 under the lower surface 12a of the first conductive type semiconductor layer 12 by the bonding layer 19 to integrate the structures shown in fig. 6 and 7, and interposing the plurality of first conductive contact layer dot-shaped structures 11 and the electrical connection layer 17 between the lower surface 12a of the first conductive type semiconductor layer 12 and the bonding layer 19, as shown in fig. 8. The temporary substrate 16 is removed to expose the second electrical electrodes 15b, the second electrical extension electrodes 15c and a portion of the upper surface 14a of the second conductive type semiconductor layer 14, as shown in fig. 9. Dry Etching the second conductive type semiconductor layer 14 and the active layer 13 from top to bottom by using an Inductively Coupled Plasma Reactive Ion Etching System (Inductively Coupled Plasma Etching System) until a portion of the surface of the first conductive type semiconductor layer 12 is exposed to form a first isolation channel 20 and a second isolation channel 21; the first isolation channel 20 separates the first light emitting diode 100 into a first region 50A and a second region 50B, and the distance between the two regions is not less than 25 μm. The second isolation channel 21 is located between the first light emitting diode 100 and the second light emitting diode 200. The upper surface 14a of the second conductive type semiconductor layer 14 is etched to a rough surface by dry etching or wet etching, as shown in fig. 10. Then, the inductively coupled plasma ion etching system is used to etch and remove part of the first conductive type semiconductor layer 12 in the second isolation channel 21. Due to the difference in the dry etching rates between the previous and subsequent steps, the sidewalls of the second conductive type semiconductor layer 14, the active layer 13, and the first conductive type semiconductor layer 12 in the second isolation channel 21 are formed in a step shape, as shown in fig. 11.

An electrode insulating layer 22 is formed on the first isolation channel 20 along the sidewall of the second region 50B by evaporation, and the height of the electrode insulating layer 22 is greater than the height of the sidewall of the second region 50B. In the second isolation channel 21, an insulating structure 23 is formed along a portion of the upper surface and the sidewall of the second region 50B by evaporation, and another insulating structure 23 is formed along a portion of the upper surface and the sidewall of the second light emitting diode 200 by evaporation, wherein the material of the electrode insulating layer 22 and the insulating structure 23 may be a dielectric material such as silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or titanium oxide. An electrode connecting layer 26 is formed to cover the sidewall and the upper surface of the first region 50A, wherein the electrode connecting layer 26 may be made of ti-au. Since the electrode connection layer 26 cannot form an electrical ohmic contact with the first conductive type semiconductor layer 12, the active layer 13 and the second conductive type semiconductor layer 14 of the first light emitting diode 100, the electrical ohmic contact with the first conductive type semiconductor layer 12 can be formed only through the electrical connection layer 17. Forming an electrical connection structure 24 in the second isolation channel 21 above the insulation structure 23, on the sidewall of the second region 50B and at the bottom of the second isolation channel 21; wherein the second conductive type semiconductor layer 14 of the first light emitting diode 100 is electrically connected in series with the first conductive type semiconductor layer 12 of the second light emitting diode 200 through the electrical connection structure 24 and the electrical connection layer 17. A second electrical bonding pad 25 is formed on the second electrical electrode 15 b. In addition, the electrode connection layer 26 can be used as a first electrical bonding pad, and when the electrode connection layer 26 and the second electrical bonding pad 25 are electrically connected by an external power source (not shown), the current provided by the external power source can flow from the electrode connection layer 26 through the electrical connection layer 17, through the first conductive type semiconductor layer 12, the active layer 13, and the second conductive type semiconductor layer 14 of the light emitting diode 100, and then through the electrical connection structure 24 to the light emitting diode 200. The electrode connecting layer 26 and the electrical connecting structure 24 can be formed by evaporation at the same time as the second electrical bonding pad 25, and the composition materials can be the same. After the above steps, an led array 1000 having two leds (100, 200) connected in series is formed. The light emitting diode 100 is divided into a first area 50A and a second area 50B by the first isolation channel 20; wherein the first region 50A is surrounded by an electrode connecting layer 26. The second electrical bonding pad 25 is disposed on a portion of the upper surface 14a of the second light emitting diode 200, and the upper surface of the electrode connecting layer 26 and the upper surface of the second electrical bonding pad 25 may be at the same level.

Fig. 13 is a top view of a light emitting diode array 2000 according to a second embodiment of the present invention, which is a light emitting diode array including 10 light emitting diodes, such as a first light emitting diode 100 and a second light emitting diode 200, electrically connected in series. As shown in fig. 13, the led array 2000 includes a substrate 30 having a first surface 30a; the light emitting diode (100, 200) is positioned on the first surface 30a; a plurality of conductive wiring structures 40 disposed on the first surface 30a and electrically connected to the light emitting diodes; two electrical bonding pads (50, 60) are disposed on the first surface 30a, and the two electrical bonding pads (50, 60) are electrically connected to an external power source (not shown); an isolation channel 70 is located between any one of the electrical bonding pads (50, 60) and any one of the light emitting diodes (100, 200); wherein the distance between the electrical bonding pad (50, 60) and the light emitting diode (100, 200) is not less than 25 μm. When the distance between the electrical bonding pad (50, 60) and the light emitting diode (100, 200) is too small, semiconductor material is likely to remain on the sidewall of the light emitting diode (100, 200) during the etching step of the light emitting diode (100, 200), thereby causing leakage. This phenomenon is improved by forming an electrode insulation layer 80 on the sidewalls of the light emitting diodes (100, 200) in the isolation channel 70. The substrate 30 is a supporting base and may include a conductive substrate, a non-conductive substrate, a transparent substrate or an opaque substrate.

The first conductive type semiconductor layer 12 and the second conductive type semiconductor layer 14 are different in electrical property, polarity or dopant of at least two portions thereof, or are single-layered or multi-layered semiconductor materials (multi-layered means two or more layers, hereinafter the same) for providing electrons and holes, respectively, and the electrical property thereof may be selected from a combination of at least any two of p-type, n-type and i-type. The active layer 13 is located between the first conductive type semiconductor layer 12 and the second conductive type semiconductor layer 14, and is a region where conversion between electrical energy and optical energy is possible or induced.

The light emitting spectrum of the light emitting diode according to the embodiment of the invention can be adjusted by changing the physical or chemical elements of the semiconductor single layer or the semiconductor multiple layers. Commonly used materials are, for example, aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide (Zn 0) series, and the like. The structure of the active layer (not shown) is as follows: single Heterostructure (SH), double Heterostructure (DH), double-side double heterostructure (DDH), or multi-quantum well (MQW). Moreover, the emission wavelength can be changed by adjusting the logarithm of the quantum wells.

In an embodiment of the invention, a buffer layer (not shown) is further included between the first conductive contact layer 11 and the growth substrate 10. The buffer layer is interposed between the two material systems to "transition" the material system of the substrate to that of the semiconductor system. For the structure of the led, on one hand, the buffer layer is a material layer for reducing lattice mismatch between two materials. On the other hand, the buffer layer may be a single layer, a multilayer or a structure for combining two materials or two separate structures, which may be selected from materials such as: organic materials, inorganic materials, metals, semiconductors, and the like; the optional structure is as follows: a reflective layer, a heat conductive layer, a conductive layer, an anti-deformation layer, a stress release (stress release) layer, a stress adjustment (stress adjustment) layer, a bonding layer, a wavelength conversion layer, a mechanical fixing structure, and the like. In one embodiment, the material of the buffer Layer may be AlN, gaN, gaInP, inP, gaAs, alAs, and the formation method may be sputtering (Sputter) or Atomic Layer Deposition (ALD).

A second conductive type contact layer (not shown) may be further selectively formed on the second conductive type semiconductor layer 14. The contact layer is provided on the side of the second conductivity type semiconductor layer away from the active layer 13. Specifically, the second conductive type contact layer may be an optical layer, an electrical layer, or a combination of both thereof. The optical layer may modify electromagnetic radiation or light from or into the active layer (not shown). As used herein, "altering" refers to altering at least one optical property of electromagnetic radiation or light, including, but not limited to, frequency, wavelength, intensity, flux, efficiency, color temperature, color rendering index, light field, and angle of view. The electrical layer is capable of changing or tending to change the value, density, distribution of at least one of voltage, resistance, current, capacitance between any set of opposing sides of the second conductivity type contact layer. The second conductive contact layer is made of a material including at least one of an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmitting metal, a metal having a transmittance of 50% or more, an organic substance, an inorganic substance, a fluorescent substance, a phosphorescent substance, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer of the second conductivity type is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. If a relatively light-transmissive metal, the thickness is about 0.005 μm to about 0.6. Mu.m.

While the drawings and description correspond to particular embodiments, respectively, the elements, implementations, design rules, and principles of the various embodiments may be arbitrarily referenced, exchanged, matched, coordinated, or combined as desired, unless otherwise clearly contradicted, contradicted or difficult to combine by itself.

Although the invention has been described with reference to particular embodiments, it is not intended to limit the scope, sequence, or use of the materials or process steps. Various modifications and alterations of this invention can be made without departing from the spirit and scope of this invention.

Claims

1. An led array, comprising:

a semiconductor stack comprising a first region and a second region, the first region having an upper surface, the second region having a first sidewall, the first region having a second sidewall;

a first isolation channel formed between the first region and the second region;

a second isolation channel formed in the semiconductor stack;

an insulating layer formed in the first isolation channel and covering the first sidewall;

an electrical connection layer located under the semiconductor stack layer; and

an electrode connecting layer directly contacting the electrical connecting layer and covering the upper surface and the second sidewall of the first region;

wherein, the electrical connection layer and the insulation layer are overlapped with each other in a vertical direction.

2. The light emitting diode array of claim 1, wherein the electrical connection layer and the first region overlap each other in the vertical direction.

3. The light emitting diode array of claim 1, wherein the second region further has a third sidewall, the insulating layer covering the third sidewall.

4. The light emitting diode array of claim 1, wherein the semiconductor stack comprises a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer in sequence.

5. The light emitting diode array of claim 4, wherein the first conductive type semiconductor layer has a width greater than the second conductive type semiconductor layer.

6. The light emitting diode array of claim 4, wherein the lower surface of the first conductive type semiconductor layer is a rough surface.

7. The light emitting diode array of claim 1, wherein the semiconductor stack further comprises a third region, the second isolation trench being formed between the second region and the third region.

8. The light emitting diode array of claim 1, further comprising a substrate underlying the stack of semiconductor layers.

9. The light emitting diode array of claim 8, further comprising a bonding layer bonding the substrate and the stack of semiconductor layers.

10. The light emitting diode array of claim 7, further comprising an electrical bonding pad on the third region.

11. The light-emitting diode array of claim 1, wherein the electrical connection layer and the second isolation channel overlap each other in the vertical direction.

12. The light emitting diode array of claim 1, wherein the second region has an upper surface, and the insulating layer covers the upper surface of the second region.