CN108598164A - 一种GaN基增强型功率电子器件及其制作方法 - Google Patents
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Abstract
一种GaN基增强型功率电子器件及其制作方法,所述电子器件自下而上依次包括衬底、GaN外延层、背势垒层、GaN沟道层和势垒层,所述势垒层上形成有源极、栅极和漏极,所述源极、栅极和漏极之间的所述势垒层上沉积有钝化层;其中所述背势垒层和势垒层独立地选自AlGaN、AlInN或者AlInGaN。本发明可以显著提高GaN基增强型器件的阈值电压,提高大尺寸增强型GaN基功率电子器件的良率和阈值均匀性。
Description
技术领域
本发明属于半导体技术领域,具体涉及一种GaN基增强型功率电子器件及其制作方法。
背景技术
增强型是功率电子器件安全工作的核心要求。目前国际上主要有四种技术实现AlGaN/GaN基增强型器件:1)栅槽刻蚀减薄AlGaN势垒层;2)在AlGaN势垒层中注入带负电的氟离子;3)在势垒层表面生长P-(Al)GaN盖帽层;4)在势垒层表面生长InGaN或厚GaN反极化层。通过以上技术尽管能实现增强型,但器件的阈值局限在+3V以下。为了突破GaN基功率电子器件的阈值瓶颈,拓展其在高压功率电子领域的应用,亟需通过设计新型增强型材料和器件结构,将GaN基增强型器件的阈值提高到+3V以上。
发明内容
为了解决现有技术中存在的问题,本发明提出了一种GaN基增强型功率电子器件及制作方法,用于提高GaN基增强型器件的阈值电压。
为了达到上述目的,一方面,本发明提出了一种GaN基增强型功率电子器件,自下而上依次包括衬底、GaN外延层、背势垒层、GaN沟道层和势垒层,所述势垒层上形成有源极、栅极和漏极,所述源极、栅极和漏极之间的所述势垒层上沉积有钝化层;
其中所述背势垒层和势垒层独立地选自AlGaN、AlInN或者AlInGaN。
优选地,所述背势垒层为AlGaN或者AlInN,其中Al组分是固定的,Al组分的含量介于0-100mol.%之间。
优选地,所述背势垒层为AlGaN或者AlInN,其中Al组分自下而上逐渐减小或逐渐增大,从y mol.%降低或升高到x mol.%,其中x,y介于0-100之间。
优选地,所述背势垒层为AlInGaN,Al,In和Ga组分随厚度是固定的,或者逐渐增加或减小。
优选地,所述背势垒层的厚度为1-1000nm。
优选地,所述势垒层的厚度为0-10nm。
优选地,所述钝化层选自AlN、SiO2或SiNx。
优选地,所述栅极和所述势垒层之间形成有栅介质层或没有栅介质层。另一方面,本发明提出了一种GaN基增强型功率电子器件的制作方法,包括:
在衬底的GaN外延层生长背势垒层;
在所述背势垒层上生长高晶体质量的GaN沟道层;
在所述GaN沟道层上生长势垒层;
在所述势垒层上形成钝化层;
刻蚀所述钝化层,然后制作源极、栅极和漏极;
在所述源极、栅极和漏极之间的所述势垒层上形成钝化层。
优选地,所述背势垒层采用MOCVD,MBE或HVPE方法制备。
优选地,所述钝化层通过MOCVD、LPCVD、PECVD或者ALD制备。
优选地,所述制作方法还包括在栅极下方形成栅介质层的步骤。
与现有技术相比,利用本发明具有以下有益效果:
1、本发明采用Al(In,Ga)N背势垒层的反极化效应抬高GaN沟道层的导带,以进一步耗尽Al(In,Ga)N/GaN异质结沟道中的二维电子气,从而显著提高GaN基增强型器件的阈值电压;
2、本发明采用薄势垒Al(In,Ga)N/GaN异质结构实现了无刻蚀的增强型栅结构,提高了大尺寸增强型GaN基功率电子器件的良率和阈值均匀性,推动了GaN基功率电子器件的应用进程。
附图说明
图1为本发明一实施例的GaN基增强型功率电子器件结构示意图;
图2为本发明另一实施例的GaN基增强型功率电子器件结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明作进一步的详细说明。
本发明公开了一种带有Al(In,Ga)N背势垒结构的GaN基增强型功率电子器件结构及制作方法。其中的制作方法包括:先在较厚的GaN外延层上生长一薄层Al(In,Ga)N BackBarrier(背势垒层),紧接着生长一层高晶体质量GaN层,最后生长Al(In,Ga)N超薄势垒层,从而形成增强型Al(In,Ga)N/GaN异质结构材料,最后在该材料结构上制备源极,栅介质,栅极和漏极,以及钝化层,形成晶体管结构。
所述Al(In,Ga)N背势垒层是采用MOCVD,MBE或HVPE方法制备的,厚度介于1nm至1000nm。
Al(In,Ga)N背势垒层可以是AlGaN或AlInN三元合金层,或者是AlInGaN四元合金。
Al(In,Ga)N背势垒层若是AlGaN三元合金层,其Al组分介于0和100%之间。
Al(In,Ga)N背势垒层若是AlGaN三元合金层,其Al组分可以是固定的,介于0和100%之间某一个数值;也可以是从下至上逐渐递减或增加,从y%降低或升高到x%,其中x,y介于0和100之间。
Al(In,Ga)N背势垒层若是AlInN三元合金层,其Al组分介于0%和100%之间。
Al(In,Ga)N背势垒层若是AlInN三元合金层,其Al组分可以是固定的,介于0和100%之间某一个数值;也可以是从下至上逐渐递减或增加,从y%降低或升高到x%,其中x,y介于0和100之间。
Al(In,Ga)N背势垒层若是AlInGaN四元合金层,其Al,In,Ga组分介于0和100%之间,它们随厚度可以是固定的,也可以逐渐变化的,可以是逐渐增大,也可以是逐渐减小。
所述势垒层Al(In,Ga)N/GaN异质结构中Al(In,Ga)N势垒层可以是AlGaN或AlInN三元合金层,或者是AlInGaN四元合金,厚度介于0nm至10nm。
所述的钝化层采用AlN、SiO2或SiNx材料制备,可以通过MOCVD、LPCVD、PECVD或者ALD生长制备,所述钝化层能在Al(In,Ga)N势垒层表面诱导出高密度的正电荷,显著提高Al(In,Ga)N势垒层/GaN异质结沟道中的二维电子气浓度(即栅极和源极之间,栅极和漏极之间的二维电子气),从而有效降低器件的导通电阻。
本发明借助Al(In,Ga)N背势垒层的反极化效应抬高GaN沟道层的导带,以进一步耗尽Al(In,Ga)N背势垒层/GaN异质结沟道中的二维电子气,从而显著提高GaN基增强型器件的阈值电压,推动了GaN在高阈值、大功率电力电子系统中的应用。
在本发明的一个实施例中,先在衬底1较厚的GaN外延层2上采用MOCVD生长一薄层AlInN背势垒层3,厚度为100nm,在AlInN背势垒层3上生长一层高晶体质量GaN沟道层4,最后生长AlGaN超薄势垒层5,厚度为5nm,从而形成增强型AlGaN/GaN异质结构材料,先通过LPCVD形成SiNx钝化层9,然后在该材料结构上制备源极6,栅极7和漏极8,形成晶体管结构,如图1所示,图中10为二维电子气。
在另一个实施例中,在栅极和势垒层之间还形成有栅介质层11,如图2所示。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种GaN基增强型功率电子器件,其特征在于,自下而上依次包括衬底、GaN外延层、背势垒层、GaN沟道层和势垒层,所述势垒层上形成有源极、栅极和漏极,所述源极、栅极和漏极之间的所述势垒层上沉积有钝化层;
其中所述背势垒层和势垒层独立地选自AlGaN、AlInN或者AlInGaN。
2.根据权利要求1所述的GaN基增强型功率电子器件,其中,所述背势垒层为AlGaN或者AlInN,其中Al组分是固定的,Al组分的含量介于0-100mol.%之间,或者,Al组分自下而上逐渐减小或逐渐增大,从y mol.%降低或升高到x mol.%,其中x,y介于0-100之间。
3.根据权利要求1所述的GaN基增强型功率电子器件,其中,所述背势垒层为AIInGaN,Al,In和Ga组分随厚度是固定的,或者逐渐增加或减小。
4.根据权利要求1所述的GaN基增强型功率电子器件,其中,所述背势垒层的厚度为1-1000nm,优选地,所述势垒层的厚度为0-10nm。
5.根据权利要求1所述的GaN基增强型功率电子器件,其中,所述钝化层选自AlN、SiO2或SiNx。
6.根据权利要求1所述的GaN基增强型功率电子器件,其中,所述栅极和所述势垒层之间形成有栅介质层或者没有栅介质层。
7.一种权利要求1-6任一项所述GaN基增强型功率电子器件的制作方法,包括:
在衬底的GaN外延层生长背势垒层;
在所述背势垒层上生长高晶体质量的GaN沟道层;
在所述GaN沟道层上生长势垒层;
在所述势垒层上形成钝化层;
刻蚀所述钝化层,然后制作源极、栅极和漏极。
8.根据权利要求7所述的制作方法,其中,所述背势垒层采用MOCVD,MBE或HVPE方法制备。
9.根据权利要求7所述的制作方法,其中,所述钝化层通过MOCVD、LPCVD、PECVD或者ALD制备。
10.根据权利要求7所述的制作方法,其中,所述制作方法还包括在在栅极下方形成栅介质层的步骤。
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