CN108563279B - Voltage stabilizing filter circuit and signal detection circuit - Google Patents
Voltage stabilizing filter circuit and signal detection circuit Download PDFInfo
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- CN108563279B CN108563279B CN201810759207.5A CN201810759207A CN108563279B CN 108563279 B CN108563279 B CN 108563279B CN 201810759207 A CN201810759207 A CN 201810759207A CN 108563279 B CN108563279 B CN 108563279B
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Abstract
According to the voltage stabilizing filter circuit and the signal detection circuit provided by the embodiment of the application, one end of the first filter capacitor is connected with one end of the second filter capacitor through the first RC network and the second RC network in sequence; one end of the first voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the first voltage dividing resistor is connected with a power supply; one end of the second voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the second voltage dividing resistor is grounded; the other end of the first filter capacitor is connected with the other end of the second filter capacitor through a third RC network and a fourth RC network in sequence; one end of the third voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the third voltage dividing resistor is connected with a power supply; one end of the fourth voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the fourth voltage dividing resistor is grounded.
Description
Technical Field
The application relates to the field of signal detection, in particular to a voltage stabilizing filter circuit and a signal detection circuit.
Background
In order for electronic devices (e.g., signal amplifiers, signal comparators, operational amplifiers, etc.) to operate properly during signal detection, the bias voltage of the input signal to the electronic device must be maintained within a certain range. If the bias voltage drifts due to external interference, the bias voltage is too high, and the electronic device may be disabled.
Among external disturbances, common mode transient events are common mode transient events, which refer to the operation process of communication between a transmitter circuit and a receiver circuit, wherein the voltage of the transmitter circuit is instantaneously greater than or less than that of the receiver circuit. Such as gate drivers commonly used in motor drives, inverters, there are fast transient voltages between the transmit and receive modules of the gate driver when the high voltage power transistors in the system are on/off at a fast speed. In particular, with the application of high-speed switching devices, the transient speed of the voltage is faster and faster, and the influence of the common mode transient event on the bias voltage of the transmission signal is more and more serious.
Content of the application
In view of the above, the embodiment of the application provides a voltage stabilizing filter circuit and a signal detection circuit.
In a first aspect, an embodiment of the present application provides a voltage stabilizing filter circuit, including: the first RC network, the second RC network, the third RC network, the fourth RC network, the first voltage dividing resistor, the second voltage dividing resistor, the third voltage dividing resistor, the fourth voltage dividing resistor, the first filter capacitor and the second filter capacitor; one end of the first filter capacitor is connected with one end of the second filter capacitor through the first RC network and the second RC network in sequence; one end of the first voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the first voltage dividing resistor is connected with a power supply; one end of the second voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the second voltage dividing resistor is grounded; the other end of the first filter capacitor is connected with the other end of the second filter capacitor through the third RC network and the fourth RC network in sequence; one end of the third voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the third voltage dividing resistor is connected with the power supply; one end of the fourth voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the fourth voltage dividing resistor is grounded.
In a second aspect, an embodiment of the present application provides a signal detection circuit, including a transmitter circuit, a signal processing circuit, and the voltage stabilizing filter circuit described above, where the transmitter circuit is connected to the voltage stabilizing filter circuit through a first high-voltage isolation capacitor and a second high-voltage isolation capacitor, and the voltage stabilizing filter circuit is connected to the signal processing circuit.
The voltage stabilizing filter circuit and the signal detection circuit provided by the embodiment of the application have the beneficial effects that:
The voltage stabilizing filter circuit provided by the embodiment of the application comprises: the filter circuit comprises a first RC network, a second RC network, a third RC network, a fourth RC network, a first voltage dividing resistor, a second voltage dividing resistor, a third voltage dividing resistor, a fourth voltage dividing resistor, a first filter capacitor and a second filter capacitor. One end of the first filter capacitor is connected with one end of the second filter capacitor through the first RC network and the second RC network in sequence; one end of the first voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the first voltage dividing resistor is connected with a power supply; one end of the second voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the second voltage dividing resistor is grounded; the other end of the first filter capacitor is connected with the other end of the second filter capacitor through the third RC network and the fourth RC network in sequence; one end of the third voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the third voltage dividing resistor is connected with the power supply; one end of the fourth voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the fourth voltage dividing resistor is grounded. The first filter capacitor and the second filter capacitor can restrict the drift of the bias voltage of the differential signal when the common mode transient event occurs, and can also play a role in filtering out low-frequency noise contained in the differential signal.
In order to make the above objects, features and advantages of the embodiments of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
For a clearer description of embodiments of the application or of solutions in the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a prior art signal detection circuit;
fig. 2 shows a circuit diagram of a voltage stabilizing filter circuit provided by an embodiment of the application;
FIG. 3 is a circuit diagram of a specific implementation of a voltage stabilizing filter circuit according to an embodiment of the present application;
fig. 4 is a circuit diagram of another embodiment of a voltage stabilizing filter circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing the comparison of the effects of the voltage stabilizing filter circuit provided by the present application and the prior art circuit;
FIG. 6a is a schematic diagram showing the bias voltage of the voltage stabilizing filter circuit and the prior art circuit according to the present application;
FIG. 6b is a schematic diagram of a variation waveform of a common mode voltage;
fig. 7 is a circuit diagram of a signal detection circuit according to an embodiment of the present application;
Fig. 8 is a block diagram of a signal detection circuit according to an embodiment of the present application.
Detailed Description
Referring to fig. 1, fig. 1 shows a signal detection circuit in the prior art, where a first high-voltage isolation capacitor Ca1 and a second high-voltage isolation capacitor Ca2 are capacitors between a transmitter circuit TX and a receiver circuit RX, and are connected to a detection network in the receiver circuit RX, and differential voltage signals Va1 and Va2 filtered by the detection network are used as inputs of a signal processing circuit Q. The signal processing circuit Q may be a comparator or an amplifier in general.
The detection network comprises a reference voltage Vref1, a capacitor (Cb 1/Cb 2) and a resistor (Rb 1/Rb 2) between the reference voltage and the differential voltage signal. The transmitter circuit TX divides the output signal at Vt1 by Ca1 and "parallel connection of Cb1 and Rb 1" to form signal Va1; the output signal of transmitter circuit TX at Vt2 is divided by Ca2 and "parallel connection of Cb2 and Rb 2" to form signal Va2. Since Va1 and Va2 share the same reference voltage Vref1, the differential signals on Vt1 and Vt2 are transferred to Va1 and Va2, forming differential signals isolated by Ca1 and Ca 2.
When there is a voltage transient between the transmitter circuit TX and the receiver circuit RX, the following description will be given by taking the example that the voltage of the transmitter circuit TX rises rapidly with respect to the receiver circuit RX: the capacitance of the capacitor Ca1 and the capacitance of the capacitor Ca2 are regarded as equal, namely Ca. If the voltage rises rapidly at a rate of beta kV/us (up to hundreds of kV/us). Typically Ca1 and Ca2 are much smaller than Cb1 and Cb2, so the common mode voltage is mainly borne by Ca1 and Ca 2; the magnitude of common mode currents Ia1 and Ia2 flowing through Ca1 and Ca2 is then:
Ia1＝Ia2≈βCa
Since the signal processing circuit Q generally has a large input impedance, a substantial portion of the common mode currents Ia1 and Ia2 flow into the reference voltage Vref1 through Cb1/Cb2 and Rb1/Rb 2. In order to control the quiescent current, the resistance values of the voltage dividing resistors Rf1 and Rf2 used for the reference voltage Vref1 are large, and therefore, it can be approximately considered that all the common mode current flows into the voltage stabilizing capacitor Cf. For a voltage transient event of duration Δt, the change in Vref1 can be calculated as:
cf is small (e.g., less than hundreds of pF) because of the limited on-chip capacitance of the integrated circuit. The total capacitance between the transmitter and the receiver will also approach or reach the pF order. If a voltage transient event of approximately 100kV/us is sustained for 10ns, ΔVref1 may reach several volts.
On the other hand, a portion of the common mode currents Ia1 and Ia2 will flow through resistors Rb1 and Rb2, respectively, creating a voltage drop across resistors Rb1 and Rb2, respectively, such that Va1 and Va2 create an additional increment relative to Vref 1.
Since the supply voltage of the signal processing circuit Q is typically 1V to 5V, the voltages Va1 and Va2 input as the signal processing circuit Q easily exceed the input voltage operating range of Q through the above analysis, and Q cannot process the differential signals transmitted by Va1 and Va 2. That is, during voltage transients, the receiver circuit no longer operates properly.
In order to solve the above technical problems, the embodiments of the present application provide a voltage stabilizing filter circuit and a signal detection circuit, and the voltage stabilizing filter circuit and the signal detection circuit in the embodiments of the present application will be described in detail with reference to the accompanying drawings.
Examples
Referring specifically to fig. 2, fig. 2 shows a voltage stabilizing filter circuit provided in an embodiment of the present application, where the circuit includes: the circuit comprises a first RC network U1, a second RC network U2, a third RC network U3, a fourth RC network U4, a first voltage dividing resistor Rf1, a second voltage dividing resistor Rf2, a third voltage dividing resistor Rg1, a fourth voltage dividing resistor Rg2, a first filter capacitor Cd1, a second filter capacitor Cd2, a first voltage stabilizing capacitor Cf and a second voltage stabilizing capacitor Cg.
One end of the first filter capacitor Cd1 is connected with one end of the second filter capacitor Cd2 through the first RC network U1 and the second RC network U2 in sequence; one end of the first voltage dividing resistor Rf1 is connected between the first RC network U1 and the second RC network U2 (i.e., a first reference voltage point), and the other end of the first voltage dividing resistor Rf1 is connected with a power supply Vdd; one end of the second voltage dividing resistor Rf2 is connected between the first RC network U1 and the second RC network U2 (i.e. a first reference voltage point), and the other end of the second voltage dividing resistor Rf2 is grounded. Preferably, the ratio of the resistance values of Rf1 to Rf2 is between 0.8 and 1.2.
The other end of the first filter capacitor Cd1 is connected with the other end of the second filter capacitor Cd2 through the third RC network U3 and the fourth RC network U4 in sequence; one end of the third voltage dividing resistor Rg1 is connected between the third RC network U3 and the fourth RC network U4 (i.e., a second reference voltage point), and the other end of the third voltage dividing resistor Rg1 is connected with the power supply Vdd; one end of the fourth voltage dividing resistor Rg2 is connected between the third RC network U3 and the fourth RC network U4 (i.e., the second reference voltage point), and the other end of the fourth voltage dividing resistor Rg2 is grounded. Preferably, the ratio of the resistance values of Rg1 to Rg2 is between 0.8 and 1.2.
The first filter capacitor Cd1 and the second filter capacitor Cd2 can restrict the drift of the bias voltage of the differential signal when the common mode transient event occurs, and can also filter out the low-frequency noise contained in the differential signal.
Referring to fig. 3, fig. 3 shows a specific implementation manner of the voltage stabilizing filter circuit according to the embodiment of the present application, in which one end of the first voltage stabilizing capacitor Cf is connected between the first voltage dividing resistor Rf1 and the second voltage dividing resistor Rf2 (i.e. the first reference voltage), and the other end of the first voltage stabilizing capacitor Cf is connected to ac ground (i.e. ground or power supply voltage). One end of the second voltage stabilizing capacitor Cg is connected between the third voltage dividing resistor Rg1 and the fourth voltage dividing resistor Rg2 (i.e. the second reference voltage), and the other end of the second voltage stabilizing capacitor Cg is connected to ac ground (i.e. ground or power supply voltage). Those skilled in the art will appreciate that Cf may also be connected between the first reference voltage point and the power supply Vdd; or a portion of Cf is connected between the first reference point and ground and the remaining portion is connected between the first reference point and the power supply Vdd. That is Cf refers to the sum of the first reference point and ground and the regulated supply of supply Vdd (which are all equivalent ac grounds). Similarly, cg refers to the sum of the second reference point and ground and the regulated supply of supply Vdd. The particular division ratio of Cf and Cg between ground and power supply Vdd should not constitute a limitation of the present application.
The first RC network U1 comprises a first RC capacitor Cb1 and a first RC resistor Rb1, the first RC capacitor Cb1 being connected in parallel with the first RC resistor Rb 1; one end of the first RC capacitor Cb1 connected in parallel with the first RC resistor Rb1 is connected to one end of the first filter capacitor Cd1, and the other end is connected to one end (i.e., a first reference voltage point) of the second RC network U2 away from the second filter capacitor Cd 2.
The second RC network U2 includes a second RC capacitor Cb2 and a second RC resistor Rb2, the second RC capacitor Cb2 being connected in parallel with the second RC resistor Rb 2; one end of the second RC capacitor Cb2 connected in parallel with the second RC resistor Rb2 is connected to one end of the second filter capacitor Cd2, and the other end is connected to one end (i.e., the first reference voltage point) of the first RC network U1, which is far away from the first filter capacitor Cd 1.
The first RC network U1 and the second RC network U2 may be symmetrical, the capacitance values of the first RC capacitor Cb1 and the second RC capacitor Cb2 are equal, and the resistance values of the first RC resistor Rb1 and the second RC resistor Rb2 are equal. The first RC network U1 and the second RC network U2 may include only a resistor and no capacitor connected in parallel therewith, and the parasitic capacitance of the resistor is regarded as a capacitance connected in parallel with the resistor; the leakage resistance of the capacitor may be regarded as the resistance of the capacitor connected in parallel. The specific composition of the first RC network U1 and the second RC network U2 does not constitute a limitation of the present invention.
The third RC network U3 includes a third RC capacitor Ce1 and a third RC resistor Re1, the third RC capacitor Ce1 being connected in parallel with the third RC resistor Re 1; one end of the third RC capacitor Ce1 connected in parallel with the third RC resistor Re1 is connected to one end of the first filter capacitor Cd1 away from the first RC network U1, and the other end is connected to one end of the fourth RC network U4 away from the second filter capacitor Cd2 (i.e., the second reference voltage point).
The fourth RC network U4 includes a fourth RC capacitor Ce2 and a fourth RC resistor Re2, the fourth RC capacitor Ce2 being connected in parallel with the fourth RC resistor Re 2; one end of the fourth RC capacitor Ce2 connected in parallel with the fourth RC resistor Re2 is connected to one end of the second filter capacitor Cd2 away from the second RC network U2, and the other end is connected to one end of the third RC network U3 away from the first filter capacitor Cd1 (i.e., the second reference voltage point).
The third RC network U3 and the fourth RC network U4 may be symmetrical in particular. The capacitance values of the third RC capacitor Ce1 and the fourth RC capacitor Ce2 are equal, the resistance values of the third RC resistor Re1 and the fourth RC resistor Re2 are equal, the third RC network U3 and the fourth RC network U4 can only comprise resistors and do not comprise the capacitance connected in parallel with the resistors, and the parasitic capacitance of the resistors is regarded as the capacitance connected in parallel with the resistors; the leakage resistance of the capacitor may be regarded as the resistance of the capacitor connected in parallel. The specific composition of the third RC network U3 and the fourth RC network U4 does not constitute a limitation of the present invention.
The first reference voltage Vref1 may be formed by a first voltage dividing resistor Rf1, a second voltage dividing resistor Rf2, and a total Cf of voltage stabilizing capacitances between the voltage dividing point and the ground and the power supply Vdd.
The second reference voltage Vref2 may be formed by the third voltage dividing resistor Rg1, the fourth voltage dividing resistor Rg2, and the sum Cg of the voltage stabilizing capacitances between the voltage dividing point and the ground and the power supply Vdd.
The capacitance value of the first filter capacitor Cd1 is equal to the capacitance value of the second filter capacitor Cd2, and is smaller than one tenth of the sum of the capacitance value of the first voltage stabilizing capacitor Cf and the capacitance value of the second voltage stabilizing capacitor Cg. The breakdown voltages of the first filter capacitor Cd1 and the second filter capacitor Cd2 are generally less than 2000V, and in particular, the breakdown voltage of the filter capacitors may be less than 1000V.
The working principle of the voltage stabilizing filter circuit provided by the embodiment of the application is as follows:
In the prior art, vref1 drifts during voltage transients, particularly when the voltage of the transmitter circuit TX rises rapidly at a constant rate relative to the voltage of the receiver circuit RX, during which the voltage drop across Rb1 and Rb2 caused by the common mode current can be considered approximately constant, so the rate of change of the voltages at nodes Va1, va2 can be written as:
since the voltages of Va1 and Va2 are changing, there is also a common-mode displacement current flowing through the first filter capacitor Cd1 and the second filter capacitor Cd2 (since the capacitance values of the two are equal, the capacitance value is taken as Cd here), and the common-mode currents Id1 and Id2 can be calculated as follows:
At the voltage division point of the second reference voltage Vref2, id1 and Id2 mostly flow into the second stabilizing capacitor Cg of the second reference voltage Vref2, so the drift amount Δvref2 of the second reference voltage Vref2 can be estimated as follows:
that is, the voltage of Vref2 is offset by only a proportion of the voltage drift of Vref1 (2 Cd/Cg), and if Cd (the capacitance of Cd1 or Cd 2) is much smaller than Cg, vref2 is much more stable than Vref 1.
On the other hand, in integrated circuits, the area of the chip is limited, so the total regulated capacitance that can be placed on the chip is limited. In the present invention, two independent reference voltages (i.e., the first reference voltage Vref1 and the second reference voltage Vref 2) are used, and two voltage stabilizing capacitors (i.e., the first voltage stabilizing capacitor Cf and the second voltage stabilizing capacitor Cg) are required.
As will be demonstrated below, using the scheme of the present invention, vref2 is stable over the prior art using a larger capacitance but only a single reference voltage, even though each regulated capacitance is smaller than the single capacitance used in the prior art (see fig. 1).
Assuming that the area on the integrated circuit chip where the capacitor can be placed is S, the capacitance density per unit area of the integrated capacitor is Cox. Using the prior art, the voltage drift of Vref1 is:
in the present invention, the voltage stabilizing capacitors on Vref1 and Vref2 share the area S where the capacitors are placed, so:
Cf+Cg＝S·Cox
According to the mean inequality, cf=cg, C f·Cg is the largest, i.e. the drift of Vref2 is the smallest:
Then in the present invention the voltage drift on Vref2 is:
So as long as Cd is two orders of magnitude smaller than the sum of the regulated capacitances, av ref2 can be significantly smaller than av ref1. For example, when s·c ox =200 pF, if the prior art is used, Δvref1 has been calculated before, which can reach several volts. In the present invention, capacitances of 200pF are equally allocated to Cf and Cg (100 pF each), and Cd is taken to be 2pF, so that Δvf2 can be calculated to be only a few hundred millivolts. Therefore, cd needs to be less than 10% of the sum of capacitance values of the stabilizing capacitors included in the first reference voltage and the second reference voltage, that is, (cf+cg)/10. Specifically, cd may be 0.2% -5% of the sum of the capacitance values of the stabilizing capacitors included in the first and second reference voltages. Preferably, the ratio of the capacitance values of Cf and Cg is between 0.2 and 5.0.
The first reference voltage and the second reference voltage shown in fig. 3 are implemented by voltage dividing resistors and voltage stabilizing capacitors between the voltage dividing point and ground or the voltage dividing point and the Vdd voltage of the power supply, it should be understood that the reference voltages may be implemented in other manners, and the equivalent input impedances thereof may be represented by Zf and Zg, and generally, the direct current impedances of Zf and Zg are both large, so as to limit the reference voltages to flow to the ground or the quiescent current of the Vdd voltage of the power supply, see fig. 4.
The network formed by the first filter capacitor Cd1, the second filter capacitor Cd2, the third RC network U3 and the fourth RC network U4 has the function of a high-pass filter, and low-frequency noise at Va1 and Va2 can be filtered.
Referring to fig. 5, fig. 5 shows a comparison effect diagram of the voltage stabilizing filter circuit provided by the present application and the prior art, and a broken line 401 is a drift (Δv ref1) of a reference voltage when a common mode transient event occurs in the prior art. The broken line 402 is the drift (Δv ref2) of the second reference voltage corresponding to the voltage stabilizing filter circuit provided by the present application when C d＝0.01×S·Cox, compared with the prior art, the present application reduces the reference voltage drift before the data processor by more than 10 times, but the required voltage stabilizing capacitance does not need to be increased.
Referring to fig. 6a and 6b, the voltage simulation result of the input terminal of the differential signal detection circuit is shown for convenience of explanation, only the input voltage waveform without data transmission, that is, the bias voltage of the differential signal (the transmitted data signal is a small pulse superimposed on the bias signal). Referring to fig. 6b,510 is a waveform of a common mode voltage, i.e., the potential of the transmitter circuit relative to the receiver circuit (VGND 1-VGND 2). 511 corresponds to a common mode transient event in which the transmitter potential increases relative to the receiver potential and 512 corresponds to a common mode transient event in which the transmitter potential decreases relative to the receiver potential.
Referring to fig. 6a and 501, a voltage waveform diagram of an input terminal (Va 1 or Va2 in fig. 1) of the differential signal detection circuit when the prior art is used; 502 is a waveform diagram of the input of the signal processing circuit (Vd 1 or Vd2 in FIG. 2) after the method of the present invention is used. Horizontal line 503 is the upper limit of the dynamic range of the signal processing circuit, i.e., the highest bias voltage at which the signal is normally processed. When the input signal is located in the area corresponding to 504 in the prior art, the upper voltage limit of the signal processing circuit is exceeded, and the signal transmitted at this time cannot be normally processed by the subsequent differential signal detection circuit. In the invention, the drift of the second reference voltage Vref2 is well controlled, so that the input voltage 505 of the signal processing circuit does not exceed the upper voltage limit of the differential signal detection circuit at any time in the voltage transient process, and the normal transmission of signals is ensured.
The above analysis is based on the fact that the transmitter circuit potential rises instantaneously with respect to the receiver circuit potential. The opposite case can also be analyzed similarly, and will not be described in detail here.
It should be noted that, referring to fig. 2, signals Vd1 and Vd2 output after passing through the segmented bias voltage stabilizing filter circuit of the present invention are directly connected to the differential signal detecting circuit Q. In practical applications, other filter circuits may be added after Vd1 and Vd2, and then connected to the signal processing circuit Q.
Referring to fig. 3, the embodiment of the present application further provides a signal detection circuit, which includes a transmitter circuit TX, a signal processing circuit Q, and a voltage stabilizing filter circuit as described above, wherein the transmitter circuit TX is connected to the voltage stabilizing filter circuit through a first high-voltage isolation capacitor Ca1 and a second high-voltage isolation capacitor Ca2, and the voltage stabilizing filter circuit is connected to the signal processing circuit.
One end of the first high-voltage isolation capacitor Ca1 is connected to the transmitter TX and the other end is connected to the receiver circuit RX, and one end of the second high-voltage isolation capacitor Ca2 is connected to the transmitter circuit TX and the other end is connected to the receiver circuit RX. The other end of the first high-voltage isolation capacitor Ca1 is connected with one end of the first filter capacitor Cd1, and the other end of the second high-voltage isolation capacitor Ca1 is connected with one end of the second filter capacitor Cd2. The breakdown voltage of the high voltage isolation capacitor is typically greater than 1000V, preferably greater than 2000V. In order to ensure that during common mode transient events, the high voltage between the transmitter circuit TX and the receiver circuit RX is mainly borne by the first high voltage isolation capacitor Ca1 and the second high voltage isolation capacitor Ca2, instead of the filter capacitor, increasing the risk of breakdown, it is necessary to ensure that the capacitance values of the first high voltage isolation capacitor Ca1 and the second high voltage isolation capacitor Ca2 are smaller than the first filter capacitor Cd1 and the second filter capacitor Cd2. Specifically, the capacitance value of the first high-voltage isolation capacitor Ca1 is smaller than 40% of the capacitance value of the first filter capacitor Cd 1; the capacitance value of the second high-voltage isolation capacitor Ca2 is smaller than 40% of the capacitance value of the second filter capacitor Cd2.
The first high voltage isolation capacitor Ca1 and the second high voltage isolation capacitor Ca2 are mainly used to withstand high voltages between the transmitter and the receiver that need to be isolated. The first filter capacitor Cd1 and the second filter capacitor Cd2 are mainly used for being matched with the first RC network, the second RC network, the third RC network and the fourth RC network to restrict the drift of the bias voltage of the differential signal in the occurrence process of the common-mode transient event, and meanwhile, low-frequency noise contained in the differential signal is filtered.
Referring to fig. 7, sometimes, in order to obtain a higher isolation voltage, the first high-voltage isolation capacitor may include a plurality of first isolation sub-capacitors, where the plurality of first isolation sub-capacitors are connected in series; the second high-voltage isolation capacitor comprises a plurality of second isolator capacitors, and the second isolator capacitors are connected in series. The particular number of series capacitances is not limiting to the invention.
The transmitter circuit TX amplifies the input signal and the input signal inverted by the inverter 601 by the drivers 602 and 603, and transmits the amplified signal to the receiver circuit RX in the form of differential signals through the high-voltage isolation capacitors Ca11-Ca1n and Ca21-Ca2 n. The breakdown voltage of the high-voltage isolation capacitor is greater than 2000V, and specifically, 1 or more capacitors with higher breakdown voltages can be formed in series. The high voltage isolation capacitor may be located on or off the transmitter or receiver chip, and then connected by a package (e.g., a bond wire) according to the requirements of a particular manufacturing process. The differential signal transmitted to the receiver through the high-voltage isolation capacitor is connected with the input end of the comparator circuit through the segmented bias voltage stabilizing circuit to obtain an output signal. The output signal may then be restored to a level signal by a latch.
Referring to fig. 8, in the embodiment shown in fig. 8, three chips are included. The first chip TX is the transmitter circuit, the second chip CA is a special isolation capacitor chip, the first high-voltage isolation capacitor and the second high-voltage isolation capacitor are integrated on the first chip CA, the third chip RX is the receiver circuit, the segmented bias voltage stabilizing filter circuit and the differential signal comparator circuit are included, and the first filter capacitor Cd1 and the second filter capacitor Cd2 are integrated on the third chip. The first chip and the second chip are connected by bonding wires 601 and the second chip and the third chip are connected by bonding wires 602. The technical advantage of this embodiment is that the high voltage isolation capacitor mainly bearing high voltage is separately placed on a different chip from the transmitter and receiver circuits, so that the transmitter chip, the receiver chip, and the high voltage isolation capacitor chip can be produced by different semiconductor process steps, the filter capacitor and the receiver chip which are better compatible with the standard CMOS process are integrated, and the high voltage isolation capacitor which is worse compatible with the standard CMOS process is used as a separate chip, thereby achieving the effects of optimizing the system performance and reducing the system cost.
The embodiment of the application provides a voltage stabilizing filter circuit and a signal detection circuit, wherein the circuit comprises: the filter capacitor comprises a first RC network U1, a second RC network U2, a third RC network U3, a fourth RC network U4, a first voltage dividing resistor Rf1, a second voltage dividing resistor Rf2, a third voltage dividing resistor Rg1, a fourth voltage dividing resistor Rg2, a first filter capacitor Cd1 and a second filter capacitor Cd2. One end of the first filter capacitor Cd1 is connected with one end of the second filter capacitor Cd2 through the first RC network U1 and the second RC network U2 in sequence; one end of the first voltage dividing resistor Rf1 is connected between the first RC network U1 and the second RC network U2, and the other end of the first voltage dividing resistor Rf1 is connected with a power supply Vdd; one end of the second voltage division resistor Rf2 is connected between the first RC network U1 and the second RC network U2, and the other end of the second voltage division resistor Rf2 is grounded; the other end of the first filter capacitor Cd1 is connected with the other end of the second filter capacitor Cd2 through the third RC network U3 and the fourth RC network U4 in sequence; one end of the third voltage dividing resistor Rg1 is connected between the third RC network U3 and the fourth RC network U4, and the other end of the third voltage dividing resistor Rg1 is connected with the power supply Vdd; one end of the fourth voltage dividing resistor Rg2 is connected between the third RC network U3 and the fourth RC network U4, and the other end of the fourth voltage dividing resistor Rg2 is grounded. The first filter capacitor Cd1 and the second filter capacitor Cd2 can restrict the drift of the bias voltage of the differential signal when the common mode transient event occurs, and can also filter out the low-frequency noise contained in the differential signal.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes. It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A voltage stabilizing filter circuit, said circuit comprising: the first RC network, the second RC network, the third RC network, the fourth RC network, the first voltage dividing resistor, the second voltage dividing resistor, the third voltage dividing resistor, the fourth voltage dividing resistor, the first filter capacitor and the second filter capacitor;
one end of the first filter capacitor is connected with one end of the second filter capacitor through the first RC network and the second RC network in sequence;
One end of the first voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the first voltage dividing resistor is connected with a power supply; one end of the second voltage dividing resistor is connected between the first RC network and the second RC network, and the other end of the second voltage dividing resistor is grounded;
the other end of the first filter capacitor is connected with the other end of the second filter capacitor through the third RC network and the fourth RC network in sequence;
One end of the third voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the third voltage dividing resistor is connected with the power supply; one end of the fourth voltage dividing resistor is connected between the third RC network and the fourth RC network, and the other end of the fourth voltage dividing resistor is grounded.
2. The voltage stabilizing filter circuit of claim 1, further comprising a first voltage stabilizing capacitor, wherein one end of the first voltage stabilizing capacitor is connected between the first voltage dividing resistor and the second voltage dividing resistor, and the other end of the first voltage stabilizing capacitor is connected to ac ground.
3. The voltage stabilizing filter circuit according to claim 2, further comprising a second voltage stabilizing capacitor, wherein one end of the second voltage stabilizing capacitor is connected between the third voltage dividing resistor and the fourth voltage dividing resistor, and the other end of the second voltage stabilizing capacitor is connected to ac ground.
4. The voltage stabilizing filter circuit of claim 3 wherein the capacitance of the first filter capacitor is equal to the capacitance of the second filter capacitor and less than one tenth of the sum of the capacitance of the first voltage stabilizing capacitor and the capacitance of the second voltage stabilizing capacitor.
5. The voltage stabilizing filter circuit of claim 1, wherein the first RC network comprises a first RC capacitor and a first RC resistor, the first RC capacitor being connected in parallel with the first RC resistor;
one end of the first RC capacitor connected in parallel with the first RC resistor is connected with the first filter capacitor, and the other end of the first RC capacitor is connected with one end, far away from the second filter capacitor, of the second RC network.
6. The voltage stabilizing filter circuit of claim 1, wherein the second RC network comprises a second RC capacitor and a second RC resistor, the second RC capacitor being in parallel with the second RC resistor;
One end of the second RC capacitor connected in parallel with the second RC resistor is connected with the second filter capacitor, and the other end of the second RC capacitor is connected with one end, far away from the second filter capacitor, of the first RC network.
7. The voltage stabilizing filter circuit according to claim 1, wherein the third RC network comprises a third RC capacitor and a third RC resistor, the third RC capacitor being connected in parallel with the third RC resistor;
One end of the third RC capacitor connected in parallel with the third RC resistor is connected with one end of the first filter capacitor far away from the first RC network, and the other end of the third RC capacitor is connected with one end of the fourth RC network far away from the second filter capacitor.
8. The voltage stabilizing filter circuit according to claim 1, wherein said fourth RC network comprises a fourth RC capacitor and a fourth RC resistor, said fourth RC capacitor being connected in parallel with said fourth RC resistor;
one end of the fourth RC capacitor connected in parallel with the fourth RC resistor is connected with one end of the second filter capacitor far away from the second RC network, and the other end of the fourth RC capacitor is connected with one end of the third RC network far away from the first filter capacitor.
9. A signal detection circuit, comprising a transmitter circuit, a signal processing circuit, and a voltage stabilizing filter circuit according to any one of claims 1-8, wherein the transmitter circuit is connected to the voltage stabilizing filter circuit via a first high voltage isolation capacitor and a second high voltage isolation capacitor, and the voltage stabilizing filter circuit is connected to the signal processing circuit.
10. The signal detection circuit of claim 9, wherein the first high voltage isolation capacitor comprises a plurality of first isolator capacitors, the plurality of first isolator capacitors being in series with one another; the second high-voltage isolation capacitor comprises a plurality of second isolator capacitors, and the second isolator capacitors are connected in series.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN208506626U (en) * | 2018-07-11 | 2019-02-15 | 重庆线易电子科技有限责任公司 | Filter circuit of pressure-stabilizing and signal deteching circuit |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2001284670A1 (en) * | 2000-07-27 | 2002-02-13 | Lynk Labs, Inc. | Current mode transmission |
| CN200994116Y (en) * | 2006-12-20 | 2007-12-19 | 青岛海信空调有限公司 | Current feedback differential amplifying-sampling circuit and air conditioner with same |
| US7848713B2 (en) * | 2007-09-10 | 2010-12-07 | Qualcomm Incorporated | Common mode signal attenuation for a differential duplexer |
| JP4482048B2 (en) * | 2008-05-30 | 2010-06-16 | 株式会社日本自動車部品総合研究所 | Receiver |
| CN102026063B (en) * | 2010-11-26 | 2014-12-10 | 中兴通讯股份有限公司 | Pseudo differential audio input circuit and installation method thereof |
| US9024654B2 (en) * | 2012-09-14 | 2015-05-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method to actively drive the common mode voltage of a receiver termination network |
| US8693528B1 (en) * | 2012-11-30 | 2014-04-08 | Nxp B.V. | Common mode suppression circuit |
| US9698728B2 (en) * | 2012-12-13 | 2017-07-04 | Texas Instruments Incorporated | Digital isolator |
| US9379746B2 (en) * | 2014-06-30 | 2016-06-28 | Texas Instruments Incorporated | Isolation circuits for digital communications and methods to provide isolation for digital communications |
| US9998301B2 (en) * | 2014-11-03 | 2018-06-12 | Analog Devices, Inc. | Signal isolator system with protection for common mode transients |
| US9634646B1 (en) * | 2015-10-27 | 2017-04-25 | Analog Devices, Inc. | Mismatch calibration of capacitive differential isolator |
| CN106531414A (en) * | 2016-12-20 | 2017-03-22 | 成都线易科技有限责任公司 | Transformer and control and driving system |
| CN108230652B (en) * | 2017-10-16 | 2024-05-03 | 瑞纳智能设备股份有限公司 | High-power MBUS master controller circuit |
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| CN208506626U (en) * | 2018-07-11 | 2019-02-15 | 重庆线易电子科技有限责任公司 | Filter circuit of pressure-stabilizing and signal deteching circuit |
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