CN108563144B - Missile-borne radar signal processing semi-physical simulation test system - Google Patents
Missile-borne radar signal processing semi-physical simulation test system Download PDFInfo
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Abstract
The invention belongs to the field of radar signal simulation processing, and discloses a missile-borne radar signal processing semi-physical simulation test system which comprises a radar seeker comprehensive test device, an analog-to-digital conversion module, an FPGA preprocessing module, a DSP imaging processing module and an upper computer display terminal; the signal source outputs two paths of reference clocks, one path of reference clocks is used as a reference clock for the radar seeker comprehensive testing device, the other path of reference clocks is used as a sampling clock for the signal processor, the radar seeker comprehensive testing device outputs analog radar echo signals and frame synchronization and pulse synchronization signals, the analog-to-digital conversion module finishes A/D sampling of the analog radar echo, the FPGA serves as a preprocessing module and finishes data preprocessing and ping-pong transmission, two DSP chips in the DSP imaging processing module finish imaging processing, the other DSP chip finishes transmission of imaging results to an upper computer, and imaging processing results are displayed on a display terminal of the upper computer in real time.
Description
Technical Field
The invention belongs to the technical field of radar signal simulation processing, and particularly relates to a missile-borne radar signal processing semi-physical simulation test system which is used for the fields of high-speed aircraft imaging tracking guidance and the like.
Background
In order to adapt to increasingly complex battlefield environments, radar science and technology develops rapidly, and higher requirements are put forward on modern real-time signal processing algorithms. The synthetic aperture radar signal processing technology also becomes a hotspot explored and developed in various countries, however, the performance of the signal processing algorithm is not limited to theoretical simulation, and further verification is needed in practical application.
In the test and verification process of the conventional synthetic aperture radar signal processor, the following defects exist: firstly, the actual performance of the signal processor is often verified by an external field experiment, the method is time-consuming and labor-consuming, the research and development period is increased undoubtedly, and the method is easily influenced by external conditions such as weather; secondly, the actual missile-borne signal processing board is a missile-borne board, and a uniform hardware platform is not provided, which brings great difficulty to the verification of a new algorithm; and thirdly, the whole-material seeker system has more external devices and higher manufacturing cost, and additional expenses are brought when the seeker system is used for testing and verifying a signal processing algorithm. Therefore, the construction of the radar signal processing semi-physical simulation test system is necessary for the simulation test of the signal processor in the laboratory stage.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a missile-borne radar signal processing semi-physical simulation test system, which makes laboratory stage test verification closer to the outfield experiment and is used to solve a series of problems that the outfield experiment is susceptible to the environment, the development cycle is long, the cost is high, and the like.
In the radar signal processing semi-physical simulation test system, a radar seeker comprehensive test device simulates the actual radar front end to output simulated radar echo, and a series of signal processing algorithms are completed in a signal processor, so that the performance of the signal processing algorithms and whether the signal processing system works normally are verified.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme.
A missile-borne radar signal processing semi-physical simulation test system, the system comprising: the radar seeker integrated test system comprises a clock signal source, a radar seeker integrated test device, a signal processor and an upper computer display terminal; the signal processor includes: the system comprises an analog-to-digital conversion module, an FPGA signal preprocessing module and a DSP imaging processing module;
a reference clock output end arranged on the clock signal source is connected with a reference clock input end arranged on the radar seeker comprehensive testing device;
the sampling clock output end arranged on the clock signal source is connected with the sampling clock input end arranged on the analog-to-digital conversion module;
an analog signal output end arranged on the radar seeker comprehensive testing device is connected with an analog signal input end arranged on the analog-to-digital conversion module;
a synchronous signal output end arranged on the radar seeker comprehensive testing device is connected with a synchronous signal input end of the FPGA signal preprocessing module;
the digital signal output end of the analog-to-digital conversion module is connected with the digital signal input end of the FPGA signal preprocessing module;
the digital signal output end of the FPGA signal preprocessing module is connected with the digital signal input end of the DSP imaging processing module;
and the digital signal output end of the DSP imaging processing module is connected with the digital signal input end of the upper computer display terminal through an Ethernet.
The technical scheme of the invention has the characteristics and further improvements that:
(1) the radar seeker comprehensive testing device is used for acquiring a simulation radar echo signal from simulation software, completing conversion from the simulation radar echo signal to a simulation radar echo signal, and sending the simulation radar echo signal to four analog signal input ends of an analog-to-digital conversion module through four SMA interfaces;
the radar seeker comprehensive testing device is also used for setting a radar echo frame synchronization signal and a pulse synchronization signal and sending the radar echo frame synchronization signal and the pulse synchronization signal to an FPGA signal preprocessing module through a BNC interface;
the analog-to-digital conversion module is used for sequentially amplifying the analog radar echo signal, performing single-ended to differential operation and A/D sampling, and sending the digital radar signal obtained after sampling to the FPGA signal preprocessing module through a 12-bit LVDS interface;
the FPGA signal preprocessing module is used for sequentially carrying out preprocessing operations of digital down-conversion and pulse compression on the digital radar signals according to the radar echo frame synchronizing signals and the pulse synchronizing signals to obtain preprocessed digital radar signals, and ping-pong sending the preprocessed digital radar signals to the DSP imaging processing module through the SRIO interface;
the DSP imaging processing module is used for imaging the preprocessed digital radar signals and sending radar signal imaging results to an upper computer display terminal through a gigabit Ethernet;
and the upper computer display terminal is used for displaying the radar signal imaging result in real time.
(2) The analog-to-digital conversion module comprises: the four amplifiers are correspondingly connected with the four A/D converters;
the amplifier is used for amplifying the input analog radar echo signal and converting a single-end signal into a differential signal; the gain of the amplifier for amplifying the analog radar echo signal is controlled by the FPGA signal preprocessing module through the SPI interface;
and the A/D converter is used for carrying out A/D sampling on the amplified differential signal to obtain a digital radar signal and sending the digital radar signal to the FPGA signal preprocessing module.
(3) The FPGA signal preprocessing module comprises: the system comprises a data sorting submodule, a digital down-conversion submodule, a pulse compression submodule, a data buffering submodule and an SRIO transmission submodule;
the data sorting submodule is used for sorting the digital radar signals, converting unsigned numbers into signed numbers, expanding data bit width from 12 bits to 16 bits, intercepting data point numbers in each pulse repetition period to 4096 points, performing clock domain conversion on the data, and transmitting the data to the digital down-conversion module;
the digital down-conversion submodule is used for receiving the data processed by the data sorting submodule, mixing and filtering the data according to the radar echo frame synchronous signal and the pulse synchronous signal, generating a radar echo frame synchronous signal and a pulse synchronous signal and transmitting the radar echo frame synchronous signal and the pulse synchronous signal to the pulse compression submodule;
the pulse compression submodule is used for receiving the data processed by the digital down-conversion submodule, performing 4096-point FFT operation, matched filtering and 4096-point IFFT operation on the data according to the radar echo frame synchronizing signal and the pulse synchronizing signal, generating a radar echo frame synchronizing signal and a pulse synchronizing signal and transmitting the radar echo frame synchronizing signal and the pulse synchronizing signal to the data buffering submodule;
the data buffer submodule is used for performing clock domain conversion on data and providing a pulse starting transmission mark for the SRIO transmission submodule;
and the SRIO transmission submodule is used for receiving the data of the data buffering submodule, detecting a frame starting mark, finishing an SRIO stream writing protocol and ping-pong transmitting the data to the DSP imaging processing module.
(4) The DSP imaging processing module comprises three DSP chips which are respectively marked as DSP1, DSP2 and DSP 3; the DSP1 is connected with the DSP2 through a Hyperlink interface, and the DSP3 is connected with the DSP2 through a PCI-Express interface;
the FPGA signal preprocessing module is used for sending 4096 pulse data to the DSP1, then sending data with the same data volume to the DSP3, sequentially alternating between the DSP1 and the DSP3, and ping-pong sending the preprocessed digital radar signals to the DSP imaging processing module through the SRIO interface;
the DSP1 and the DSP3 are used for receiving the preprocessed digital radar signals sent by the FPGA signal preprocessing module in a ping-pong manner; respectively carrying out imaging processes of Doppler center estimation, range walk correction, range bend correction, secondary range pulse pressure, motion error estimation and compensation, azimuth compression and geometric correction on the received preprocessed digital radar signals to obtain radar signal imaging results, and sending the radar signal imaging results to a DSP 2;
and the DSP2 sends the radar signal imaging result to an upper computer display terminal through a gigabit Ethernet.
(5) The DSP2 is connected to the gigabit Ethernet conversion chip through an SGMII interface, and the gigabit Ethernet conversion chip is connected to an upper computer display terminal through an RJ45 network interface.
The invention has the following advantages: firstly, the radar seeker comprehensive testing device is provided with an 8192GB solid state disk, the storage capacity is large, and radar echo signals with any data volume generated by MATALB can be played back; secondly, the radar seeker comprehensive testing device is provided with four DA chips with the highest 500MHz, the maximum four radar intermediate-frequency echo signals meeting hardware parameters and generated by MATLAB can be played back, the four signals can be the same or different, and multi-channel verification of a signal processing board can be completed at the same time; thirdly, the invention adopts a radar seeker comprehensive testing device which is provided with a reference clock input interface, a frame synchronization output interface and a pulse synchronization output interface, echo data is played back according to the three signals, and the actual working condition of the front end of the radar is simulated; fourthly, the FPGA chip selects Virtex-6 series chips with abundant logic resources, memory resources and DSP resources, the DSP chip also selects TMS320C6678 chips with the highest performance in the industry, and each DSP is externally connected with a DDR SDRAM chip with the capacity of 2GByte so as to meet the requirements of the system on processing large data volume and running complex algorithms; fifthly, the FPGA preprocessing module in the invention completes data transmission with the DSP1 and the DSP3 chips in a ping-pong mode by adopting a high-speed serial communication interface SRIO, and the other DSP2 chip communicates with an upper computer through a gigabit Ethernet chip, so that the defect of slow transmission rate in the prior art is overcome, the real-time performance of the invention is improved, and the requirements of a missile-borne radar signal processor system on high real-time performance and high speed are met; sixth, the implementation process of the invention is simple, the function of the signal processing board can be tested and verified in a laboratory, the invention is not influenced by external conditions, the manpower and material resources are saved, and the time period and the development cost of the external field experiment are saved; seventh, the system of the invention has less equipment, convenient connection and lower cost; eighth, the invention can replace the signal processing board or the signal processing algorithm, and completes verification for different signal processing boards or algorithms, thereby having strong universality.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of an implementation structure of a missile-borne radar signal processing semi-physical simulation test system according to the present invention;
FIG. 2 is a schematic diagram of the connection between the integrated test device of the radar seeker and the signal processor;
FIG. 3 is a schematic diagram of the connection between the analog-to-digital conversion module and the FPGA preprocessing module according to the present invention;
FIG. 4 is a schematic diagram of the connection between the DSP imaging processing module and the FPGA preprocessing module of the present invention;
fig. 5 is a schematic diagram of the connection between the upper computer display terminal and the signal processor according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention is further described with reference to the following figures.
According to the attached figure 1, the invention comprises the following modules: the radar seeker comprehensive testing device comprises a radar seeker comprehensive testing device, a signal processor and an upper computer display terminal. Wherein:
the radar seeker comprehensive test device is mainly used for generating multipath synchronous analog radar echo signals. The back panel of the radar seeker comprehensive testing device is provided with 4 paths of SMA D/A output interfaces, the maximum conversion rate of a DA chip is 500MHz, the resolution is 16 bits, one path of external reference clock input interface, one path of frame synchronization output interface and one path of pulse synchronization output interface.
The radar seeker comprehensive testing device mainly has the following functions: format conversion from MATLAB simulation echo data to radar seeker comprehensive test device echo data; the device is used for importing and browsing echo data into a solid state disk of the radar seeker comprehensive testing device; setting playback parameters of the radar seeker comprehensive testing device; the analog radar echo signal processing device is used for outputting a plurality of paths of analog radar echo signals to the signal processor; and the pulse synchronization signal is used for outputting a radar echo frame synchronization signal and a pulse synchronization signal to the signal processor.
The signal processor comprises an analog-to-digital conversion module, an FPGA preprocessing module and a DSP imaging processing module.
The analog-digital conversion module adopts four analog-digital conversion chips ADS5463, but is not limited to the chips, the highest sampling rate of the chips is 500MSPS (how many megabits of sampling per second), 12-bit LVDS output, is unidirectionally connected with the radar seeker comprehensive testing device and bidirectionally connected with the FPGA preprocessing module, is used for receiving the simulated radar echo output by the radar seeker comprehensive testing device and sampling, since the radar seeker integrated test device gives a single-ended signal, and the peak-to-peak value of the signal is 1.2Vpp, so that the collected analog quantity is firstly converted into differential signal by amplifier AD8370 of ADI company, and amplified, and the gain of the output signal of the AD8370 chip can be controlled by the FPGA chip through modifying the value of an on-chip register through the SPI interface, and then the differential signal output by the AD8370 is output to the ADS5463 to complete analog-to-digital conversion, and finally the sampled data is sent to an FPGA preprocessing module.
The FPGA preprocessing module selects a Virtex-6 series high-performance XC6VLX240T-FF1156 chip from XILINX company, but is not limited to the chip, the number of logic units of the chip reaches 241152, the number of DSP48E1 Slice reaches 768, the speed reaches 600MHz, the number of single-ended pins reaches 600, and the number of high-speed serial transceivers reaches 20, so that various high-speed serial bus protocols can be realized.
The FPGA preprocessing module comprises a data sorting submodule, a digital down-conversion submodule, a pulse compression submodule, a data buffering submodule and an SRIO transmission submodule, wherein the data sorting submodule is used for sorting echo data transmitted by the analog-to-digital conversion module, converting unsigned numbers into signed numbers, expanding data bit width from 12 bits to 16 bits, intercepting data points in each pulse repetition period to 4096 points, performing clock domain conversion on the data, and transmitting the data to the digital down-conversion module; the digital down-conversion submodule is used for receiving the data processed by the data sorting submodule, mixing and filtering the data according to the synchronous signals, generating frame synchronous and pulse synchronous signals and transmitting the frame synchronous and pulse synchronous signals to the pulse compression submodule; the pulse compression submodule is used for receiving the data processed by the digital down-conversion submodule, performing 4096-point FFT operation, matched filtering and 4096-point IFFT operation on the data according to the pulse synchronization signal, generating a frame synchronization signal and a pulse synchronization signal and transmitting the frame synchronization signal and the pulse synchronization signal to the data buffering submodule; the data buffer submodule performs clock domain conversion on data and provides a pulse starting transmission mark for the SRIO transmission submodule; the SRIO transmission submodule is used for receiving data of the data buffering submodule, detecting a frame start mark and finishing an SRIO stream writing protocol, ping-pong transmitting the data to the DSP1 and the DSP3 chips, sending 4096 pulse data to one DSP chip, then sending data with the same data volume to the other DSP chip, and sequentially alternating between the two DSP chips to finish doorbell interrupt transmission.
The DSP imaging processing module selects three DSP chips of a TMS320C6678 model of TI company, but is not limited to the chips, the chips have 8 high-performance fixed-point/floating-point CPU cores with the speed up to 1.25GHz, 4096KB multi-core shared memory is arranged in the chips, the maximum 8GB DDR3 memory can be expanded out of the chips, the maximum running speed of the off-chip DDR3 is 1600MHz, 4 SRIO channels are provided, the working speeds of 1.25, 2.5, 3.125 and 5Gbps are compatible, each DSP chip is an SDRAM chip with the plug-in capacity of 2GByte and is used for storing data and imaging results sent by the FPGA preprocessing module, and the DSP1 and the DSP3 are used for receiving preprocessed data sent by the FPGA preprocessing module in a ping-pong manner; the DSP1 and the DSP3 are used for performing Doppler center estimation, distance walking correction, distance bending correction, secondary distance pulse pressure, motion error estimation and compensation, orientation compression and geometric correction algorithms, completing imaging processing, and sending imaging results to a DSP2 chip through a Hyperlink interface and a PCI-Express interface; the DSP2 chip is used for sending the imaging result sent by the DSP1 and the DSP3 to the upper computer display terminal through a gigabit Ethernet.
And the upper computer display terminal is bidirectionally connected with the signal processor through a network cable, and in the system implementation process, the DSP2 chip sends SAR images obtained by the DSP1 and the DSP3 in the DSP imaging processing module to the upper computer through a gigabit Ethernet, and the imaging result is displayed in the upper computer display terminal in real time.
The connection between the integrated test device for a radar seeker and the signal processor is further illustrated with reference to fig. 2.
The radar seeker comprehensive testing device is provided with four paths of SMA D/A output interfaces: the system comprises SMA1, SMA2, SMA3 and SMA4, which can output at most four-channel coherent signals at the same time, a DA output interface is connected with four A/D input interfaces AD1, AD2, AD3 and AD4 of an analog-digital conversion module through coaxial cables, a reference clock input interface CLK _ IN of the radar seeker comprehensive test device is connected with one output of a signal source, an AD sampling clock input interface ADC _ CLK of a signal processor is connected with the other output of the signal source, a frame synchronization signal IPPS _ OUT and a pulse synchronization signal TRIG _ OUT of the radar seeker comprehensive test device are output through a BNC interface, and are connected with a frame synchronization input sync _ frame and a pulse synchronization input sync _ pulse of the signal processor through the coaxial cables to provide reference for FPGA data preprocessing.
The connection between the analog-to-digital conversion module and the FPGA preprocessing module is further illustrated and described with reference to fig. 3.
The analog-to-digital conversion module adopts four A/D conversion chips, the chips select ADS5463 of TI company for collecting intermediate frequency echo signals of analog radar, firstly, an amplifier AD8370 of ADI company is selected to convert single-end signals of collected analog quantity into differential signals, the differential signals are amplified, the FPGA chip modifies the value of a register in the AD8370 through an SPI interface to control the gain of output signals, specific control signals are DATA, CLK and LATCH, then the AD8370 chip transmits the differential signals to the ADS5463, the AD chip carries out A/D sampling, and the DATA are sent to the FPGA preprocessing module. The main signal lines of the analog-to-digital conversion chip ADS5463 connected with the FPGA chip are as follows: ADC _ P [ 11: 0), ADC _ N [ 11: 0] is a low voltage differential signal used for transmitting A/D sampling data, and the data output mode is a DDR mode; OVR _ P, OVR _ N is a data overflow signal line for indicating whether the input signal value overflows; DRY _ P, DRY _ N is a DATA ready signal line to indicate that sampling has been completed.
The connection between the DSP imaging processing module and the FPGA preprocessing module is further described with reference to fig. 4.
The DSP imaging processing module selects three DSP chips with the model number of TMS320C6678, the three DSP chips are connected with an FPGA preprocessing module through a Serial Rapid IO (SRIO) interface, five MGT high-speed transceiving modules including BANK112-BANK116 are arranged in the FPGA, and the BANK112 is connected with the DSP 3; the BANK113 is connected with the DSP1, the BANK116 is connected with the DSP2, the three SRIO interfaces are set to be 4 channels, the rate of each channel is 3.125GHz, the terminal device is a source or a destination of a data packet, different terminal devices are distinguished by device IDs, the ID numbers of the FPGA are respectively 0xFF, 0x AA and 0x 55, the ID number of the DSP1 is D1, the ID number of the DSP2 is D2, and the ID number of the DSP3 is D3. The SRIO clock frequency of the high-speed serial communication interface is 125MHz, and the serial communication interface adopts the following signal wires: srio _ txp0, srio _ txn0, srio _ txpl, srio _ txn1, srio _ txp2, srio _ txn2, srio _ txp3, srio _ txn 3; srio _ rxp0, srio _ rxn0, srio _ rxp1, srio _ rxn1, srio _ rxp2, srio _ rxn2, srio _ rxp3, srio _ rxn3, in serial differential form. After the DSP1 and the DSP3 complete the imaging algorithm, the imaging result is sent to the DSP2 through a Hyperlink interface and a PCI-Express interface, and the DSP2 transmits data from the signal processing board to an upper computer display terminal to display the result in real time.
The connection between the upper computer display terminal and the signal processor will be further described with reference to fig. 5.
An SGMII interface of the DSP2 chip is connected to a gigabit Ethernet conversion chip, the gigabit Ethernet conversion chip adopts an 88EE1111 chip, and the following signal lines are adopted for specific connection: the signal line comprises a DSP2_ SGMII1_ RXP, a DSP2_ SGMII1_ RXN, a DSP2_ SGMII1_ TXP and a DSP2_ SGMII1_ TXN, and is a differential data transmission line; the DSP2_ MDIO is a bidirectional IO control line of an Ethernet conversion chip, the DSP2_ MDC is a clock line of the Ethernet conversion chip, the conversion chip is connected with an RJ45 network port, and the conversion chip is communicated with an upper computer through an RJ45 connection network line to transmit an imaging processing result in real time.
The working principle of the invention in the implementation process is explained as follows:
and (5) echo simulation. Customizing echo parameters according to test requirements, simulating echo data in MATLAB, writing the data into a file with a suffix name of dat, completing data conversion in data conversion software, adding 32 bytes of header information before each pulse data, wherein the header is mainly used for analyzing the echo simulation data by internal hardware in a system, storing the data to be played back into an SSD (solid state disk) through an embedded computer after the data conversion is completed, browsing the data on a software interface after the data is imported, configuring system parameters including a clock source, a reference clock, a pulse repetition frequency, a frame and a pulse width after the imported data is confirmed to be correct, entering a playback interface after the setting is completed, selecting a playback mode, and waiting for electrifying a signal processing board.
And (5) connecting the systems. A reference clock input interface of the radar seeker comprehensive testing device is connected with a signal source output interface through a coaxial cable, an AD sampling clock input interface of a signal processor is connected with the other output interface of the signal source through a coaxial cable, a DA output interface of the radar seeker comprehensive testing device is connected with an AD input interface of the signal processor through a coaxial cable, a frame synchronization output interface of the radar seeker comprehensive testing device is connected with a frame synchronization output interface of the signal processor, a pulse synchronization input interface of the radar seeker comprehensive testing device is connected with a pulse synchronization input interface of the signal processor through a coaxial cable, and an Ethernet interface of the signal processor is connected with a computer host through a network cable.
The signal processing board is powered on. Clicking a start playback button of a software interface of the radar seeker comprehensive testing device, outputting an analog radar echo signal and a frame synchronization and pulse synchronization signal under the action of an external reference clock, modifying a register value in an AD8370 chip by an SPI (Serial peripheral interface) to control the gain of the output signal, carrying out A/D (analog to digital) conversion on the input analog radar echo signal when a sampling clock arrives, carrying out data preprocessing on data transmitted by the analog to digital conversion module under the guidance of the frame synchronization and pulse synchronization signal by an FPGA preprocessing module to realize digital down-conversion, fast Fourier transform and distance-oriented pulse compression operations, then sending the preprocessed data to a DSP1 and a DSP3 in the DSP imaging processing module in a ping-pong mode by the FPGA preprocessing module through a Serial Rapid IO (SRIO) interface, sending a doorbell interrupt when sending data of 4096 pulse repetition periods, after the DSP1 and the DSP3 receive the interrupt, Doppler center estimation, distance walking correction, distance bending correction, secondary distance pulse pressure, motion error estimation and compensation, azimuth compression and geometric correction algorithms are carried out on the preprocessed data to complete imaging processing, then the DSP1 and the DSP3 send the processed result to the DSP2 through a Hyperlink interface and a PCI-Express interface, the DSP2 transmits the imaging processing result to an upper computer display terminal through a gigabit Ethernet and carries out real-time imaging on an upper computer display terminal interface.
The application of the invention is not limited by external conditions, the invention can simulate the actual radar front end to work, and the system also has the advantages of stability, reliability, large storage capacity and high transmission rate, and is mainly suitable for the laboratory stage test verification in the fields of high-speed aircraft imaging tracking guidance and the like.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (5)
1. A missile-borne radar signal processing semi-physical simulation test system is characterized by comprising: the radar seeker integrated test system comprises a clock signal source, a radar seeker integrated test device, a signal processor and an upper computer display terminal; the signal processor includes: the system comprises an analog-to-digital conversion module, an FPGA signal preprocessing module and a DSP imaging processing module;
a reference clock output end arranged on the clock signal source is connected with a reference clock input end arranged on the radar seeker comprehensive testing device;
the sampling clock output end arranged on the clock signal source is connected with the sampling clock input end arranged on the analog-to-digital conversion module;
an analog signal output end arranged on the radar seeker comprehensive testing device is connected with an analog signal input end arranged on the analog-to-digital conversion module;
a synchronous signal output end arranged on the radar seeker comprehensive testing device is connected with a synchronous signal input end of the FPGA signal preprocessing module;
the digital signal output end of the analog-to-digital conversion module is connected with the digital signal input end of the FPGA signal preprocessing module;
the digital signal output end of the FPGA signal preprocessing module is connected with the digital signal input end of the DSP imaging processing module;
the digital signal output end of the DSP imaging processing module is connected with the digital signal input end of the upper computer display terminal through an Ethernet;
the radar seeker comprehensive testing device is used for acquiring a simulation radar echo signal from simulation software, completing conversion from the simulation radar echo signal to a simulation radar echo signal, and sending the simulation radar echo signal to four analog signal input ends of an analog-to-digital conversion module through four SMA interfaces;
the radar seeker comprehensive testing device is also used for setting a radar echo frame synchronization signal and a pulse synchronization signal and sending the radar echo frame synchronization signal and the pulse synchronization signal to an FPGA signal preprocessing module through a BNC interface;
the analog-to-digital conversion module is used for sequentially amplifying the analog radar echo signal, performing single-ended to differential operation and A/D sampling, and sending the digital radar signal obtained after A/D sampling to the FPGA signal preprocessing module through a 12-bit LVDS interface;
the FPGA signal preprocessing module is used for sequentially carrying out preprocessing operations of digital down-conversion and pulse compression on the digital radar signals according to the radar echo frame synchronizing signals and the pulse synchronizing signals to obtain preprocessed digital radar signals, and ping-pong sending the preprocessed digital radar signals to the DSP imaging processing module through the SRIO interface;
the DSP imaging processing module is used for imaging the preprocessed digital radar signals and sending radar signal imaging results to an upper computer display terminal through a gigabit Ethernet;
and the upper computer display terminal is used for displaying the radar signal imaging result in real time.
2. The system of claim 1, wherein the analog-to-digital conversion module comprises: the four amplifiers are correspondingly connected with the four A/D converters;
the amplifier is used for amplifying an input analog radar echo signal and converting the amplified single-ended signal into a differential signal; the gain of the amplifier for amplifying the analog radar echo signal is controlled by the FPGA signal preprocessing module through the SPI interface;
and the A/D converter is used for carrying out A/D sampling on the amplified differential signal to obtain a digital radar signal and sending the digital radar signal to the FPGA signal preprocessing module.
3. The system according to claim 1, wherein the FPGA signal preprocessing module comprises: the system comprises a data sorting submodule, a digital down-conversion submodule, a pulse compression submodule, a data buffering submodule and an SRIO transmission submodule;
the data sorting submodule is used for sorting the digital radar signals, converting unsigned numbers into signed numbers, expanding data bit width from 12 bits to 16 bits, intercepting data point numbers in each pulse repetition period to 4096 points, performing clock domain conversion on the data, and transmitting the data to the digital down-conversion module;
the digital down-conversion submodule is used for receiving the data processed by the data sorting submodule, mixing and filtering the data according to the radar echo frame synchronous signal and the pulse synchronous signal, generating a radar echo frame synchronous signal and a pulse synchronous signal and transmitting the radar echo frame synchronous signal and the pulse synchronous signal to the pulse compression submodule;
the pulse compression submodule is used for receiving the data processed by the digital down-conversion submodule, performing 4096-point FFT operation, matched filtering and 4096-point IFFT operation on the data according to the radar echo frame synchronizing signal and the pulse synchronizing signal, generating a radar echo frame synchronizing signal and a pulse synchronizing signal and transmitting the radar echo frame synchronizing signal and the pulse synchronizing signal to the data buffering submodule;
the data buffer submodule is used for performing clock domain conversion on data and providing a pulse starting transmission mark for the SRIO transmission submodule;
and the SRIO transmission submodule is used for receiving the data of the data buffering submodule, detecting a frame starting mark, finishing an SRIO stream writing protocol and ping-pong transmitting the data to the DSP imaging processing module.
4. The semi-physical simulation test system for missile-borne radar signal processing according to claim 1, wherein the DSP imaging processing module comprises three DSP chips, which are respectively marked as DSP1, DSP2 and DSP 3; the DSP1 is connected with the DSP2 through a Hyperlink interface, and the DSP3 is connected with the DSP2 through a PCI-Express interface;
the FPGA signal preprocessing module is used for sending 4096 pulse data to the DSP1, then sending data with the same data volume to the DSP3, sequentially alternating between the DSP1 and the DSP3, and ping-pong sending the preprocessed digital radar signals to the DSP imaging processing module through the SRIO interface;
the DSP1 and the DSP3 are used for receiving the preprocessed digital radar signals sent by the FPGA signal preprocessing module in a ping-pong manner; respectively carrying out imaging processes of Doppler center estimation, range walk correction, range bend correction, secondary range pulse pressure, motion error estimation and compensation, azimuth compression and geometric correction on the received preprocessed digital radar signals to obtain radar signal imaging results, and sending the radar signal imaging results to a DSP 2;
and the DSP2 sends the radar signal imaging result to an upper computer display terminal through a gigabit Ethernet.
5. The semi-physical simulation test system for missile-borne radar signal processing according to claim 4, wherein the DSP2 is connected to a gigabit Ethernet conversion chip through an SGMII interface, and the gigabit Ethernet conversion chip is connected to an upper computer display terminal through an RJ45 network interface.
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