CN108538843A - The preparation method of flash cell and semiconductor structure - Google Patents
The preparation method of flash cell and semiconductor structure Download PDFInfo
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- CN108538843A CN108538843A CN201810312988.3A CN201810312988A CN108538843A CN 108538843 A CN108538843 A CN 108538843A CN 201810312988 A CN201810312988 A CN 201810312988A CN 108538843 A CN108538843 A CN 108538843A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000007667 floating Methods 0.000 claims abstract description 111
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000002210 silicon-based material Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 210000003205 muscle Anatomy 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides the preparation methods of a kind of flash cell and semiconductor structure, the length range of floating boom in flash cell to be formed is determined first, then the dielectric layer and the floating gate layer are etched again, form the first opening, the cross-sectional width of first open bottom is measured, and polycrystalline silicon material is filled in first opening；The dielectric layer is removed, the second opening is formed；The cross-sectional width of the first side wall is selected according to the length range of the floating boom and the cross-sectional width of first open bottom, and forms first side wall in the side wall of second opening.When forming floating boom due to separating different flash cells, it is the floating gate layer that first side wall bottom is etched using the first side wall as mask, the length of the floating boom of formation is adjusted by adjusting the cross-sectional width of first side wall, to ensure that the floating boom formed in its length range, avoids the performance of device from changing.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to the preparation methods of a kind of flash cell and semiconductor structure.
Background technology
Flash memory (Flash Memory) is that a kind of the non-volatile of long-life (remains to keep being stored under power blackout situation
Data information) memory, due to remained to when it is powered off preserve data, flash memory is usually used to preservation setting information, such as in electricity
Preservation data etc. in the BIOS (basic program) of brain, PDA (personal digital assistant), digital camera.
The length of floating boom in flash memory is most important, which determine the number that flash memory is capable of amount of charge stored, however it is existing
Formation flash memory technique in, the length of floating boom is difficult to control, and the performance of device is caused to change.
Invention content
The purpose of the present invention is to provide the preparation methods of a kind of flash cell and semiconductor structure, to solve the prior art
The problems such as length of middle floating boom is difficult to control.
In order to achieve the above object, the present invention provides a kind of preparation method of flash cell, the systems of the flash cell
Preparation Method includes：
Determine the length range of floating boom in flash cell to be formed；
Substrate is provided, floating gate layer and dielectric layer are sequentially formed on the substrate；
The dielectric layer and the floating gate layer are etched, the first opening is formed, first opening exposes the substrate；
The cross-sectional width of first open bottom is measured, and polycrystalline silicon material is filled in first opening；
The dielectric layer is removed, the second opening is formed；
The section of the first side wall is selected according to the length range of the floating boom and the cross-sectional width of first open bottom
Width, and form first side wall in the side wall of second opening；
Using first side wall as mask, the floating gate layer of second open bottom is removed, forms floating boom.
Optionally, the length range of the floating boom includes 90nm~95nm.
Optionally, the cross-sectional width of first open bottom includes 60nm~65nm.
Optionally, the cross-sectional width of first side wall includes 200 angstroms~1000 angstroms.
Optionally, it is also formed with control grid layer between the floating gate layer and the dielectric layer.
Optionally, the dielectric layer and the floating gate layer are etched, the first opening is formed, first opening exposes described
Substrate includes：
The dielectric layer is etched, first groove is formed, the first groove exposes the control grid layer；
The second side wall is formed in the side wall of the first groove；
Using second side wall as mask, the control grid layer is etched, forms second groove, the second groove exposes
The floating gate layer；
Third side wall is formed in the side wall of the second groove and first side wall；
Using the third side wall as mask, the floating gate layer is etched, forms third groove, the third groove exposes institute
State substrate；
The 4th side wall is formed in the side wall of the third groove and the third side wall.
Optionally, the cross-sectional width of the third channel bottom is equal to the cross-sectional width of first open bottom.
Optionally, using the third side wall as mask, the floating gate layer is etched, forms third groove, the third groove
Exposing the substrate includes：
Using the floating gate layer of the lithographic method etched portions thickness of anisotropic,
The floating gate layer of residual thickness is etched using the lithographic method of isotropic, forms floating boom tip.
Optionally, include the step of filling polycrystalline silicon material in first opening：
Polysilicon material layer is formed, the polysilicon material layer covers the dielectric layer and fills the third groove；
The polysilicon material layer is planarized, until exposing the dielectric layer.
Optionally, the step of forming the floating boom include：
Using first side wall as mask, the floating gate layer of second open bottom is removed, the floating boom and the 4th are formed
Groove；
The 5th side wall is formed in the side wall of the 4th groove and first side wall.
Optionally, the material of the dielectric layer includes at least one of silica, silicon nitride or silicon oxynitride.
The present invention also provides a kind of preparation methods of semiconductor structure, using the preparation method of the flash cell.
In the preparation method of flash cell provided by the invention and semiconductor structure, it is first determined flash memory list to be formed
Then the length range of floating boom in member etches the dielectric layer and the floating gate layer again, form the first opening, measure described first
The cross-sectional width of open bottom, and fill polycrystalline silicon material in first opening；The dielectric layer is removed, second is formed and opens
Mouthful；The cross-sectional width of the first side wall is selected according to the length range of the floating boom and the cross-sectional width of first open bottom,
And first side wall is formed in the side wall of second opening, then the floating gate layer is etched to form floating boom.Due to will be different
Flash cell when separating and forming floating boom, be the floating gate layer that first side wall bottom is etched using the first side wall as mask,
The length of the floating boom of formation is adjusted by adjusting the cross-sectional width of first side wall, to ensure the floating boom formed in its length
In range, the performance of device is avoided to change.
Description of the drawings
Fig. 1 is the flow chart of the preparation method of flash cell provided in an embodiment of the present invention；
Fig. 2-Figure 12 is the semiconductor junction that the preparation method provided in an embodiment of the present invention using the flash cell is formed
The diagrammatic cross-section of structure；
Wherein, 1- substrates, 2- floating gate layers, 3- control grid layers, 4- dielectric layers, 51- first grooves, 52- second grooves, 53-
Third groove, 54- second are open, the first side walls of 61-, the second side walls of 62-, 63- third side walls, the 4th side walls of 64-, 65- the 5th
Side wall.
Specific implementation mode
The specific implementation mode of the present invention is described in more detail below in conjunction with schematic diagram.According to following description and
Claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and
Using non-accurate ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Refering to fig. 1, it is the flow chart of the preparation method of flash cell provided in this embodiment, the system of the flash cell
Preparation Method includes：
S1：Determine the length range of floating boom in flash cell to be formed；
S2：Substrate is provided, floating gate layer and dielectric layer are sequentially formed on the substrate；
S3：The dielectric layer and the floating gate layer are etched, the first opening is formed, first opening exposes the lining
Bottom；
S4：The cross-sectional width of first open bottom is measured, and polycrystalline silicon material is filled in first opening；
S5：The dielectric layer is removed, the second opening is formed；
S6：Cutting for the first side wall is selected according to the length range of the floating boom and the cross-sectional width of first open bottom
Face width, and form first side wall in the side wall of second opening；
S7：Using first side wall as mask, the floating gate layer of second open bottom is removed, forms floating boom.
It is to etch described first by mask of the first side wall when forming floating boom due to separating different flash cells
The floating gate layer of side wall bottom adjusts the length of the floating boom of formation by adjusting the cross-sectional width of first side wall, to ensure
The floating boom of formation avoids the performance of device from changing in its length range.
Specifically, please referring to Fig.2 to Figure 12, for the semiconductor structure formed using the preparation method of the flash cell
Diagrammatic cross-section.Next, by being further described to the preparation method of the flash cell in conjunction with Fig. 2 to Figure 12.
The parameter of the flush memory device formed as needed first determines the length model of floating boom in flash cell to be formed
It encloses, in the present embodiment, the length of the floating boom needed to form is between 90nm~95nn, certainly, when the flush memory device of formation is different
When, the length range of the floating boom can change correspondingly, and no longer illustrate one by one herein.
Referring to Fig. 2, providing a substrate 1, the material of the substrate 1 is preferably silicon, can be specifically monocrystalline silicon, polycrystalline
Silicon etc. on silicon, insulator；It can also be the materials such as germanium, SiGe, GaAs.It is sequentially formed with floating boom on the substrate 1
Layer 2, control grid layer 3 and dielectric layer 4, the floating gate layer 2 and the material of the control grid layer 3 may each be polycrystalline silicon material, institute
The material for stating dielectric layer 4 can be one or more of silica, silicon nitride, silicon oxynitride, low-K dielectric, super low-K dielectric group
It closes.An insulating layer, e.g. silicon oxide layer can also be formed between the substrate 1 and the floating gate layer 2, be used for isolation liner bottom 1
With floating gate layer 2, the floating gate layer 2 and the control grid layer 3 for forming floating boom and control gate in the subsequent process.The floating boom
A separation layer can also be formed between layer 2 and the control grid layer 3, for being isolated floating boom and control gate, the separation layer can be with
For the composite construction layer of oxidenitride oxide (ONO).
Next, etching the dielectric layer 4, control grid layer 3 and floating gate layer 2 until exposing substrate, the first opening is formed,
Then the cross-sectional width of first open bottom is measured, in the present embodiment, the cross-sectional width of first open bottom exists
Between 60nm~65nm.
Specifically, referring to Fig. 3, etch the dielectric layer 4 using dry etching until exposing control grid layer 3, formed
First groove 51.Then, as shown in figure 4, forming the second side wall 62 on the side wall of the first groove 51, further, it is possible to
Certain thickness oxidation is deposited on the inner wall and the dielectric layer 4 of the first groove 51 using the method for low pressure gas phase deposition
Silicon layer can carry out short annealing after deposition, to enhance the step coverage and compactness of side wall, finally etch the first groove
Silicon oxide layer on 51 bottom walls and dielectric layer 4 forms the second side wall 62.Then, referring to Fig. 5, being with second side wall 62
Mask etches the control grid layer 3 of 51 bottom of the first groove to expose floating gate layer 2, second groove 52 is formed, such as Fig. 6 institutes
Show, then forms third side wall 63 in the side wall of the second groove 52 and second side wall 62 again.Next, please referring to figure
7, it is mask with the third side wall 63, etches the floating gate layer 2 of 52 bottom of the second groove to expose substrate 1, forms the
Three grooves 53.First opening includes the first groove 51, second groove 52 and third groove 53, and described first opens
The cross-sectional width of mouth bottom is the cross-sectional width of 53 bottom of third groove.After forming third groove 53, described the is measured
The cross-sectional width of three grooves, 53 bottom, then form the 4th side wall in the side wall of the third groove 53 and the third side wall 63
64, it is specific as shown in Figure 8.Further, the third side wall 63, the material of the 4th side wall 64 and forming method can with it is described
Second side wall 62 is identical.
Further, it is mask with the third side wall 63, when etching the floating gate layer 2, anisotropic can be used first
Lithographic method etched portions thickness floating gate layer 2, keep the surface of the floating gate layer 2 of the residual thickness arc-shaped, then using each
The floating gate layer 2 of the lithographic method etching residual thickness of the item same sex forms floating boom tip after two steps etch.
Then referring to Fig. 9, forming polysilicon material layer, the polysilicon material layer covers the dielectric layer 4 and fills
The third groove 53, then to polysilicon material layer progress chemical-mechanical planarization up to exposing the dielectric layer 4,
The polysilicon layer retained in the third groove 53 will form wordline in subsequent technique.
0- Figure 12 is please referred to Fig.1, the dielectric layer 4 is removed, forms the second opening 54, second opening 54 exposes
The control grid layer 3 needs the side wall in second opening 54 to form the first side wall to separate different flash cells
61, then with first side wall 61 be mask, the control grid layer 3 and floating gate layer 2 of 54 bottoms of the second opening of etching, to form control
Grid 31 and floating boom 21.As shown in Figure 10, etch it is described second opening 54 bottoms control grid layer 3 and floating gate layer 2 when, it is described
First side wall 61 can protect floating gate layer 2 to be below not etched, and even described first side wall 61 is thicker, the floating boom 21 of formation
Just longer, first side wall 61 is relatively thin, and the floating boom 21 of formation is shorter, thus in the flash cell each floating boom 21 length
It is that can be adjusted by the cross-sectional width of first side wall 61.
Next, passing through the length model of floating boom in the cross-sectional width of the first opening bottom wall and flash cell to be formed
It encloses, selects the cross-sectional width of first side wall 61, for example, when etching first opening and generating error, as will be described the
One opening carves width, and the cross-sectional width of first side wall 61 is constant, then the length for the floating boom being actually formed can be partially short, then
It is suitable to be selected by the length range of floating boom in the cross-sectional width of the first opening bottom wall and flash cell to be formed
The first thicker side wall 61, to make up the length of the floating boom more etched away in the first opening；It is narrow when the first opening quarter
, the length for the floating boom being actually formed can grow partially, after the cross-sectional width for measuring the first opening bottom wall, can select one
The first relatively thin side wall 61 makes the floating gate layer 2 of second opening, 54 bottoms carve a part by more.It is open by described first
Cutting for first side wall 61 is adaptively adjusted in the length range of floating boom in the cross-sectional width of bottom wall and flash cell to be formed
Face width, it is ensured that the length for the floating boom 21 being subsequently formed avoids the performance change of device in its length range.
Finally please refer to Fig.1 1, it is determined that after the cross-sectional width of first side wall 61, in the side of second opening 54
Wall forms first side wall 61, and the cross-sectional width of first side wall 61 is between 300 angstroms~1000 angstroms.Again with described first
Side wall 61 is mask, and the control grid layer 3 and floating gate layer 2 of 54 bottoms of etching second opening form control gate 31 and floating boom 21.
As shown in figure 12, the 5th side wall 65 is formed in the side wall of second opening 54 and the side wall of first side wall 61, with protection
The control gate 31 and floating boom 21.
In addition, be not limited only to flash cell, the present embodiment additionally provides a kind of preparation method of semiconductor structure, described half
The preparation method of conductor structure is using the step as above-mentioned flash cell preparation method come in adjusting control semiconductor structure
Floating boom or selection gate length, details are not described herein for specific steps.
To sum up, in the preparation method of flash cell provided in an embodiment of the present invention and semiconductor structure, it is first determined wait for
Then the length range of floating boom in the flash cell of formation etches the dielectric layer and the floating gate layer again, form the first opening,
The cross-sectional width of first open bottom is measured, and polycrystalline silicon material is filled in first opening；Remove the medium
Layer forms the second opening；The first side is selected according to the length range of the floating boom and the cross-sectional width of first open bottom
The cross-sectional width of wall, and form first side wall in the side wall of second opening.Since different flash cells being separated
It is the floating gate layer that first side wall bottom is etched using the first side wall as mask and when forming floating boom, by adjusting described
The cross-sectional width of one side wall adjusts the length of the floating boom of formation, to ensure that the floating boom formed in its length range, avoids device
The performance of part changes.
The preferred embodiment of the present invention is above are only, does not play the role of any restrictions to the present invention.Belonging to any
Those skilled in the art, in the range of not departing from technical scheme of the present invention, to the invention discloses technical solution and
Technology contents make the variations such as any type of equivalent replacement or modification, belong to the content without departing from technical scheme of the present invention, still
Within belonging to the scope of protection of the present invention.
Claims (12)
1. a kind of preparation method of flash cell, which is characterized in that the preparation method of the flash cell includes：
Determine the length range of floating boom in flash cell to be formed；
Substrate is provided, floating gate layer and dielectric layer are sequentially formed on the substrate；
The dielectric layer and the floating gate layer are etched, the first opening is formed, first opening exposes the substrate；
The cross-sectional width of first open bottom is measured, and polycrystalline silicon material is filled in first opening；
The dielectric layer is removed, the second opening is formed；
The cross-sectional width of the first side wall is selected according to the length range of the floating boom and the cross-sectional width of first open bottom,
And form first side wall in the side wall of second opening；
Using first side wall as mask, the floating gate layer of second open bottom is removed, forms floating boom.
2. the preparation method of flash cell as described in claim 1, which is characterized in that the length range of the floating boom includes
90nm~95nm.
3. the preparation method of flash cell as claimed in claim 2, which is characterized in that the section of first open bottom is wide
Degree includes 60nm~65nm.
4. the preparation method of flash cell as claimed in claim 2, which is characterized in that the cross-sectional width packet of first side wall
Include 200 angstroms~1000 angstroms.
5. the preparation method of flash cell as described in claim 1, which is characterized in that the floating gate layer and the dielectric layer it
Between be also formed with control grid layer.
6. the preparation method of flash cell as claimed in claim 5, which is characterized in that etch the dielectric layer and the floating boom
Layer, forms the first opening, and first opening exposes the substrate and includes：
The dielectric layer is etched, first groove is formed, the first groove exposes the control grid layer；
The second side wall is formed in the side wall of the first groove；
Using second side wall as mask, the control grid layer is etched, forms second groove, the second groove exposes described
Floating gate layer；
Third side wall is formed in the side wall of the second groove and first side wall；
Using the third side wall as mask, the floating gate layer is etched, forms third groove, the third groove exposes the lining
Bottom；
The 4th side wall is formed in the side wall of the third groove and the third side wall.
7. the preparation method of flash cell as claimed in claim 6, which is characterized in that the section of the third channel bottom is wide
Cross-sectional width of the degree equal to first open bottom.
8. the preparation method of flash cell as claimed in claim 6, which is characterized in that using the third side wall as mask, carve
The floating gate layer is lost, third groove is formed, the third groove exposes the substrate and includes：
Using the floating gate layer of the lithographic method etched portions thickness of anisotropic,
The floating gate layer of residual thickness is etched using the lithographic method of isotropic, forms floating boom tip.
9. the preparation method of flash cell as claimed in claim 8, which is characterized in that fill polycrystalline in first opening
The step of silicon materials includes：
Polysilicon material layer is formed, the polysilicon material layer covers the dielectric layer and fills the third groove；
The polysilicon material layer is planarized, until exposing the dielectric layer.
10. the preparation method of flash cell as claimed in claim 9, which is characterized in that the step of forming the floating boom include：
Using first side wall as mask, the floating gate layer of second open bottom is removed, the floating boom and the 4th groove are formed；
The 5th side wall is formed in the side wall of the 4th groove and first side wall.
11. the preparation method of flash cell as described in claim 1, which is characterized in that the material of the dielectric layer includes oxygen
At least one of SiClx, silicon nitride or silicon oxynitride.
12. a kind of preparation method of semiconductor structure, which is characterized in that using the sudden strain of a muscle as described in any one of claim 1-11
The preparation method of memory cell.
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| CN113611745A (en) * | 2021-07-30 | 2021-11-05 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN113611745B (en) * | 2021-07-30 | 2024-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN114267594A (en) * | 2021-12-21 | 2022-04-01 | 华虹半导体(无锡)有限公司 | Method for forming semiconductor structure |
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Application publication date: 20180914 |