CN1085369C - Data output interface circuit of optical disk driving recording system - Google Patents
Data output interface circuit of optical disk driving recording system Download PDFInfo
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- CN1085369C CN1085369C CN96103485A CN96103485A CN1085369C CN 1085369 C CN1085369 C CN 1085369C CN 96103485 A CN96103485 A CN 96103485A CN 96103485 A CN96103485 A CN 96103485A CN 1085369 C CN1085369 C CN 1085369C
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- 230000003287 optical effect Effects 0.000 title abstract description 8
- 230000005540 biological transmission Effects 0.000 claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 claims abstract description 12
- 230000001052 transient effect Effects 0.000 claims description 12
- 230000008030 elimination Effects 0.000 claims description 5
- 238000003379 elimination reaction Methods 0.000 claims description 5
- 230000001131 transforming effect Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 4
- 241001269238 Data Species 0.000 description 3
- 230000005055 memory storage Effects 0.000 description 2
- 210000001367 artery Anatomy 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/004—Recording, reproducing or erasing methods; Read, write or erase circuits therefor
- G11B7/005—Reproducing
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- Engineering & Computer Science (AREA)
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- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
一种光盘驱动记录系统，特别是一种根据数据信号输出声频数据的数据输出接口装置。该光盘驱动记录系统的数据输出接口装置包括一个存储器和一个数据输出接口装置，存储器存储收自预定信号处理器的数据，数据输出接口装置根据数据传输信号的输入访问存储器从而接收给定单位的数据和表示数据间隔中处于产生误差的状态的错误位，产生预定的基准时钟和字节时钟，使数据的并行转换与预定的基准时钟同步化，并对对应于表示有误差产生的错误位的“0”状态输出数据。
An optical disc drive recording system, in particular a data output interface device for outputting audio data according to data signals. The data output interface device of the optical disk drive recording system includes a memory and a data output interface device, the memory stores data received from a predetermined signal processor, and the data output interface device accesses the memory according to the input of the data transmission signal to receive data of a given unit and the error bit indicating that an error has occurred in the data interval, generate a predetermined reference clock and a byte clock, synchronize the parallel conversion of data with the predetermined reference clock, and "0" state output data.
Description
The present invention relates to a kind of optical disk driving recording system, more particularly, relate to a kind of response data and transmit the needed signal data output interface device of output audio data then.
The example of optical disk driving recording system is the compact disk player normally.The korean patent application 94-2311 of applicant's application of the present invention discloses this technology.
Above-mentioned optical disk driving recording system has a storer and a data output interface circuit 20, the signal that storer will read from the CD as recording medium is decoded by the signal processor such as EFM (eight to 14 modulation) demoder (not shown) and with data output, data output interface circuit 20 outputs are stored in the data in the storer and handle the data of being exported.Fig. 1 is the circuit diagram of the general data output interface circuit that proposes among the above-mentioned korean patent application 94-2311.In this compact disk player, in the time of need transmitting data, the data of 212 bytes just send successively at every turn, and its data transmission period figure as shown in Figure 2.
Bit clock shown in Fig. 2 (2a) from data output interface circuit 20 export to data transmission need with the treatment circuit 30 (being hereinafter referred to as data processing circuit 30) of the data that receive, the signal (being hereinafter referred to as data-signal) that the data transmission of logic " low " level shown in Fig. 2 (2b) need be used is input to data output interface circuit 20 from data processing circuit 30.Data shown in Fig. 2 (2c) send data processing circuit 30 to from data output interface circuit 20, whether the byte clock shown in Fig. 2 (2d) is exported to data processing circuit 30 from data output interface circuit 20, have error to exist in the data that the error signal shown in Fig. 2 (2e) is represented to be transmitted.Time diagram shown in Fig. 2 is the transmission time of a word of data, in view of the data that must transmit 212 bytes in the compact disk player, thereby the timing operation of Fig. 2 should be repeated 106 times.
The course of work of general data output interface circuit is described referring to Fig. 1 and Fig. 2 below.
When the data-signal shown in Fig. 2 (2b) was input to data output interface circuit 20, interface circuit 20 read the corresponding data shown in (2c) of Fig. 2 from storer 10.After this, data output interface circuit 20 sends the data that read to data processing circuit 30 successively with the form of byte units.At this moment, the bit clock shown in Fig. 2 (2a), its frequency is about 5.65 megahertzes.Meanwhile, data output interface circuit 20 reads the error signal that whether has error to exist the data shown in (2c) of the presentation graphs 2 shown in (2e) of Fig. 2 from storer 10, and during 1 byte interval of the data shown in (2c) of Fig. 2 with read and want that the signal that transmits sends data processing circuit 30 to the form of 1 bit location.Being illustrated in when in other words, error signal is in logic " height " attitude in the 1 byte transmission data shown in (2c) of Fig. 2 has error to exist.When the data-signal shown in Fig. 2 (b) is in logic " height " attitude in the drop edge of the byte clock second round shown in Fig. 2 (2d), finished the data transmission of a word, thereby carried out 106 times data transfer operation, thereby the data of 212 bytes have been transmitted.
Yet, such problem is arranged: even traditional data output interface circuit sends the data that error is arranged also for data processing circuit 30 under the situation of error originated from input signal.In addition, also have such problem: traditional data output interface circuit has transient pulse to disturb in data transfer signal can not the normal transmission data when taking place.
Thereby therefore the purpose of this invention is to provide a kind of in the time may producing error, data are removed can transmit effectively data through improved data output interface device.
Even another object of the present invention provides a kind of data output interface device that also can the normal transmission data when having error to produce in data-signal.
For reaching above-mentioned and other purpose, a kind of data output interface device of optical disk driving recording system provided by the invention is characterized in that it comprises: memory storage, for the data of storage receipts from the predetermined signal processing device; And data output interface circuit, has the transient pulse interference cancellation circuit, disturb in order to the transient pulse of eliminating the data transfer signal input, eliminate circuit with misdata, in order to input according to data transfer signal, the misdata of elimination in the data break that above-mentioned memory storage is read produces predetermined reference clock and byte clock, so that make the parallel conversion and predetermined reference clock synchronization of above-mentioned data.
Describe content of the present invention in detail referring to accompanying drawing below.Same numbering is represented identical or similar elements in the accompanying drawing.
Fig. 1 is the block scheme of traditional data output interface device;
Fig. 2 is the time diagram of Fig. 1;
Fig. 3 is the block scheme by the data output interface device of principle body plan of the present invention;
Fig. 4 is the time diagram of Fig. 3;
Fig. 5 is the detailed circuit diagram of Fig. 3 part-structure;
Fig. 6 is the time diagram of Fig. 5;
Fig. 7 is the detailed circuit diagram of Fig. 3 another part structure.
Fig. 3 is the block scheme by the Data Input Interface device of principle body plan of the present invention.Equipment among the figure comprises: storer 10, in order to the data of storage receipts from the predetermined signal processing device; Data output interface device 200 in order to give storer 10 output address datas according to the data-signal of input, receives and the employed data of output address data, and generation and output byte clock, so that data sync is conveyed to bit clock as reference clock; With data processing circuit 30, in order to produce the data transmission desired signal and to pass through to receive data, bit clock and byte clock with deal with data.
In the structure of Fig. 3, data output interface circuit 200 is according to the data-signal access and transmit the data that are stored in the storer 10.In addition, the data that send from data output interface circuit 200 are expanded data processing circuit 30 with predetermined algorithm.At this moment, the unit of account of data processing circuit 30 is 212 bytes.In other words, storer 10 is unit storage data with 212 bytes, and passes through data output interface circuit 200 by 212 byte output datas when receiving that requiring of data transmitted in requirement.In addition, storer 10 is the storage errors position, and whether each represents to have in the data of 212 bytes error to exist.Therefore, though data processing circuit 30 has been received error information, the present invention becomes particular value (for example " 0 " value) with data-switching and transmits through the data converted value, thereby does not transmit error signal.
Fig. 4 is the time diagram of Fig. 3.Position clock shown in Fig. 4 (4a) is the reference clock of data output interface circuit 200, and the data-signal shown in 4 (b) of Fig. 4 is the signal of data processing circuit 30.Data shown in Fig. 4 (4c) are the data that send successively from data output interface circuit 200, and the byte clock shown in 4 (d) of Fig. 4 is the clock of data output interface circuit 200 generation/outputs.
Fig. 5 is the detailed circuit diagram of transient pulse interference cancellation circuit of the data output interface circuit 200 of Fig. 3.The data transfer signal importation comprises first D flip-flop 210, transducer 220 and second D flip-flop 230.First D flip-flop 210 receives and bit clock data in synchronization signal, and locking and the signal received of output, transducer 220 receives bit clock, and the bit clock received of conversion and output, the 2nd D type triggers along receiving from the bit clock of transducer 220 through conversion, and the output signal of synchronous first D flip-flop 210 of locking and output and the bit clock received.
Fig. 6 is the time diagram of Fig. 5, and wherein waveform (6a) expression is input to the data transfer signal of first D flip-flop 210, (6b) expression bit clock, (6c) output signal of expression second D flip-flop 230.
Fig. 7 is a detailed circuit diagram of removing a structure of the data that contain the error that produces in Fig. 3 data output interface circuit 200.Be equiped with transducer 240 and AND gate 250 in the structure, transducer 240 receives receives the error bit of receiving from the error bit of storer 10 and conversion and output, AND gate 250 is in order to receive respectively from the output data of storer 10 and the error bit of 240 conversion of transducer, and carry out AND operation, thereby the result of output AND operation.
Referring now to Fig. 3 to Fig. 7, the operating process of most preferred embodiment of the present invention is described.
When the data-signal shown in Fig. 4 (4b) was imported from data processing circuit 30, the transient pulse that data output interface circuit 200 is removed in the data-signal of being imported disturbed.In other words, owing to the initiating signal of data-signal as data transmission works, thereby disturb because of ectocine produces transient pulse in the data-signal, transient pulse interference cancellation circuit shown in Figure 5 can prevent data output interface circuit 200 imbalances.In Fig. 5 and Fig. 6 clear data the process that the transient pulse of signal disturbs, data-signal from the data processing circuit input shown in Fig. 6 (6a) is in the lock state and exports when being in the rising edge by (6b) of first D flip-flop 210 at bit clock such as Fig. 6, and when being in drop edge shown in (6b) of Fig. 6, bit clock enters lock-out state, the such output away shown in Fig. 6 (6c) then by second D flip-flop 230.Like this, because (6b) bit clock has locked data-signal 6a, thereby the transient pulse that produces during locking disturbs the not influence of data transfer operation to data output interface circuit 200.
Data output interface circuit 200 is as follows according to the process of data signal transmission data.Storing data and error bit that external signal processor (for example EFM demoder) sends in the storer 10.Therefore, when data-signal is imported from data processing circuit 30, thereby data output interface circuit 200 is just according to message reference storer 10 reading of data and the error bit imported.At this moment, data are exactly the audio compression signal of compact disk player etc. for example.The data volume that reads from storer 10 is 212 bytes, the expansion part of expression data processing circuit 30 audio signals.In addition, when data-signal was imported from data processing circuit 30, data output interface circuit 200 was just given data processing circuit 30 output byte clock and bit clocks according to the signal of input.Referring to Fig. 4, data are to begin to transmit when the data-signal that data processing circuit 30 inputs come drops to logic " low " attitude.The cycle of byte clock by 8 bit periods of transmission data, promptly convert the conversion of 8 bit location parallel datas in the data processing circuit 30 to this byte clock.
On the other hand, in the process of transmission data, data output interface circuit 200 is from the corresponding error bit of storer 10 reading of data, and when error produces all data stationary arrived " 0 " state.Transmit data then, but transport error bit not.In other words, as shown in Figure 7, second transducer 240 receive be in logic " height " attitude represent to have error bit that corresponding data error at interval produces and output logic " low " attitude, through the signal of conversion.250 pairs of AND gates through the signal of conversion and from the data of storer 10 carry out " with " handle, and produce data and be input in the data processing circuit 30.
In sum, the present invention has such benefit: owing to eliminated the instantaneous arteries and veins of data signals Punching is disturbed, thereby can avoid the data output interface circuit imbalance, and transmission line is not because transferring mistake Miss the position and the structure system that can conform to the principle of simplicity, and the data treatment circuit can not carry out locating of other error bit again The reason operation.
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR13290/95 | 1995-05-25 | ||
| KR1019950013290A KR0180790B1 (en) | 1995-05-25 | 1995-05-25 | Data output interface device of optical disk drive recording device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1138726A CN1138726A (en) | 1996-12-25 |
| CN1085369C true CN1085369C (en) | 2002-05-22 |
Family
ID=19415427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96103485A Expired - Fee Related CN1085369C (en) | 1995-05-25 | 1996-02-29 | Data output interface circuit of optical disk driving recording system |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2823831B2 (en) |
| KR (1) | KR0180790B1 (en) |
| CN (1) | CN1085369C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3530388B2 (en) * | 1998-07-22 | 2004-05-24 | 三洋電機株式会社 | Code error correction device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0089021A2 (en) * | 1982-03-15 | 1983-09-21 | Kabushiki Kaisha Toshiba | Overlay recording prevention device for optical disc apparatus |
| US5185734A (en) * | 1990-07-20 | 1993-02-09 | International Business Machines Corporation | Calibrating and power-protecting laser drive circuits |
-
1995
- 1995-05-25 KR KR1019950013290A patent/KR0180790B1/en not_active IP Right Cessation
-
1996
- 1996-02-22 JP JP8034967A patent/JP2823831B2/en not_active Expired - Fee Related
- 1996-02-29 CN CN96103485A patent/CN1085369C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0089021A2 (en) * | 1982-03-15 | 1983-09-21 | Kabushiki Kaisha Toshiba | Overlay recording prevention device for optical disc apparatus |
| US5185734A (en) * | 1990-07-20 | 1993-02-09 | International Business Machines Corporation | Calibrating and power-protecting laser drive circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1138726A (en) | 1996-12-25 |
| KR0180790B1 (en) | 1999-04-15 |
| JP2823831B2 (en) | 1998-11-11 |
| KR960042713A (en) | 1996-12-21 |
| JPH08321134A (en) | 1996-12-03 |
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| SE01 | Entry into force of request for substantive examination | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20020522 |