CN108461512A - wafer bonding structure and wafer bonding method - Google Patents
wafer bonding structure and wafer bonding method Download PDFInfo
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- CN108461512A CN108461512A CN201810108058.6A CN201810108058A CN108461512A CN 108461512 A CN108461512 A CN 108461512A CN 201810108058 A CN201810108058 A CN 201810108058A CN 108461512 A CN108461512 A CN 108461512A
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- 238000000034 method Methods 0.000 title claims abstract description 59
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 239000000376 reactant Substances 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 abstract 7
- 238000000576 coating method Methods 0.000 abstract 7
- 235000012431 wafers Nutrition 0.000 abstract 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The present invention provides a kind of wafer bonding structure and wafer bonding methods, after forming the first oxide skin(coating), also form the second oxide skin(coating), the consistency of consistency first oxide skin(coating) of second oxide skin(coating) is high, so that the second oxide skin(coating) first oxide skin(coating) has higher adhesiveness, to by second oxide skin(coating) by device wafers and load wafer bonding together when can improve device wafers and load wafer between bonding force, improve and be formed by wafer bonding reliability of structure.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a wafer bonding structure and a wafer bonding method.
Background
In recent years, as the pixel value of an image sensor (CIS) chip is increased, the physical size of a single pixel of the sensor is reduced, so that the manufacturing process of an integrated circuit for a sensor part in the chip is complicated, and the part is difficult to manufacture in the same process with a signal processing module. In addition, as the photosensitive area of a single pixel becomes smaller, there is a severe limitation on the amount of incident photons in order to prevent image distortion.
In the prior wafer level packaging, interconnection lines are made from the back of a wafer, photons enter a pixel photosensitive area from the front of the wafer through a metal interconnection layer, and the complex metal interconnection layer often blocks a part of the photons, so that the number of the photons obtained from the photosensitive area cannot meet the requirement of imaging. In order to solve the above problems, the current package tends to adopt a backside illumination (BSI) process to transfer a circuit portion originally located between the lens and the photosensitive semiconductor to the periphery or under the photosensitive semiconductor, so that light can directly enter the photosensitive region, blocking of the interconnection line to the light is prevented, and the utilization efficiency of a single pixel unit to the light is greatly improved.
Backside illuminated wafer level packaging requires grinding the backside of the wafer to about 5 μm to allow light to pass through the silicon activated photo-sensing region, and the 5 μm wafer support capability is limited, requiring the use of a load wafer on the front side of the wafer. At present, a common process is a process of using a load wafer as a support to thin the back of a device wafer, using a microlens and a filter on the back of the thinned wafer, then using a sealing cover to protect the surface, continuously thinning the load wafer, using a TSV (through silicon via) process and an RDL (redistribution layer) process on the load wafer to lead out a bonding pad (pad), and finally cutting the wafer into single chips.
The support of the load wafer to the device wafer is typically achieved by bonding the load wafer and the device wafer together. In the prior art, the adhesive force between the load wafer and the device wafer is not strong, so that the reliability problems such as cracking and the like are easy to occur in the subsequent process.
Disclosure of Invention
The invention aims to provide a wafer bonding structure and a wafer bonding method, which are used for solving/relieving the problem of weak bonding force between a load wafer and a device wafer in the prior art.
In order to solve the above technical problem, the present invention provides a wafer bonding method, including:
forming a first oxide layer on a device wafer;
forming a second oxide layer on the device wafer, wherein the second oxide layer covers the first oxide layer, and the density of the second oxide layer is higher than that of the first oxide layer;
bonding the second oxide layer on the device wafer to a carrier wafer.
Optionally, in the wafer bonding method, the first oxide layer and the second oxide layer are made of the same material.
Optionally, in the wafer bonding method, the first oxide layer and the second oxide layer are made of silicon oxide.
Optionally, in the wafer bonding method, the reactants used in the first silicon oxide layer and the second silicon oxide layer both include tetraethoxysilane and oxygen.
Optionally, in the wafer bonding method, the first oxide layer and the second oxide layer are both formed by a plasma enhanced chemical vapor deposition process.
Optionally, in the wafer bonding method, the high-frequency power used for forming the second oxide layer is 60% to 70% of the high-frequency power used for forming the first oxide layer, and the low-frequency power used for forming the second oxide layer is 75% to 85% of the low-frequency power used for forming the first oxide layer.
Optionally, in the wafer bonding method, a difference between a temperature used for forming the second oxide layer and a temperature used for forming the first oxide layer is less than or equal to 5 ℃, and a difference between a pressure used for forming the second oxide layer and a pressure used for forming the first oxide layer is less than or equal to 1 Torr.
Optionally, in the wafer bonding method, the thickness of the first oxide layer is between 1 μm and 5 μm, and the thickness of the second oxide layer is between 100 angstroms and 1000 angstroms.
Optionally, in the wafer bonding method, after the first oxide layer is formed and before the second oxide layer is formed, the wafer bonding further includes: a planarization process is performed on the first oxide layer.
The invention also provides a wafer bonding structure, which comprises:
a device wafer;
a first oxide layer formed on the device wafer;
a second oxide layer formed on the device wafer, the second oxide layer covering the first oxide layer, the second oxide layer having a density higher than that of the first oxide layer;
a load wafer bonded together with the second oxide layer on the device wafer.
In the wafer bonding structure and the wafer bonding method provided by the invention, after the first oxide layer is formed, the second oxide layer is further formed, and the density of the second oxide layer is higher than that of the first oxide layer, so that the second oxide layer has higher adhesiveness than that of the first oxide layer, and therefore, when the device wafer and the load wafer are bonded together through the second oxide layer, the adhesive force between the device wafer and the load wafer can be improved, and the reliability of the formed wafer bonding structure is improved.
Drawings
FIGS. 1-2 are cross-sectional views of structures formed by a wafer bonding method;
FIGS. 3-6 are cross-sectional views of structures formed by a wafer bonding method according to an embodiment of the invention;
wherein,
100-a device wafer; 110-oxide layer; 120-load wafer;
200-a device wafer; 210-a first oxide layer; 220-a second oxide layer; 230-load wafer.
Detailed Description
The wafer bonding structure and the wafer bonding method according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
First, please refer to fig. 1to 2, which are schematic cross-sectional views of a structure formed by a wafer bonding method. As shown in fig. 1 and 2, a wafer bonding method specifically includes the following steps: forming an oxide layer 110 on a device wafer 100; the oxide layer 110 on the device wafer 100 is then bonded to a carrier wafer 120. The oxide layer 110 is formed by a plasma enhanced chemical vapor deposition process, the high-frequency power used for forming the oxide layer 110 is 600W-900W, and the low-frequency power used for forming the oxide layer 110 is 100W-400W. Experimental detection shows thatThe bonding force of the formed wafer bonding structure is between 0.8J/m2～1.1J/m2In the meantime.
The adhesion force (of the size) cannot well meet the requirements of the subsequent process, and the reliability problems such as splintering and the like still occur. On the basis, the inventor makes further research and proposes the following wafer bonding method, which specifically comprises the following steps:
forming a first oxide layer on a device wafer;
forming a second oxide layer on the device wafer, wherein the second oxide layer covers the first oxide layer, and the density of the second oxide layer is higher than that of the first oxide layer;
bonding the second oxide layer on the device wafer to a carrier wafer.
In the wafer bonding method, after the first oxide layer is formed, the second oxide layer is further formed, and the density of the second oxide layer is higher than that of the first oxide layer, so that the second oxide layer has higher adhesion than that of the first oxide layer, and therefore, when the device wafer and the load wafer are bonded together through the second oxide layer, the adhesion between the device wafer and the load wafer can be improved, and the reliability of the formed wafer bonding structure is improved.
Specifically, please refer to fig. 3to 6, which are schematic cross-sectional views of structures formed by the wafer bonding method according to an embodiment of the invention.
First, as shown in fig. 3, a device wafer 200 is provided, and in the embodiment of the present disclosure, a pixel array including a plurality of pixel units (not shown) may be formed in the device wafer 200. The pixel array may include a plurality of pixel units arranged in rows and columns, and the pixel units may include photosensitive elements, such as photodiodes, phototransistors, and the like. Further, a plurality of transmission gates (not shown) may be formed in the device wafer 200, and the transmission gates are electrically connected to the pixel units.
With continued reference to fig. 3, in the present embodiment, a first oxide layer 210 is then formed on the device wafer 200. The material of the first oxide layer 210 is preferably silicon oxide, the material of the device wafer 200 is usually silicon, and the first oxide layer 210 selected from the silicon oxide material can be well bonded with the device wafer 200.
Preferably, the first oxide layer 210 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Specifically, the high frequency power used for forming the first oxide layer 210 is between 600W and 900W, and for example, the high frequency power used for forming the first oxide layer 210 is 600W, 650W, 700W, 750W, 800W, 850W, 900W, or the like. The low frequency power used for forming the first oxide layer 210 is between 100W and 400W, for example, the low frequency power used for forming the first oxide layer 210 is 100W, 150W, 200W, 250W, 300W, 350W, or 400W. Further, the process temperature for forming the first oxide layer 210 may be between 400 ℃ and 700 ℃, for example, the process temperature for forming the first oxide layer 210 is 400 ℃, 450 ℃, 500 ℃, 550 ℃, 600 ℃, 620 ℃, 680 ℃, or 700 ℃. Further, the pressure used for forming the first oxide layer 210 may be in a range of 3to 7Torr, and for example, the pressure used for forming the first oxide layer 210 is 3Torr, 3.5Torr, 4.2Torr, 4.6Torr, 5Torr, 5.5Torr, 6Torr, 6.5Torr, 7Torr, or the like.
The reactant used for the first oxide layer 210 may include tetraethyl orthosilicate (TEOS) and oxygen (O)2). Wherein, the amount of the oxygen introduced into the reaction chamber can be higher than the amount of the tetraethoxysilane introduced into the reaction chamber. For example, the ratio of the amount of oxygen introduced into the reaction chamber to the amount of tetraethoxysilane introduced into the reaction chamber may be between 3: 1to 20: 1. Preferably, the thickness of the first oxide layer 210 is between 1 μm and 5 μm, for example, the thickness of the first oxide layer 210The thickness is 1 μm, 1.5 μm, 2 μm, 3 μm, 3.5 μm, 4 μm, 4.7 μm, or 5 μm, etc.
Referring to fig. 4, in the present embodiment, after the first oxide layer 210 is formed, a planarization process is performed on the first oxide layer 210 to improve the flatness of the surface of the first oxide layer 210. Specifically, a planarization process may be performed on the first oxide layer 210 using a Chemical Mechanical Polishing (CMP) process. Considering that the thickness of the first oxide layer 210 is reduced after the planarization process is performed on the first oxide layer 210, the thickness of the first oxide layer 210 formed may also be increased on the basis of a target thickness when the first oxide layer 210 is formed through a plasma enhanced chemical vapor deposition process.
Referring to fig. 5, a second oxide layer 220 is formed on the device wafer 200, the second oxide layer 220 covers the first oxide layer 210, and the density of the second oxide layer 220 is higher than that of the first oxide layer 210. Preferably, the second oxide layer 220 and the first oxide layer 210 are made of the same material, so that the adhesive force between the second oxide layer 220 and the first oxide layer 210 can be improved. In the embodiment, the material of the second oxide layer 220 is selected from silicon oxide.
Preferably, the second oxide layer 220 is formed by a plasma enhanced chemical vapor deposition process. Preferably, the high frequency power used to form the second oxide layer 220 is 60% to 70% of the high frequency power used to form the first oxide layer 210, and the low frequency power used to form the second oxide layer 220 is 75% to 85% of the low frequency power used to form the first oxide layer 210. In the embodiment of the present application, the adhesion of the second oxide layer 220 formed is improved by changing the high frequency power and the low frequency power for forming the second oxide layer 220.
Further, a difference between a temperature used for forming the second oxide layer 220 and a temperature used for forming the first oxide layer 210 is 5 ℃ or less, and a difference between a pressure used for forming the second oxide layer 220 and a pressure used for forming the first oxide layer 210 is 1Torr or less. Preferably, the temperature for forming the second oxide layer 220 is the same as the temperature for forming the first oxide layer 210, and the pressure for forming the second oxide layer 220 is the same as the pressure for forming the first oxide layer 210, i.e., the temperature and pressure for forming the second oxide layer 220 and the temperature and pressure for forming the first oxide layer 210 are kept constant, so that the process control can be simplified.
Specifically, the reactant used for the second oxide layer 220 may include tetraethyl orthosilicate (TEOS) and oxygen (O)2). Wherein, the amount of the oxygen introduced into the reaction chamber can be higher than the amount of the tetraethoxysilane introduced into the reaction chamber. For example, the ratio of the amount of oxygen introduced into the reaction chamber to the amount of tetraethoxysilane introduced into the reaction chamber may be between 3: 1to 20: 1. Preferably, the thickness of the second oxide layer 220 is between 100 angstroms and 1000 angstroms, for example, the thickness of the second oxide layer 220 is 100 angstroms, 200 angstroms, 350 angstroms, 500 angstroms, 600 angstroms, 750 angstroms, 900 angstroms or 1000 angstroms.
Next, as shown in fig. 6, the second oxide layer 220 on the device wafer 200 is bonded to a carrier wafer 230. The bonding between the device wafer 200 and the carrier wafer 230 may be formed by a conventional bonding process such as thermal bonding.
Correspondingly, the present embodiment further provides a wafer bonding structure, as shown in fig. 6, the wafer bonding structure includes: a device wafer 200; a first oxide layer 210, the first oxide layer 210 being formed on the device wafer 200; a second oxide layer 220, wherein the second oxide layer 220 is formed on the device wafer 200, the second oxide layer 220 covers the first oxide layer 210, and the density of the second oxide layer 220 is higher than that of the first oxide layer 210; a carrier wafer 230, the carrier wafer 230 bonded to the second oxide layer 220 on the device wafer 200.
The experimental detection shows that the adhesive force of the wafer bonding structure formed by the method is 2.4J/m2～2.6J/m2Meanwhile, the adhesive force of the formed wafer bonding structure is greatly improved, the requirements of subsequent processes are met, and the reliability of the formed wafer bonding structure is improved.
As can be seen from the above, in the wafer bonding structure and the wafer bonding method provided in the embodiments of the present invention, after the first oxide layer is formed, the second oxide layer is further formed, and the density of the second oxide layer is higher than that of the first oxide layer, so that the second oxide layer has higher adhesion than that of the first oxide layer, and thus when the device wafer and the load wafer are bonded together through the second oxide layer, the adhesion between the device wafer and the load wafer can be improved, and the reliability of the formed wafer bonding structure is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A wafer bonding method is characterized by comprising the following steps:
forming a first oxide layer on a device wafer;
forming a second oxide layer on the device wafer, wherein the second oxide layer covers the first oxide layer, and the density of the second oxide layer is higher than that of the first oxide layer;
bonding the second oxide layer on the device wafer to a carrier wafer.
2. The wafer bonding method of claim 1, wherein the first oxide layer and the second oxide layer are made of the same material.
3. The wafer bonding method of claim 2, wherein the first oxide layer and the second oxide layer are made of a material selected from silicon oxide.
4. The wafer bonding method of claim 2, wherein the reactants used for the first silicon oxide layer and the second silicon oxide layer each comprise tetraethylorthosilicate and oxygen.
5. The wafer bonding method of any one of claims 1to 4, wherein the first oxide layer and the second oxide layer are both formed by a plasma enhanced chemical vapor deposition process.
6. The wafer bonding method according to claim 5, wherein the high frequency power used for forming the second oxide layer is 60% to 70% of the high frequency power used for forming the first oxide layer, and the low frequency power used for forming the second oxide layer is 75% to 85% of the low frequency power used for forming the first oxide layer.
7. The wafer bonding method of claim 6, wherein a difference between a temperature used for forming the second oxide layer and a temperature used for forming the first oxide layer is 5 ℃ or less, and a difference between a pressure used for forming the second oxide layer and a pressure used for forming the first oxide layer is 1Torr or less.
8. The wafer bonding method of any one of claims 1to 4, wherein the first oxide layer has a thickness of between 1 μm and 5 μm, and the second oxide layer has a thickness of between 100 angstroms and 1000 angstroms.
9. The wafer bonding method of any of claims 1to 4, wherein after forming the first oxide layer and before forming the second oxide layer, the wafer bonding method further comprises: a planarization process is performed on the first oxide layer.
10. A wafer bonding structure, comprising:
a device wafer;
a first oxide layer formed on the device wafer;
a second oxide layer formed on the device wafer, the second oxide layer covering the first oxide layer, the second oxide layer having a density higher than that of the first oxide layer;
a load wafer bonded together with the second oxide layer on the device wafer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810108058.6A CN108461512A (en) | 2018-02-02 | 2018-02-02 | wafer bonding structure and wafer bonding method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810108058.6A CN108461512A (en) | 2018-02-02 | 2018-02-02 | wafer bonding structure and wafer bonding method |
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| CN108461512A true CN108461512A (en) | 2018-08-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110718453A (en) * | 2019-11-15 | 2020-01-21 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
| DE102023120847B4 (en) | 2022-09-06 | 2024-11-07 | Globalfoundries U.S. Inc. | Bond structure using two oxide layers with different stress levels and corresponding process |
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| CN103065945A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor wafer bonding method |
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| CN103065945A (en) * | 2013-01-14 | 2013-04-24 | 陆伟 | Image sensor wafer bonding method |
| CN103871870A (en) * | 2014-02-28 | 2014-06-18 | 武汉新芯集成电路制造有限公司 | Method for removing wafer bonding edge defect |
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Cited By (3)
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| CN110718453A (en) * | 2019-11-15 | 2020-01-21 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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| DE102023120847B4 (en) | 2022-09-06 | 2024-11-07 | Globalfoundries U.S. Inc. | Bond structure using two oxide layers with different stress levels and corresponding process |
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