CN108449090A - A kind of configurable multi-code is long, multi code Rate of Chinese character ldpc decoder - Google Patents
A kind of configurable multi-code is long, multi code Rate of Chinese character ldpc decoder Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
A kind of configurable multi-code is long, multi code Rate of Chinese character low density parity check code ldpc decoder, which includes three-decker, and top-level module includes storage input Soft Inform ation unit, storage output Soft Inform ation unit, storage verification and unit, encoded control unit, macrodefinition unit, core decoding unit；Core decoding layer module includes initialization unit, iteration control unit, variable information processing unit VPU, check information processing unit CPU, iterative information storage unit, row connected logic units, row logic connection unit, verification unit；It includes verification core cell, verification and computing unit to verify layer module.The decoder can be realized to carry out flexible configuration, and can improve the throughput of decoder to a variety of code lengths, various code rate, is suitable for completing the work decoding of the low density parity check code LDPC to a variety of code lengths, various code rate.
Description
Technical field
The present invention relates to field of communication technology, a kind of configurable multi-code in wireless communication technology field is further related to
Long, multi code Rate of Chinese character low density parity check code LDPC (Low Density Parity Check Code) decoder.The present invention carries
Long, multi code Rate of Chinese character the low density parity check code ldpc decoder structure for a kind of configurable multi-code, the decoding utensil under the structure
There are many code length, various code rates to be compatible with, and the characteristics of code length code check flexibly configurable, is applicable to a variety of code lengths, a variety of
The work decoding of the low density parity check code LDPC of code check.
Background technology
Low density parity check code is a kind of linear block codes with sparse check matrix proposed the 1960s.
Its error performance has flexible structure, the spies such as relatively low, parallel work-flow of decoding complexity very close to shannon limit
Point, is very suitable for hardware realization.Thus channel decoding field in recent years has obtained good development.Low-density parity-check
The code check construction for testing yard LDPC is more flexible, can construct arbitrary bit rate, therefore, for different business demand, compatible different codes
The low density parity check code ldpc decoder of long, different code checks is particularly important.
Chinese Academy of Sciences Microelectronics Institute is (special in a kind of patent document " ldpc decoder of high-throughput " of its application
Sharp application number：200910081094.9 application publication number：CN101854177A it is strange that a kind of high-throughput low-density is disclosed in)
Even parity check code decoder.The decoder includes input-buffer, check-node arithmetic element, variable node arithmetic element, exports and delay
It deposits, control logic unit and internet.Wherein：The decoder uses Partly parallel decoding structure, is transported using x variable node
Calculate unit, y check-node arithmetic element, x and y are respectively the columns and line number of the basis matrix of H, 1 input-buffer, 1
Output caching.Each variable node arithmetic element is made of channel information memory access and external information memory, each check-node
The arithmetic element that arithmetic element calculates input minimum value and input sub-minimum by 1 is constituted.The invention is not increasing hardware consumption
On the basis of, it is carried out while realizing decoding input and output, to substantially increase the throughput of decoder.The decoder exists
Shortcoming be that first, variable node computing unit, check node calculation unit have only corresponded to one used in the decoder
Kind check matrix structure, code check is single, and for the demand of different business, which cannot be satisfied multi-code length, multi code Rate of Chinese character simultaneously
The decoding demand deposited, secondly, the decoder are not encapsulated into a fixed module to the abstraction function for verifying basic matrix parameter, when
Code length, after code check variation, the transplanting of the decoder is difficult, and third, the partially-parallel architecture which uses solves only list
Code length, solid size rate decoder take into account lower hardware resource consumption while improving its throughput, be not particularly suited for multi-code
Long, multi code Rate of Chinese character decoder.
In the patent document of its application, " variable code length LDPC code encodes or the method and dress of decoding for Huawei Tech Co., Ltd
Set and encoder and decoder " disclose one in (application number CN200510012193.3, application publication number CN1017411396A)
The low density parity check code ldpc decoder of kind variable code length.The decoder is stored using one group of base index matrix memory cell
Base index matrix, and the base index matrix of each code length is extended according to spreading factor, check matrix is obtained, to reach code
Long variable purpose.But the shortcoming that the decoder still has is, although which realizes the variable of code length,
And the variable of code check is not implemented.Moreover, the decoder cannot use a variety of code lengths and various code rate simultaneously in same system.
Invention content
The purpose of the present invention is in view of the deficiency of the prior art, providing, a kind of configurable multi-code is long, multi code Rate of Chinese character
Low density parity check code LDPC (Low Density Parity Check Code) decoder architecture, translating under the structure
Code device can realize a variety of code lengths, the compatibility of various code rate, and multi-code is long, multi code Rate of Chinese character can carry out flexible configuration, and be translated in raising
Lower hardware resource consumption is taken into account while code device throughput, is suitable for completing to a variety of code lengths, the low-density of various code rate
The work decoding of parity check code LDPC.
The decoder includes top-level module, core decoding layer module, the three-decker for verifying layer module；The top-level module
Soft Inform ation unit, storage output Soft Inform ation unit, storage verification and unit, encoded control unit, macrodefinition are inputted including storage
Unit, core decoding unit；The core decoding layer module includes initialization unit, iteration control unit, variable information processing
Unit VPU, check information processing unit CPU, iterative information storage unit, row connected logic units, row logic connection unit, school
Verification certificate member；The verification layer module includes verification core cell, verification and computing unit；
The macrodefinition unit is more with the one-to-one low density parity check code ldpc decoder of code check for storing
A verification basic matrix and multiple standard extension factors, by all verification basic matrixs, spreading factor expands according to different standards
Exhibition, obtains and the one-to-one check matrix of code length；By the school for replacing the low density parity check code ldpc decoder of input
Basic matrix is tested, realizes the configuration of different code checks, is expanded by replacing the standard of low density parity check code ldpc decoder of input
The factor is opened up, realizes the configuration of code length；
The core decoding unit, using partially-parallel architecture, for completing low density parity check code ldpc decoder
Initialization, iterative decoding, verifying work；
The variable information processing unit VPU, the variable information for updating variable node, variable information processing unit
VPU shares the variable information processing unit VPU modules of 15 kinds of input port quantity, and core decoding unit is inputted with macrodefinition unit
Verification basic matrix each row weight on the basis of, choose corresponding variable information processing unit VPU modules, core decoding unit with
On the basis of the maximum number of column of the verification basic matrix of macrodefinition unit input, the sum of variable information processing unit VPU is chosen；
The check information processing unit CPU, the check information for updating check-node, check information processing unit
CPU shares the check information processing unit CPU module of 15 kinds of input port quantity, and core decoding unit is inputted with macrodefinition unit
Verification basic matrix each row weight on the basis of, choose corresponding check information processing unit CPU module, core decoding unit with
On the basis of the maximum number of lines of the verification basic matrix of macrodefinition unit input, the total quantity of check information processing unit CPU is chosen；
The iterative information storage unit, including iterative information memory and offset address generator, the offset address
Generator is used to generate the read/write address of iterative information memory, and offset address generator utilizes the verification of macrodefinition unit output
The location information of basic matrix element, is written according to backward, and the mode sequentially read generates the read/write address of iterative information memory.
The present invention compared with prior art, has the following advantages that：
First, due to the macrodefinition unit of the present invention, can store and the one-to-one low density parity check code of code check
Multiple verification basic matrixs of ldpc decoder, overcome variable node computing unit, school used in decoder in the prior art
It tests node computing unit and has only corresponded to a kind of check matrix structure, the problem of existing single code check so that the present invention can be simultaneously
To the low density parity check code LDPC of various code rate into row decoding.
Second, due to the macrodefinition unit of the present invention, the multiple of low density parity check code ldpc decoder can be stored
The standard extension factor, by all verification basic matrixs, spreading factor is extended according to different standards, is obtained a pair of with code length one
The check matrix answered cannot simultaneously make although overcoming the transformation that code length may be implemented in the prior art in same system
The problem of with a variety of code lengths so that the present invention realizes the simultaneous of a variety of code lengths when to low density parity check code LDPC into row decoding
Hold.
Third can store the multiple of low density parity check code ldpc decoder due to the macrodefinition unit of the present invention
Basic matrix and multiple standard extension factors are verified, the verification of the low density parity check code ldpc decoder by replacing input
Basic matrix realizes the configuration of different code checks, the standard extension of the low density parity check code ldpc decoder by replacing input
The factor realizes the configuration of different code length, overcomes code length in the prior art, difficult problem is transplanted after code check variation so that this
The multi-code of low density parity check code ldpc decoder is long in invention, and multi code Rate of Chinese character can carry out flexible configuration.
4th, since core of the invention decoding unit uses partially-parallel architecture, variable information processing unit VPU, school
Testing information process unit CPU has the module of 15 kinds of input port quantity, and at the big variable information of input port quantitative value
Reason unit VPU modules, check information processing unit CPU module is backward compatible, and the small variable information processing of input port quantitative value is single
First VPU modules, check information processing unit CPU module overcome the decoding for being not directed to multi-code length, multi code Rate of Chinese character in the prior art
The problem of device takes into account lower hardware resource consumption while improving its throughput so that the low-density parity-check in the present invention
It tests yard ldpc decoder and takes into account lower hardware resource consumption while improving its throughput.
Description of the drawings
Fig. 1 is three-layered node composition of the present invention.
Fig. 2 is top-level module structure chart of the present invention.
Fig. 3 is core decoding layer function structure chart of the present invention.
Specific implementation mode
The present invention will be further described below in conjunction with the accompanying drawings.
Referring to Fig.1, to the present invention decoder architecture be further described, the decoder architecture include top-level module,
Core decoding layer module, the three-decker for verifying layer module, the overall structure of the decoder are divided with function, and top-level module is used for
Complete sequential and Row control of the decoder during decoding；Core decoding layer structure is used to complete the core iteration of decoder
Work decoding；Verification layer is used to complete calculating and storage work of the decoder to check information.
With reference to Fig. 2, the top level structure of the present invention is further described, the top-level module includes that storage inputs soft letter
Interest statement member, storage output Soft Inform ation unit, storage verification and unit, encoded control unit, macrodefinition unit, core decoding are single
Member；The decoding process of the decoder is：The control instruction for starting decoding in EMIF mapping signals is sent to by encoded control unit
Storage input Soft Inform ation unit, storage input Soft Inform ation unit delay the serial initial soft information in EMIF mapping signals
It deposits, is then provided in parallel to core decoding unit, various code lengths that core decoding unit is provided using macrodefinition unit, code check
Information is iterated decoding, and after the completion of iterative decoding, encoded control unit sends control instruction and exports Soft Inform ation to storage respectively
Unit and storage verification and unit, storage export the parallel output Soft Inform ation of Soft Inform ation unit caches, then Serial output；Storage
Verification and unit caches verification and information, export after matching sequential.
Macrodefinition unit is for storing and multiple schools of the one-to-one low density parity check code ldpc decoder of code check
Test basic matrix and multiple standard extension factors.
The verification basic matrix and the standard extension factor that macrodefinition unit is stored in conjunction with the embodiment of the present invention do into
One step describes, and the macrodefinition unit of the embodiment realizes 3 kinds of code lengths, the compatibility of 9 kinds of code checks, and three kinds of code checks are respectively 1/2,
3/4、1/3；The corresponding verification basic matrix of wherein 1/2 code check is mx0：
The corresponding verification basic matrix of 3/4 code check is mx1：
The corresponding verification basic matrix of 1/3 code check is mx2：
By above-mentioned 3 verification basic matrix each verify basic matrix, respectively according to 3 different standard extension factors into
Row extension, obtain with one-to-one 9 check matrixes of code length, realize 9 kinds of code checks compatibility, wherein：
The corresponding 3 different standard extension factors of 1st verification basic matrix mx0 are z_faca：
Z_faca=[26 40 90]；
The corresponding 3 different standard extension factors of 2nd verification basic matrix mx1 are z_facb：
Z_facb=[26 53 77]；
The corresponding 3 different standard extension factors of 3rd verification basic matrix mx2 are z_facc：
Z_facc=[22 24 90]；
The 9 kinds of code checks obtained after extension are matrix mx：
By replacing the verification basic matrix of the low density parity check code ldpc decoder of input, matching for different code checks is realized
It sets, the standard extension factor of the low density parity check code ldpc decoder by replacing input realizes the configuration of code length.
Macrodefinition unit verifies basic matrix first with 3 of input and 9 standard extension factor statistics decode core list
The various parameters information of member, specifically includes：Count all verification line numbers of basic matrixs, columns, maximum number of lines, maximum number of column, non-
The maximum number information of the number of 1 element, non-1 element, wherein the line number row=[8 15 16] of three verification basic matrixs, three
The maximum number of lines of the columns col=[16 20 24] of a verification basic matrix, three verification basic matrixs are 16, maximum number of column 24；
The number num=[50 59 83] of non-1 element, three numbers for verifying non-1 element in basic matrixs in three verification basic matrixs
It is 83；Then, macrodefinition unit constructs 4 tables of data using 3 verification basic matrixs of input and 9 standard extension factors, point
It is not row weighted data table vpu_type, row weighted data table cpu_type, row weight statistics table vpu_tn, row weight system
Table cpu_tn is counted, detailed process is：
The row weight information for counting each column in 3 verification basic matrixs respectively, by the row weight information difference descending row of each column
Row take the maximum value of the row weight information of each column in three verification basic matrixs to be stored in row weighted data table vpu_type, can
Obtain vpu_type=[16 16 66333322222222222222 2]；
Row weight information often capable in 3 verification basic matrixs is counted respectively, by the row weight information difference descending row of every row
Row take the maximum value for the row weight information often gone in three verification basic matrixs to be stored in row weighted data table
In vpu_type, cpu_type=[7 77666655555555 5] can be obtained；
The row weight information in row weighted data table vpu_type is counted, the row weighted value not repeated is stored in row
Quantity corresponding to each row weighted value is stored in row weight statistical data by the first row of weight statistics table vpu_tn
The second row of table vpu_tn, can obtain
The row weighted value not repeated storage is expert at by the row weight information in Statistics Bar weighted data table cpu_type
Quantity corresponding to each row weighted value is stored weight statistical data of being expert at by the first row of weight statistics table cpu_tn
The second row of table cpu_tn, can obtain
With reference to Fig. 3, core of the invention decoding layer structure is further described, the core decoding layer module includes
Initialization unit, iteration control unit, variable information processing unit VPU, check information processing unit CPU, iterative information storage
Unit, row connected logic units, row logic connection unit, verification unit；The decoding process of core decoding unit is：It will be from top layer
The initial soft information that storage input Soft Inform ation unit inputs parallel in module is respectively stored in each initial information memory, respectively
A variable information processing unit VPU carries out trial and error decoding using respective initial soft information, and it is single that decoding result is input to verification
Member is verified, if verification and be 0, decoding terminates, and is otherwise input to soft decoding information repeatedly by row logic connection unit
For in information memory cell, check information processing unit CPU is read by row connected logic units in iterative information storage unit
New check information is input to by row connected logic units for updating check information after update by variable information again
Iterative information storage unit, such iteration will finally decode soft letter until decoding correct or reaching maximum iteration
Breath is output in parallel to the storage output Soft Inform ation unit of top-level module, and the storage that verification and information are output to top-level module verifies
And unit.
Core decoding unit uses partially-parallel architecture, for completing the initial of low density parity check code ldpc decoder
Change, iterative decoding, verifying work；
The partially-parallel architecture that core decoding unit uses in the embodiment of the present invention refers to that core decoding unit includes 1
A initialization unit, 1 verification unit, 1 iteration control unit, the variable information processing unit VPU of 24 concurrent workings, 16
The check information processing unit CPU of a concurrent working, the row connected logic units of 24 concurrent workings, the row of 16 concurrent workings
Connected logic units, the iterative information storage unit of 83 concurrent workings, 24,16,83 be respectively verification basic matrix mx0, mx1,
Maximum number of column, maximum number of lines, weight limit number in mx2.
Variable information processing unit VPU is used to update the variable information of variable node, and variable information processing unit VPU is more
Used algorithm is not limited to a certain decoding algorithm based on belief propagation when the variable information of new variables node, presents this
Decoder architecture has good versatility；Variable information processing unit VPU shares the variable information of 15 kinds of input port quantity
There is unique input port quantity, the quantitative value of input port to be arranged from [2,16] for processing unit VPU modules, each module,
Core decoding unit is chosen on the basis of each row weight for the verification basic matrix that macrodefinition unit inputs at corresponding variable information
Reason unit VPU modules can be selected according to row weight statistics table vpu_tn at variable information in an embodiment of the present invention
The type and quantity of unit VPU are managed, i.e.,：The variable information processing unit VPU of 2 16 inputs of selection, 26 variable letters inputted
Cease processing unit VPU, the variable information processing unit VPU of 15 input, the variable information processing unit VPU of 43 inputs, 15
The variable information processing unit VPU of a 2 input；The big variable information processing unit VPU modules of input port quantitative value are simultaneous downwards
Hold the small variable information processing unit VPU modules of input port quantitative value, due to the vpu_tn storages of row weight statistics table
It is the maximum value of row weight in three verification basic matrixs, therefore, if the row weighted value of verification basic matrix is less than maximum column weight
Some input ports, then can be grounded, to realize the multiplexing of variable information processing unit VPU modules by value.For example, verification group moment
The maximum column weight of battle array mx0 is 6, therefore, when using the decoder of 1/2 code check, by the variable information processing unit of 16 inputs
10 pins of VPU modules are grounded, and can be used as the variable information processing unit VPU modules of 6 inputs.
Check information processing unit CPU is used to update the check information of check-node, and check information processing unit CPU is more
Used algorithm is also not necessarily limited to a certain decoding algorithm based on belief propagation when the check information of new check-node；Verification letter
Breath processing unit CPU shares the check information processing unit CPU module of 15 kinds of input port quantity, each module has unique
The quantitative value of input port quantity, input port is arranged from [2,16], the verification that core decoding unit is inputted with macrodefinition unit
On the basis of each row weight of basic matrix, corresponding check information processing unit CPU module is chosen, in an embodiment of the present invention,
It can be according to row weight statistics table cpu_tn come the type and quantity of selection check information process unit CPU, i.e.,：Selection 37
The check information processing unit CPU of input, the check information processing unit CPU of 46 inputs, 95 inputs check informations at
Manage unit CPU；The big backward compatible input port quantitative value of check information processing unit CPU module of input port quantitative value is small
Check information processing unit CPU module, what it is due to the cpu_tn storages of row weight statistics table is row in three verification basic matrixs
The maximum value of weight therefore, can be by some input terminals if the row weighted value of verification basic matrix is less than maximum row weighted value
Mouth ground connection, to realize the multiplexing of check information processing unit CPU module.For example, the maximum row weight of verification basic matrix mx1 is 4,
Therefore, when using the decoder of 3/4 code check, 3 pins of the check information processing unit CPU module of 7 inputs are grounded, it can
Check information processing unit CPU module as 4 inputs.
Iterative information storage unit includes iterative information memory and offset address generator, wherein offset address generates
Device is used to generate the read/write address of iterative information memory, and offset address generator utilizes the verification group moment of macrodefinition unit output
The location information of element, is written according to backward in battle array, and the mode sequentially read generates the read/write address of iterative information memory, will
The benefit that offset address generator is built in iterative information storage unit is any variable information processing unit VPU, verification letter
It is all not necessarily to do the selection of offset address when breath processing unit CPU accesses iterative information storage unit, logical resource can be reduced and disappeared
Consumption.
Phase is chosen in the maximum number of lines for all verification basic matrixs that row connected logic units are used to input from macrodefinition unit
The port sum answered, determines the logic of check information processing unit CPU and iterative information storage unit on the basis of the sum of port
Connection type, the type and quantity used are corresponding with the type and quantity of check information processing unit CPU；The present invention's
It is patrolled using the row of the row connected logic units of 37 ports, the row connected logic units of 46 ports, 95 ports in embodiment
Collect connection unit.
Row logic connection unit chooses phase in the maximum number of column using all verification basic matrixs inputted from macrodefinition unit
The port sum answered, determines the logic of variable information processing unit VPU and iterative information storage unit on the basis of the sum of port
Connection type, the type and quantity used are corresponding with the type and quantity of variable information processing unit VPU；The present invention's
It is patrolled using the row of the row logic connection unit of 2 16 ports, the row logic connection unit of 26 ports, 15 port in embodiment
Volume connection unit, the row logic connection unit of 43 ports, 15 2 ports row logic connection unit.
It includes verification core cell, verification and computing unit to verify layer module.
Verification unit is used to complete the verifying work of decoding, to the Soft Inform ation of each variable information processing unit VPU outputs
It is adjudicated into row decoding, when verifying and being 0, decoding is correct, stops iteration, otherwise continues next iteration decoding, until reaching
Until maximum iteration.
Claims (7)
1. the low density parity check code ldpc decoder of a kind of configurable multi-code length, multi code Rate of Chinese character, which is characterized in that the decoder
Including top-level module, core decoding layer module, the three-decker for verifying layer module；The top-level module includes that storage inputs soft letter
Interest statement member, storage output Soft Inform ation unit, storage verification and unit, encoded control unit, macrodefinition unit, core decoding are single
Member；The core decoding layer module includes initialization unit, iteration control unit, variable information processing unit VPU, check information
Processing unit CPU, iterative information storage unit, row connected logic units, row logic connection unit, verification unit；The verification
Layer module includes verification core cell, verification and computing unit；
The macrodefinition unit, for storing and multiple schools of the one-to-one low density parity check code ldpc decoder of code check
Basic matrix and multiple standard extension factors are tested, by all verification basic matrixs, spreading factor is extended according to different standards,
It obtains and the one-to-one check matrix of code length；By the verification base for replacing the low density parity check code ldpc decoder of input
Matrix realizes the configuration of different code checks, by replace input low density parity check code ldpc decoder standard extension because
Son realizes the configuration of code length；
The core decoding unit, using partially-parallel architecture, for completing the first of low density parity check code ldpc decoder
Beginningization, iterative decoding, verifying work；
The variable information processing unit VPU, the variable information for updating variable node, variable information processing unit VPU are total
There are the variable information processing unit VPU modules of 15 kinds of input port quantity, the school that core decoding unit is inputted with macrodefinition unit
It tests on the basis of each row weight of basic matrix, chooses corresponding variable information processing unit VPU modules, core decoding unit is with macro fixed
On the basis of the maximum number of column of the verification basic matrix of adopted unit input, the sum of variable information processing unit VPU is chosen；
The check information processing unit CPU, the check information for updating check-node, check information processing unit CPU are total
There are the check information processing unit CPU module of 15 kinds of input port quantity, the school that core decoding unit is inputted with macrodefinition unit
It tests on the basis of each row weight of basic matrix, chooses corresponding check information processing unit CPU module, core decoding unit is with macro fixed
On the basis of the maximum number of lines of the verification basic matrix of adopted unit input, the total quantity of check information processing unit CPU is chosen；
The iterative information storage unit, including iterative information memory and offset address generator, the offset address generate
Device is used to generate the read/write address of iterative information memory, and offset address generator utilizes the verification group moment of macrodefinition unit output
The location information of array element element, is written according to backward, and the mode sequentially read generates the read/write address of iterative information memory.
2. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the variable information processing unit VPU shares the variable information processing unit VPU moulds of 15 kinds of input port quantity
Block refers to that there is each module unique input port quantity, the quantitative value of input port to be arranged from [2,16], input port number
The small variable information processing unit VPU of the big backward compatible input port quantitative value of variable information processing unit VPU modules of magnitude
Module, by the part input pin ground connection of the big variable information processing unit VPU of input port quantitative value, to substitute input port
The small variable information processing unit VPU of quantitative value.
3. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the check information processing unit CPU shares the check information processing unit CPU moulds of 15 kinds of input port quantity
Block refers to that there is each module unique input port quantity, the quantitative value of input port to be arranged from [2,16], input port number
The small check information processing unit CPU of the big backward compatible input port quantitative value of check information processing unit CPU module of magnitude
Module, by the part input pin ground connection of the big check information processing unit CPU of input port quantitative value, to substitute input port
The small check information processing unit CPU of quantitative value.
4. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the core decoding unit refers to using partially-parallel architecture, core decoding unit includes that 1 initialization is single
Member, 1 verification unit, 1 iteration control unit, the variable information processing unit VPU of m concurrent working, n concurrent working
Check information processing unit CPU, the row connected logic units of g concurrent working, the row logic connection unit of h concurrent working, k
The iterative information storage unit of a concurrent working, m, n, k are indicated respectively by maximum number of column, the maximum row in all verification basic matrixs
Numerical value determined by number, weight limit number, g is equal with the value of m, and h is equal with the value of n.
5. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the row connected logic units, the maximum number of lines of all verification basic matrixs for being inputted from macrodefinition unit
It is middle to choose corresponding port sum, determine that check information processing unit CPU and iterative information storage are single on the basis of the sum of port
The logical connection mode of member.
6. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the row logic connection unit, utilizes the maximum number of column of all verification basic matrixs inputted from macrodefinition unit
It is middle to choose corresponding port sum, determine that variable information processing unit VPU and iterative information storage are single on the basis of the sum of port
The logical connection mode of member.
7. the low density parity check code ldpc decoder of a kind of configurable multi-code length according to claim 1, multi code Rate of Chinese character,
It is characterized in that, the verification unit, the verifying work for completing decoding export each variable information processing unit VPU
Soft Inform ation adjudicated into row decoding, when verifying and being 0, decoding is correct, stops iteration, otherwise continues next iteration decoding,
Until reaching maximum iteration.
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