CN108432168A

CN108432168A - A kind of method and apparatus demodulated and decode

Info

Publication number: CN108432168A
Application number: CN201680077493.6A
Authority: CN
Inventors: 张昌明; 蔡梦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2016-06-14
Filing date: 2016-06-14
Publication date: 2018-08-21
Anticipated expiration: 2036-06-14
Also published as: CN108432168B; WO2017214860A1

Abstract

The invention discloses a kind of demodulation coding methods and apparatus, are related to modulation and the coding field of mobile communication, including：Symbol sebolic addressing is received, first group of bit in first symbol is demodulated, according to the demodulation result and prior information of first group of bit, obtains the second Soft Inform ation of first group of bit, first group of bit includes the bit for belonging to first code word；And so on, obtain the second Soft Inform ation of first group of bit in N number of symbol, to the second Soft Inform ation of first group of bit in N number of symbol into row decoding, according to decoding result and the second Soft Inform ation, obtain the first external information of first group of bit in N number of symbol, wherein, the first external information of first group of bit can be used for the demodulation of second group of bit, and second group of bit includes the bit for belonging to second code word.In the embodiment of the present invention, the first external information for first demodulating bit can be used for the demodulation of other bits in same symbol, take full advantage of iterative process to obtain performance benefits.

Description

A kind of method and apparatus demodulated and decode

Technical field

The present invention relates to the modulation of mobile communication and coding techniques field, in particular to the method and apparatus of a kind of demodulation and decoding.

Background technique

Coding and modulation are two most basic concepts in the communications field.Coding techniques by introduced on the useful information of transmission it is some can detect identifiable redundancy, after transmission and influence of noise, can use redundancy in receiving end and detected and corrected, recover correct original transmitted information.Substantially, channel coding is to obtain coding gain to increase system bandwidth.Modulation transmits binary bits information MAP at symbol, and the conversion between signal-to-noise ratio (Signal-to-Noise Ratio, SNR) and bandwidth may be implemented.In the system that frequency band is limited, it is capable of increasing the rate of information throughput by improving order of modulation, reaches same effect of the low-order-modulated in broadband system.But, the requirement due to high order modulation to SNR is higher, and information is easier to malfunction in transmission process.

Traditional coding and modulation designs independently of each other, and as the communication technology constantly advances, this mentality of designing does not adapt to the needs of high capacity transmission gradually.In fact, coding and the target of modulation are all efficiently inerrably to realize information transmission, so the two, which is carried out joint, considers that the thinking of design is gradually paid attention to.In this respect, the concept of Trellis-coded modulation (Trellis Coded Modulation, TCM) is just proposed early in nineteen eighty-two, modulation and coding is subjected to combined optimization as a whole.TCM is extended by signal diversifying obtains coding gain, but it cannot make adaptive adjustment when channel condition changes, and fail to be used widely in systems in practice.

The intertexture of TCM is completed based on symbol, and limited diversity order becomes the key reason that performance is restricted under fading channel.It is combined using interleaving technology with coded modulation, i.e., Bit Interleaved Coded Modulation (Bit-Interleaved Coded Modulation, BICM) technology is a kind of effective ways to solve the above problems, can obtain bit error rate under fading channel The promotion of (Bit Error Ratio, BER) performance.

In order to preferably utilize the advantage of Bit Interleave, iteration exchanges information between the demodulation decoding of BICM, form Bit Interleaved Coded Modulation iterative decoding (Bit-Interleaved Coded Modulation with Iterative Decoding, BICM-ID) system further improves system performance.However, in BICM-ID system, since the bit in the same symbol is typically from same code word, and different code words and distinct symbols are each other independent, therefore each bit demodulation information for demodulating of previous code word cannot be used for the demodulation for the latter code word for being not belonging to same symbol, that is, in order to obtain iteration income, BICM-ID can only transmit the demodulating information of bit between different the number of iterations, the demodulating information that bit cannot be updated between same symbol difference bit in time, does not make full use of iterative process to obtain performance benefits.

Summary of the invention

In view of this, the embodiment of the present invention proposes that a kind of method and apparatus demodulated and decode, the demodulating information for solving the bit first demodulated cannot be used for the demodulation of other bits in same symbol, be unable to fully using iterative process come the problem of obtaining performance benefits.

In a first aspect, providing a kind of demodulation coding method, comprising: receive symbol sebolic addressing, the symbol sebolic addressing includes N number of symbol, bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, wherein, N, K and m are positive integer, K > 1；First group of bit in first symbol is demodulated according to the prior information of each bit in first symbol, obtain the first Soft Inform ation of first group of bit in first symbol, according to the prior information of the first Soft Inform ation of first group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of first group of bit in first symbol, wherein, first group of bit includes the bit for belonging to first code word；According to the processing mode of first group of bit in first symbol, second first group of bit into n-th symbol is handled, the second Soft Inform ation of first group of bit in N number of symbol is obtained；Second Soft Inform ation of first group of bit in N number of symbol is decoded, obtain the third Soft Inform ation of first group of bit in N number of symbol, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information of first group of bit in N number of symbol is obtained；According to the prior information of other bits in the first external information of first group of bit in first symbol and first symbol, Second group of bit in first symbol is demodulated, the first Soft Inform ation of second group of bit in first symbol is obtained, wherein second group of bit includes the bit for belonging to second code word.

Method provided in an embodiment of the present invention can allow the demodulating information of the bit first demodulated for the demodulation of other bits in same symbol, and taking full advantage of iterative process can be obtained performance benefits, improve the decoding performance of system.

With reference to first aspect, in the first possible implementation of the first aspect, the method also includes: according to the prior information of the first Soft Inform ation of second group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of second group of bit in first symbol；According to the processing mode of second group of bit in first symbol, second second group of bit into n-th symbol is handled, the second Soft Inform ation of second group of bit in N number of symbol is obtained；Second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained.

The possible implementation of with reference to first aspect the first, in the second possible implementation of the first aspect, the method also includes: according to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, obtain the first external information of second group of bit in N number of symbol；According to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, third group bit in first symbol is demodulated, obtain the first Soft Inform ation of third group bit in first symbol, wherein, the third group bit includes the bit for belonging to third code word.

With reference to first aspect, in a third possible implementation of the first aspect, according to the prior information of the first Soft Inform ation of first group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of first group of bit in first symbol, specifically include: the first Soft Inform ation of first group of bit subtracts the prior information of corresponding bit in first symbol, obtains the second Soft Inform ation of first group of bit in first symbol；According to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, obtain the first external information of first group of bit in N number of symbol, specifically include: the third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtains the first external information of first group of bit in N number of symbol.

With reference to first aspect or the first or second of possible implementation of first aspect, in a fourth possible implementation of the first aspect, in iteration for the first time, the prior information of each bit be each bit be 0 or be 1 probability log-likelihood ratio；In non-iteration for the first time, each bit Prior information is the first external information of the corresponding bit that last iteration obtains.

With reference to first aspect, in the fifth possible implementation of the first aspect, the sum of bit number of L group bit in N number of symbol is the integral multiple of code word size, wherein, L is the positive integer no more than K, guarantees to contain at least one complete code word in the bit decoded.

With reference to first aspect, in the sixth possible implementation of the first aspect, second Soft Inform ation of first group of bit in N number of symbol is decoded, obtain the third Soft Inform ation of first group of bit in N number of symbol, it specifically includes: the second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, obtain the 4th Soft Inform ation of first group of bit in N number of symbol, 4th Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained.

The 6th kind of possible implementation with reference to first aspect, in a seventh possible implementation of the first aspect, it is described according to the third Soft Inform ation of first group of bit in N number of symbol and the second Soft Inform ation of corresponding bit, the first external information for obtaining first group of bit in N number of symbol specifically includes: the third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtain the second external information of first group of bit in N number of symbol, second external information of first group of bit in N number of symbol is interleaved, obtain the first external information of first group of bit in N number of symbol.

With reference to first aspect or the first or second of possible implementation of first aspect, in the 8th kind of possible implementation of first aspect, after the completion of last time iteration, the method also includes: the third Soft Inform ation of the first to K group bit in N number of symbol is made decisions respectively, obtains the road K discriminative information；The road K discriminative information is subjected to parallel-serial conversion, recovers the first bit sequence.

Second aspect provides a kind of code modulating method, comprising: receives the first bit sequence, first bit sequence is handled by serioparallel exchange, obtains the road K bit sequence, wherein K is positive integer；The road K bit sequence is encoded respectively, obtains the road K codeword sequence；It respectively takes at least one bit to be modulated in the codeword sequence of the road K, obtains symbol, the symbol is sent.

In conjunction with second aspect, in the first possible implementation of the second aspect, the road K bit sequence is executed into coding respectively in the sending device, after obtaining the road K codeword sequence, the method also includes: the road K codeword sequence is interleaved respectively, the codeword sequence after the road K interweaves is obtained, the error correcting capability of coding techniques can be preferably played.

In conjunction with the possible implementation of the first of second aspect or second aspect, in a second possible implementation of the second aspect, the bit in the symbol belongs to K different codeword sequences.

The third aspect provides a kind of demodulation coding equipment characterized by comprising receiver, demodulator, first processor, decoder and second processor, wherein

The symbol sebolic addressing is sent to the demodulator for receiving symbol sebolic addressing by the receiver, wherein, the symbol sebolic addressing includes N number of symbol, and the bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, N, K and m are positive integer, K > 1；

The demodulator demodulates first group of bit in first symbol according to the prior information of each bit in first symbol, obtains the first Soft Inform ation of first group of bit in first symbol for receiving the symbol sebolic addressing from the receiver；According to the demodulation mode of first group of bit in first symbol, second first group of bit into n-th symbol is demodulated, obtain the first Soft Inform ation of first group of bit in N number of symbol, by the prior information of first group of bit is sent to the first processor in the first Soft Inform ation and N number of symbol of first group of bit in N number of symbol, first group of bit includes the bit for belonging to first code word；

The first processor, for receiving the prior information of first group of bit in the first Soft Inform ation and N number of symbol of first group of bit in N number of symbol from the demodulator, according to the prior information of the first Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second Soft Inform ation of first group of bit in N number of symbol is obtained, the second Soft Inform ation of first group of bit in N number of symbol is sent to the decoder and the second processor；

The decoder, for receiving the second Soft Inform ation of first group of bit in N number of symbol from the first processor, second Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained, the third Soft Inform ation of first group of bit in N number of symbol is sent to the second processor；

The second processor, for receiving the third Soft Inform ation of first group of bit in N number of symbol from the decoder, the second Soft Inform ation of first group of bit in N number of symbol is received from the first processor, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information of first group of bit in N number of symbol is obtained, the first external information of first group of bit in N number of symbol is sent to the demodulator and the first processor；

The demodulator is also used to receive first group of ratio in N number of symbol from the second processor The first special external information, according to the first external information of first group of bit in first symbol, and in first symbol other bits prior information, second group of bit in first symbol is demodulated, the first Soft Inform ation of second group of bit in first symbol is obtained, second group of bit includes the bit for belonging to second code word.

Equipment provided in an embodiment of the present invention can allow the demodulating information of the bit first demodulated for the demodulation of other bits in same symbol, and taking full advantage of iterative process can be obtained performance benefits, improve the decoding performance of system.

In conjunction with the third aspect, in the first possible implementation of the third aspect, the demodulator, it is also used to the demodulation mode according to second group of bit in first symbol, second second group of bit into n-th symbol is demodulated, the first Soft Inform ation of second group of bit in N number of symbol is obtained, by the prior information of second group of bit is sent to the first processor in the first Soft Inform ation and N number of symbol of second group of bit in N number of symbol；The first processor, it is also used to receive the prior information of second group of bit in the first Soft Inform ation and N number of symbol of second group of bit in N number of symbol from the demodulator, according to the prior information of the first Soft Inform ation of second group of bit in N number of symbol and corresponding bit, the second Soft Inform ation of second group of bit in N number of symbol is obtained, the second Soft Inform ation of second group of bit in N number of symbol is sent to the decoder and the second processor；The decoder, it is also used to receive the second Soft Inform ation of second group of bit in N number of symbol from the first processor, second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained, the third Soft Inform ation of second group of bit in N number of symbol is sent to the second processor.

In conjunction with the possible implementation of the first of the third aspect or the third aspect, in the second possible implementation of the third aspect, the second processor, it is also used to receive the third Soft Inform ation of second group of bit in N number of symbol from the decoder, the second Soft Inform ation of second group of bit in N number of symbol is received from the first processor, according to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, obtain the first external information of second group of bit in N number of symbol, first external information of second group of bit in N number of symbol is sent to the demodulator；The demodulator, it is also used to receive the first external information of second group of bit in N number of symbol from the second processor, according to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, the third group bit in first symbol is solved It adjusts, obtains the first Soft Inform ation of third group bit in first symbol, wherein the third group bit includes the bit for belonging to third code word.

In conjunction with the third aspect, in the third possible implementation of the third aspect, the first processor obtains the second Soft Inform ation of first group of bit in first symbol specifically for allowing the first Soft Inform ation of first group of bit in first symbol to subtract the prior information of corresponding bit；The second processor obtains the first external information of first group of bit in N number of symbol specifically for allowing the third Soft Inform ation of first group of bit in N number of symbol to subtract the second Soft Inform ation of corresponding bit.

In conjunction with the first or second of possible implementation of the third aspect or the third aspect, in the fourth possible implementation of the third aspect, in iteration for the first time, the prior information of each bit be each bit be 0 or be 1 probability log-likelihood ratio；In non-iteration for the first time, the prior information of each bit is the first external information of the corresponding bit that last iteration obtains.

In conjunction with the third aspect, in the 5th kind of possible implementation of the third aspect, the sum of bit number of L group bit in N number of symbol is the integral multiple of code word size, wherein, L is the positive integer no more than K, guarantees to contain at least one complete code word in the bit decoded.

In conjunction with the third aspect, in the 6th kind of possible implementation of the third aspect, the equipment further include: deinterleaver, for receiving the second Soft Inform ation of first group of bit in N number of symbol from the first processor, second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, the 4th Soft Inform ation of first group of bit in N number of symbol is obtained, the 4th Soft Inform ation of first group of bit in N number of symbol is sent to the decoder and the second processor；The decoder is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from the deinterleaver, decodes to the 4th Soft Inform ation of first group of bit in N number of symbol, obtains the third Soft Inform ation of first group of bit in N number of symbol；The second processor, it is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from the deinterleaver, according to the 4th Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second external information of first group of bit in N number of symbol is obtained.

In conjunction with the 6th kind of possible implementation of the third aspect, in the 7th kind of possible implementation of the third aspect, the equipment further include: interleaver, for receiving the second external information of first group of bit in N number of symbol from the second processor, second external information of first group of bit in N number of symbol is interleaved, the first external information of first group of bit in N number of symbol is obtained.

In conjunction with the first or second of possible implementation of the third aspect or the third aspect, in the 8th kind of possible implementation of the third aspect, the equipment further include: decision device and parallel-to-serial converter,

The decision device, for after the completion of last time iteration, from the decoder receive in N number of symbol first to K group bit third Soft Inform ation, in N number of symbol first to K group bit third Soft Inform ation is made decisions respectively, the road K discriminative information is obtained, the road K discriminative information is sent to the parallel-to-serial converter；The parallel-to-serial converter carries out parallel-serial conversion processing to the road K discriminative information, recovers the first bit sequence for receiving the road K discriminative information from the decision device.

Fourth aspect provides a kind of coded modulation equipment, it is characterised in that, it include: deserializer, encoder, modulator and transmitter, wherein, the deserializer carries out serioparallel exchange to first bit sequence for receiving the first bit sequence, obtain the road K bit sequence, the road K bit sequence is sent to the encoder, wherein K is positive integer；The encoder encodes the road K bit sequence respectively, obtains the road K codeword sequence, the road K codeword sequence is sent to the modulator for receiving the road K bit sequence from the deserializer；The modulator takes at least one bit to be modulated, obtains symbol, the symbol is sent to transmitter for receiving the road K codeword sequence from the encoder in every road codeword sequence；The transmitter sends the symbol for receiving the symbol from the modulator.

In conjunction with fourth aspect, in the first possible implementation of the fourth aspect, the equipment further include: interleaver, for receiving the road K codeword sequence from the encoder, the road K codeword sequence is interleaved respectively, the codeword sequence after the road K interweaves is obtained, the codeword sequence after the road K is interweaved is sent to the modulator；The modulator is also used to receive the codeword sequence after the road K interweaves from the interleaver, takes at least one bit to be modulated in the codeword sequence after every road interweaves, obtains symbol.

In conjunction with the possible implementation of the first of fourth aspect or fourth aspect, in the first possible implementation of the fourth aspect, the bit in the symbol belongs to K different codeword sequences.

5th aspect, a kind of modulation demodulation system is provided, it include: the demodulation coding equipment as described in the above-mentioned third aspect perhaps any one optional way of the third aspect and the coded modulation equipment as described in any one optional way of above-mentioned fourth aspect or fourth aspect.

Method provided in an embodiment of the present invention can allow the demodulating information of the bit first demodulated for same The demodulation of other bits in symbol, taking full advantage of iterative process can be obtained performance benefits, improve the decoding performance of system.

Detailed description of the invention

In order to thoroughly understand the present invention, referring now to the explanation briefly below described in conjunction with the drawings and specific embodiments, same reference numerals therein indicate same section.

Fig. 1 is the structure chart of BICM-ID system；

Fig. 2 is that the demodulation of BICM-ID system single iteration decodes procedure chart；

Fig. 3 is the method flow diagram of an embodiment of the present invention；

Fig. 4 is the method flow diagram of another embodiment of the present invention；

Fig. 5 is that the demodulation of another embodiment single iteration of the present invention decodes procedure chart；

Fig. 6 is the BER performance comparison figure of another embodiment of the present invention and traditional Gray code mapping and BICM-ID scheme；

Fig. 7 is the structure drawing of device of an embodiment of the present invention；

Fig. 8 is the structure drawing of device of another embodiment of the present invention；

Fig. 9 is the structure drawing of device of another embodiment of the present invention.

Specific embodiment

First it should be understood that any number of technology can be used to implement for disclosed system and or method although the illustrative embodiment of one or more embodiments is provided below, no matter the technology is currently known or existing.The present invention should in no way be limited to illustrative embodiment described below, attached drawing and technology, including exemplary design and embodiment illustrated and described herein, but can modify in the scope of the appended claims and the full breadth of its equivalent.

As two most basic technologies in the communications field, target is all efficiently inerrably to realize information transmission for coding and modulation, in order to adapt to the development of the communication technology, meets the needs of high capacity transmission, needs the two carrying out co-design.Wherein, coding techniques can detecte and correct single error bit or not too long of incorrect bit string, longer incorrect bit string can not be corrected, and in this Rayleigh channel of land mobile, bit error is often bunchiness generation, this is because long-term deep fade valley point influences whether successive a string of bit, it is therefore desirable to use interleaving technology.

Interleaving technology can allow the subsequent bits in an information to be transmitted in non-successive mode, even if bunchiness mistake occurs in transmission process, when receiving end reverts to the message of subsequent bits string, also the very short incorrect bit string of single error bit or length is reformed into, the error correction possessed by coding techniques corrects mistake again, can recover former message.By the interleaving technology, coding techniques and modulation technique combine the BICM technology to be formed, and have many advantages, such as that the availability of frequency spectrum is high, configuration flexibility is strong, implementation complexity is low and decoding performance is excellent, are used widely.

In order to further increase decoding performance, information iteration can be introduced in BICM system, the BICM system for introducing information iteration is BICM-ID system, and structure is as shown in Figure 1.In BICM-ID system, since the bit in the same symbol is typically from same code word, and different code words and distinct symbols are independent each other, therefore each bit information for demodulating of previous code word cannot be used for the demodulation for the latter code word for being not belonging to same symbol.

Specifically, assuming that the code word size after the bit sequence coding that information source is sent is 16, a symbol includes 4 bits, and an iteration handles 4 code words, and the demodulation decoding process of the BICM-ID scheme single iteration is as shown in Figure 2.As can be seen from the figure, be entirely for single iteration, between 4 code words it is independent, the demodulating information of the bit first demodulated cannot be used for the demodulation of other bits of same symbol in time, demodulating information can only be transmitted between different the number of iterations, and iterative process is not made full use of to obtain performance benefits.

In view of this, the embodiment of the present invention provides a kind of code modulating method, as shown in figure 3, this method may include:

301, the first bit sequence is received, the first bit sequence is handled by serioparallel exchange, obtains the road K bit sequence, wherein K is positive integer.

302, the road K bit sequence is encoded respectively, obtains the road K codeword sequence.

Wherein, coding is to add some to can detect identifiable redundancy on per the bit sequence that transmits all the way, for being detected and being corrected using redundancy in receiving end, coding mode, which can according to need, to be adjusted, it can be convolutional code, low density parity check code (Low Density Parity Check Code, LDPC), Turbo code etc., it is not limited in the embodiment of the present invention.

Optionally, it as another embodiment, is encoded respectively to the road K bit sequence, after obtaining the road K codeword sequence, the method also includes: the road K codeword sequence is interleaved respectively, obtains the codeword sequence after the road K interweaves.

Wherein, interleaving technology is to upset the sequence of codeword sequence, the subsequent bits of codeword sequence are allowed to transmit in non-successive mode, even if the bit-errors of bunchiness occur in transmission process, after receiving end deinterleaves, also it will become single or very short length mistake, the error correction that coding techniques can be allowed to have preferably plays a role.

303, it respectively takes at least one bit to be modulated in the codeword sequence of the road K, obtains symbol, symbol is sent.

Wherein, the embodiment of the present invention can guarantee bit that the symbol is included from K different codeword sequences, preferably, a bit is respectively taken to be modulated in the codeword sequence of the road K, symbol is obtained, each bit both is from different code words in the symbol, when each bit demodulates in the symbol, the newest demodulating information that may be by each bit in the symbol is conducive to receiving end and makes full use of iterative process to obtain performance boost.

Specifically, modulation system can choose as phase-shift keying (PSK) (Phase Shift Keying, PSK), amplitude shift keying (Amplitude Shift Keying,) and quadrature amplitude modulation (Quadrature Amplitude Modulation ASK, QAM) etc., it is not limited in the embodiment of the present invention.

The embodiment of the present invention provides a kind of demodulation coding method, as shown in figure 4, this method may include:

401, symbol sebolic addressing is received, which includes N number of symbol, and the bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, wherein N, K and m are positive integer, K > 1.

402, first group of bit in first symbol is demodulated according to the prior information of each bit in first symbol, obtain the first Soft Inform ation of first group of bit in first symbol, according to the prior information of the first Soft Inform ation of first group of bit in first symbol and corresponding bit, the second Soft Inform ation of first group of bit in first symbol is obtained.

Wherein, first group of bit includes the bit for belonging to first code word, the prior information of each bit will be according to each leisure { 0,1 } distribution in determines, it can be the log-likelihood ratio (Logarithmic-Likelihood Ratio, LLR) for the probability that each bit is 0 or is 1, preferably, it can be assumed each bit in { 0,1 } medium general distribution.

Specifically, the Soft Inform ation of bit can generally also be expressed as log-likelihood ratio, demodulating algorithm may be selected to be maximum a posteriori probability (Maximum a Posteriori, MAP), log-domain maximum a posteriori probability (Logarithmic MAP, LOG-MAP) or maximum value log-domain maximum a posteriori probability (Maximum-LOG-MAP, MAX-LOG-MAP) etc., it is not limited in the embodiment of the present invention.

Optionally, the mode of the second Soft Inform ation of first group of bit in first symbol is obtained specifically, the first Soft Inform ation of first group of bit subtracts the prior information of corresponding bit in first symbol, obtains the second Soft Inform ation of first group of bit in first symbol.

403, according to the processing mode of first group of bit in first symbol, second first group of bit into n-th symbol is handled, the second Soft Inform ation of first group of bit in N number of symbol is obtained.

Wherein, in N number of symbol the sum of bit number of first group of bit be code word size integral multiple.

404, second Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, obtains the first external information of first group of bit in N number of symbol.

Optionally, the mode of the first external information of first group of bit in N number of symbol is obtained specifically: the third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtains the first external information of first group of bit in N number of symbol.

405, according to the prior information of other bits in the first external information of first group of bit in first symbol and first symbol, second group of bit in first symbol is demodulated, the first Soft Inform ation of second group of bit in first symbol is obtained.

Wherein, second group of bit includes the bit for belonging to second code word.

Optionally, as another embodiment, the method also includes: according to the prior information of the first Soft Inform ation of second group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of second group of bit in first symbol；According to the processing mode of second group of bit in first symbol, second second group of bit into n-th symbol is handled, the second Soft Inform ation of second group of bit in N number of symbol is obtained；Second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained.

Optionally, the method also includes: according to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, obtain the first external information of second group of bit in N number of symbol；According to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, third group bit in first symbol is demodulated, the first Soft Inform ation of third group bit in first symbol is obtained, third group bit includes the bit for belonging to third code word.

Wherein, assuming that when being demodulated to H group, it will be according to the first external information of H-1 group bit in first symbol, and in first symbol other bits prior information, H group bit in first symbol is demodulated, the first Soft Inform ation of H group bit in first symbol is obtained, H group bit includes the bit for belonging to third code word, subsequent operation was described in embodiment before, and details are not described herein.

The embodiment of the present invention can allow the demodulating information of the one group of bit first demodulated for the demodulation of other bits in same symbol, and taking full advantage of iterative process can be obtained performance benefits, improve the decoding performance of system.Preferably, the bit number that each group of bit is included is 1.

Specifically, assuming that the code word size after bit sequence coding is 16, a symbol includes 4 bits, and an iteration handles 4 code words, and the demodulation decoding process of single iteration of the embodiment of the present invention is as shown in Figure 5.As can be seen from the figure, four bits of same symbol both are from different code words, first group of bit is all first bit of each symbol, first bit of 16 symbols constitutes first code word, after first code word demodulates, the first external information that will be updated, since first bit in first code word and second code word belongs to the same symbol, therefore the first external information of first bit can be used for the demodulation of first bit in second code word in first code word, similarly, the first external information of the 2nd to the 16th bit also may be respectively used in the demodulation of the 2nd to the 16th bit in second code word in first code word, further increase the accuracy of decoding.

Optionally, the sum of bit number of L group bit in N number of symbol is the integral multiple of code word size, wherein L is the positive integer no more than K.

Wherein, decoding is the integral multiple that the number of bits parsed to complete code, therefore decoded together is necessary for code word size, that is to say, that, the number of bits of any group of bit is necessary for the integral multiple of code word size in N number of symbol, at least equal to the length of a code word.

Optionally, as another embodiment, in iteration for the first time, the prior information of each bit be each bit be 0 or be 1 probability log-likelihood ratio；In non-iteration for the first time, the prior information of each bit is the first external information of the corresponding bit that last iteration obtains.

Specifically, by taking the demodulation of the 4th group of bit of second of iteration as an example, assuming that K is not less than 4, due in second of iterative process, first to the demodulated completion of third group bit, had updated first to third group bit the first external information, and the 4th is not demodulated also to K group bit, also without updating first external information, therefore the 4th uses first time iteration to the prior information of K group bit 4th to K group bit the first external information.

Optionally, as another embodiment, second Soft Inform ation of first group of bit in N number of symbol is decoded, obtain the third Soft Inform ation of first group of bit in N number of symbol, it specifically includes: the second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, the 4th Soft Inform ation of first group of bit in N number of symbol is obtained, the 4th Soft Inform ation of first group of bit in N number of symbol is decoded, obtains the third Soft Inform ation of first group of bit in N number of symbol.

Correspondingly, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information for obtaining first group of bit in N number of symbol specifically includes: the third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtain the second external information of first group of bit in N number of symbol, second external information of first group of bit in N number of symbol is interleaved, the first external information of first group of bit in N number of symbol is obtained.

Optionally, as another embodiment, after the completion of last time iteration, the method also includes: the third Soft Inform ation of the first to K group bit in N number of symbol is made decisions respectively, obtains the road K discriminative information；The road the K discriminative information is subjected to parallel-serial conversion, recovers the first bit sequence.

Wherein, the condition of iteration ends can be to reach the iteration convergence condition etc. that specified the number of iterations or satisfaction is set, and it is not limited in the embodiment of the present invention.

Fig. 6 shows the BER performance comparison of the embodiment of the present invention and traditional Gray code mapping and existing BICM-ID scheme, and essential condition is as follows: the LDPC code in coding mode selection IEEE 802.11ad standard, and the code length after coding is 672, code rate 13/16；Modulation system selects 16QAM, K=4, and each circuit-switched data selects a bit；Constellation point mapping mode under BICM-ID and the present invention program is selected as anti-Gray code；Demodulating algorithm selects MAX-LOG-MAP；Interleave depth is 256704, i.e. 382 LDPC code words；Maximum number of iterations is selected as 20；The channel circumstance of consideration is additive white Gaussian noise (Additive White Gaussian Noise, AWGN).

It can be found that existing BICM-ID and the BER performance curve of the embodiment of the present invention are more precipitous relative to classical Gray code map modulation from figure, BER=10E-6 is dropped to from BER=10E-2 Bit signal-to-noise ratio (the energy per bit to noise power spectral density ratio in the process, Eb/N0) only increase within 0.1dB, and the difference that Gray code maps lower Eb/N0 reaches 2.2dB or so, when Eb/N0 is larger, BICM-ID and the present invention program are mapped relative to Gray code has performance gain, when BER is 10E-6, relative to Gray code mapping, the present invention can obtain about 2.0dB performance gain.Moreover, since invention introduces grouping mechanisms, different group bits can transmit the information as demodulation in time in same an iteration, relative to existing BICM-ID technology, performance gain with about 0.5dB when BER is 10E-6 of the embodiment of the present invention.

Method provided in an embodiment of the present invention, grouping mechanism is introduced on the basis of BICM-ID, in an iterative process, the demodulation coding result of each group of bit can be timely feedbacked to other group of bit for demodulating, performance benefits brought by iteration are taken full advantage of, the decoding performance of system is improved.

The embodiment of the present invention provides a kind of equipment for coded modulation, as shown in fig. 7, the equipment may include: deserializer 701, encoder 702, modulator 703 and transmitter 704, wherein

Deserializer 701 carries out serioparallel exchange to first bit sequence, obtains the road K bit sequence, the road K bit sequence is sent to encoder 702 for receiving the first bit sequence.

Encoder 702 encodes the road K bit sequence respectively, obtains the road K codeword sequence, the road K codeword sequence is sent to modulator 703 for receiving the road K bit sequence from deserializer 701；

Wherein, coding is to add some to can detect identifiable redundancy on per the bit sequence that transmits all the way, for being detected and being corrected using redundancy in receiving end, coding mode, which can according to need, to be adjusted, it can be convolutional code, LDPC code, Turbo code etc., it is not limited in the embodiment of the present invention.

Modulator 703 takes at least one bit to be modulated, obtains symbol, which is sent to transmitter 704 for receiving the road K codeword sequence from encoder 702 in every road codeword sequence.

Specifically, modulation system can choose as PSK, ASK and QAM etc., it is not limited in the embodiment of the present invention.

Optionally, as another embodiment, the equipment further include: interleaver 705, for receiving the road K codeword sequence from encoder 702, the road K codeword sequence is interleaved respectively, obtains the codeword sequence after the road K interweaves, the codeword sequence after the road K is interweaved is sent to modulator 703；Modulator 703 is also used to receive the codeword sequence after the road K interweaves from interleaver 705, after every road interweaves Codeword sequence in respectively take at least one bit to be modulated, obtain symbol.

Transmitter 704 sends the symbol for receiving symbol from modulator 703.

The embodiment of the present invention provides a kind of equipment for demodulation coding, as shown in figure 8, receiver 801, demodulator 802, first processor 803, decoder 804 and second processor 805,

Symbol sebolic addressing is sent to demodulator 802 for receiving symbol sebolic addressing by receiver 801.

Wherein, which includes N number of symbol, and the bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, and N, K and m are positive integer, K > 1.

Demodulator 802 demodulates first group of bit in first symbol according to the prior information of each bit in first symbol, obtains the first Soft Inform ation of first group of bit in first symbol for receiving the symbol sebolic addressing from receiver 801；According to the demodulation mode of first group of bit in first symbol, second first group of bit into n-th symbol is demodulated, the first Soft Inform ation of first group of bit in N number of symbol is obtained, by the prior information of first group of bit is sent to first processor 803 in the first Soft Inform ation and N number of symbol of first group of bit in N number of symbol.

Wherein, first group of bit includes the bit for belonging to first code word；The prior information of each bit will be determined according to the distribution in each comfortable { 0,1 }, can be the LLR for the probability that each bit is 0 or is 1, it is preferable that can be assumed each bit in { 0,1 } medium general distribution.

Optionally, in N number of symbol the sum of bit number of first group of bit be code word size integral multiple.

Specifically, the Soft Inform ation of bit may generally be expressed as log-likelihood ratio, demodulating algorithm may be selected to be MAP, LOG-MAP or MAX-LOG-MAP etc., and it is not limited in the embodiment of the present invention.

First processor 803, for receiving of first group of bit in N number of symbol from demodulator 802 The prior information of first group of bit in one Soft Inform ation and N number of symbol, according to the prior information of the first Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second Soft Inform ation of first group of bit in N number of symbol is obtained, the second Soft Inform ation of first group of bit in N number of symbol is sent to decoder 804 and second processor 805.

Optionally, as another embodiment, first processor 803 is specifically used for, and allows the first Soft Inform ation of first group of bit in first symbol to subtract the prior information of corresponding bit, obtains the second Soft Inform ation of first group of bit in first symbol.

Decoder 804, for receiving the second Soft Inform ation of first group of bit in N number of symbol from first processor 803, second Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained, the third Soft Inform ation of first group of bit in N number of symbol is sent to second processor 805.

Second processor 805, for receiving the third Soft Inform ation of first group of bit in N number of symbol from decoder, the second Soft Inform ation of first group of bit in N number of symbol is received from first processor 803, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information of first group of bit in N number of symbol is obtained, the first external information of first group of bit in N number of symbol is sent to demodulator 802 and first processor 803.

Optionally, second processor 805 obtain the first external information of first group of bit in N number of symbol specifically for allowing the third Soft Inform ation of first group of bit in N number of symbol to subtract the second Soft Inform ation of corresponding bit.

Demodulator 802, it is also used to receive the first external information of first group of bit in N number of symbol from second processor 805, according to the first external information of first group of bit in first symbol, and in first symbol other bits prior information, second group of bit in first symbol is demodulated, obtain the first Soft Inform ation of second group of bit in first symbol, wherein second group of bit includes the bit for belonging to second code word.

Optionally, as another embodiment, demodulator 802, it is also used to the demodulation mode according to second group of bit in first symbol, second second group of bit into n-th symbol is demodulated, the first Soft Inform ation of second group of bit in N number of symbol is obtained, by the prior information of second group of bit is sent to first processor 803 in the first Soft Inform ation and N number of symbol of second group of bit in N number of symbol；

First processor 803 is also used to receive in N number of symbol second group of bit from demodulator 802 The prior information of second group of bit in first Soft Inform ation and N number of symbol, according to the prior information of the first Soft Inform ation of second group of bit in N number of symbol and corresponding bit, the second Soft Inform ation of second group of bit in N number of symbol is obtained, the second Soft Inform ation of second group of bit in N number of symbol is sent to decoder 804 and second processor 805；

Decoder 804, it is also used to receive the second Soft Inform ation of second group of bit in N number of symbol from first processor 803, second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained, the third Soft Inform ation of second group of bit in N number of symbol is sent to second processor 805.

Wherein, second processor 805, it is also used to receive the third Soft Inform ation of second group of bit in N number of symbol from decoder 804, the second Soft Inform ation of second group of bit in N number of symbol is received from first processor 803, according to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, the first external information of second group of bit in N number of symbol is obtained, the first external information of second group of bit in N number of symbol is sent to demodulator 802 and first processor 803；

Demodulator 802, it is also used to receive the first external information of second group of bit in N number of symbol from second processor, according to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, third group bit in first symbol is demodulated, the first Soft Inform ation of third group bit in first symbol is obtained.

Wherein, third group bit includes the bit for belonging to third code word.

Specifically, by taking first group of bit as an example, in non-iteration for the first time, first processor 803, it is also used to receive the first external information of first group of bit in N number of symbol from second processor 804, believes according to outside first of corresponding bit in the first Soft Inform ation of first group of bit in N number of symbol and last iteration Breath, obtains the second Soft Inform ation of first group of bit in N number of symbol.

Optionally, as another embodiment, the equipment further include: deinterleaver 806, for receiving the second Soft Inform ation of first group of bit in N number of symbol from first processor 803, second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, the 4th Soft Inform ation of first group of bit in N number of symbol is obtained, the 4th Soft Inform ation of first group of bit in N number of symbol is sent to decoder 804 and second processor 805；Decoder 804 is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from deinterleaver 806, decodes to the 4th Soft Inform ation of first group of bit in N number of symbol, obtains the third Soft Inform ation of first group of bit in N number of symbol；Second processor 805, it is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from deinterleaver 806, according to the 4th Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second external information of first group of bit in N number of symbol is obtained.

Correspondingly, the equipment further include: interleaver 807, for receiving the second external information of first group of bit in N number of symbol from second processor 805, the second external information of first group of bit in N number of symbol is interleaved, obtains the first external information of first group of bit in N number of symbol.

Optionally, as another embodiment, the equipment further include: decision device 808 and parallel-to-serial converter 809,

Decision device 808, for after the completion of last time iteration, from decoder 804 receive in N number of symbol first to K group bit third Soft Inform ation, in N number of symbol first to K group bit third Soft Inform ation is made decisions respectively, the road K discriminative information is obtained, the road K discriminative information is sent to parallel-to-serial converter 809；

Parallel-to-serial converter 809 carries out parallel-serial conversion processing to the road K discriminative information, recovers the first bit sequence for receiving the road K discriminative information from decision device 808.

It should be noted that the demodulation coding equipment of demodulation coding equipment provided in an embodiment of the present invention and BICM-ID system is all bitwise to be demodulated, therefore be consistent in calculation amount.

Optionally, as another embodiment, the quantity of the decoder, deinterleaver and interleaver distinguishes only one.Fig. 9 shows the demodulation coding equipment schematic diagram of the embodiment of the present invention, since in the demodulation coding equipment of the embodiment of the present invention, each effector is sequentially execution, and decoder 804, Decision device 808, the function that the devices such as interleaver 807 complete every group of bit is the same, therefore every sample device only needs the function that demodulation coding can be realized, it only need to be after iteration completion, decision device 808 is unified again by the court verdict transmitted in parallel of each group bit to parallel-to-serial converter 809, is all serial connection between other devices, therefore, compared with BICM-ID system, the embodiment of the present invention not will increase additional hardware resource cost.

The embodiment of the present invention provides a kind of modulation demodulation system, comprising: the demodulation coding equipment as described in any one of claim 13-21 and the coded modulation equipment as described in any one of claim 22-24.

System provided in an embodiment of the present invention can allow the demodulating information of the one group of bit first demodulated for the demodulation of other bits in same symbol, and taking full advantage of iterative process can be obtained performance benefits, improve the decoding performance of system.

It should be understood that " one embodiment " or " embodiment " that specification is mentioned in the whole text means that a particular feature, structure, or characteristic related with embodiment is included at least one embodiment of the present invention.Therefore, not necessarily refer to identical embodiment in " in one embodiment " or " in one embodiment " that the whole instruction occurs everywhere.In addition, these specific features, structure or characteristic can combine in any suitable manner in one or more embodiments.In various embodiments of the present invention, the serial number size of above-mentioned each process is not meant that the order of the execution order, and the execution sequence of each process should be determined by its function and internal logic, and the implementation process of the embodiments of the invention shall not be constituted with any limitation.

Those of ordinary skill in the art may be aware that, device and algorithm steps described in conjunction with the examples disclosed in the embodiments of the present disclosure, it can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the interchangeability of hardware and software, each exemplary composition and step are generally described according to function in the above description.These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Professional technician can use different methods to achieve the described function each specific application, but such implementation should not be considered as beyond the scope of the present invention.

In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be realized in other way.For example, apparatus embodiments described above are merely indicative, for example, the division of the device, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple devices or component may be combined or can be integrated into separately One system, or some features can be ignored or not executed.In addition, shown or discussed mutual coupling, direct-coupling or communication connection can be through some interfaces, the indirect coupling or communication connection of equipment or device, be also possible to electricity, mechanical or other forms connections.

In short, being not intended to limit the scope of the present invention the foregoing is merely the preferred embodiment of technical solution of the present invention.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.

Claims

A kind of demodulation coding method characterized by comprising

Symbol sebolic addressing is received, the symbol sebolic addressing includes N number of symbol, and the bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, wherein N, K and m are positive integer, K > 1；

First group of bit in first symbol is demodulated according to the prior information of each bit in first symbol, obtain the first Soft Inform ation of first group of bit in first symbol, according to the prior information of the first Soft Inform ation of first group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of first group of bit in first symbol, wherein, first group of bit includes the bit for belonging to first code word；

According to the processing mode of first group of bit in first symbol, second first group of bit into n-th symbol is handled, the second Soft Inform ation of first group of bit in N number of symbol is obtained；

Second Soft Inform ation of first group of bit in N number of symbol is decoded, obtain the third Soft Inform ation of first group of bit in N number of symbol, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information of first group of bit in N number of symbol is obtained；

According to the first external information of first group of bit in first symbol, and in first symbol other bits prior information, second group of bit in first symbol is demodulated, obtain the first Soft Inform ation of second group of bit in first symbol, wherein, second group of bit includes the bit for belonging to second code word.
The method according to claim 1, wherein the method also includes:

According to the prior information of the first Soft Inform ation of second group of bit in first symbol and corresponding bit, the second Soft Inform ation of second group of bit in first symbol is obtained；

According to the processing mode of second group of bit in first symbol, second second group of bit into n-th symbol is handled, the second Soft Inform ation of second group of bit in N number of symbol is obtained；

Second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained.
According to the method described in claim 2, it is characterized in that, the method also includes:

According to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, the first external information of second group of bit in N number of symbol is obtained；

According to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, third group bit in first symbol is demodulated, obtain the first Soft Inform ation of third group bit in first symbol, wherein, the third group bit includes the bit for belonging to third code word.
The method according to claim 1, wherein

According to the prior information of the first Soft Inform ation of first group of bit in first symbol and corresponding bit, obtain the second Soft Inform ation of first group of bit in first symbol, specifically include: the first Soft Inform ation of first group of bit subtracts the prior information of corresponding bit in first symbol, obtains the second Soft Inform ation of first group of bit in first symbol；

According to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, obtain the first external information of first group of bit in N number of symbol, specifically include: the third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtains the first external information of first group of bit in N number of symbol.
Method according to any one of claims 1 to 3, which is characterized in that

In iteration for the first time, the prior information of each bit indicate each bit be 0 or be 1 probability log-likelihood ratio；

In non-iteration for the first time, the prior information of each bit is the first external information of the corresponding bit that last iteration obtains.
The method according to claim 1, wherein the sum of the bit number of L group bit in N number of symbol is the integral multiple of code word size, wherein L is the positive integer no more than K.
The method according to claim 1, wherein being decoded to the second Soft Inform ation of first group of bit in N number of symbol, the third Soft Inform ation of first group of bit in N number of symbol is obtained, is specifically included:

Second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, obtain the 4th Soft Inform ation of first group of bit in N number of symbol, 4th Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained.
The method according to the description of claim 7 is characterized in that described specifically include according to the third Soft Inform ation of first group of bit in N number of symbol with the second Soft Inform ation of corresponding bit, the first external information for obtaining first group of bit in N number of symbol:

The third Soft Inform ation of first group of bit subtracts the second Soft Inform ation of corresponding bit in N number of symbol, obtain the second external information of first group of bit in N number of symbol, second external information of first group of bit in N number of symbol is interleaved, the first external information of first group of bit in N number of symbol is obtained.
Method according to any one of claims 1 to 3, which is characterized in that after the completion of last time iteration, the method also includes:

The third Soft Inform ation of the first to K group bit in N number of symbol is made decisions respectively, obtains the road K discriminative information；

The road K discriminative information is subjected to parallel-serial conversion, recovers the first bit sequence.
A kind of code modulating method characterized by comprising

The first bit sequence is received, first bit sequence is handled by serioparallel exchange, obtains the road K bit sequence, wherein K is positive integer；

The road K bit sequence is encoded respectively, obtains the road K codeword sequence；

It respectively takes at least one bit to be modulated in the codeword sequence of the road K, obtains symbol, the symbol is sent.
According to the method described in claim 10, it is characterized in that, encoded respectively to the road K bit sequence, after obtaining the road K codeword sequence, the method also includes:

The road K codeword sequence is interleaved respectively, obtains the codeword sequence after the road K interweaves.
Method described in 0 or 11 according to claim 1, which is characterized in that the bit in the symbol belongs to K different codeword sequences.
A kind of demodulation coding equipment characterized by comprising receiver, demodulator, first processor, decoder and second processor, wherein

The symbol sebolic addressing is sent to the demodulator for receiving symbol sebolic addressing by the receiver, wherein, the symbol sebolic addressing includes N number of symbol, and the bit in each symbol belongs to K code word, and m-th of bit in each symbol belongs to the same code word, N, K and m are positive integer, K > 1；

The demodulator demodulates first group of bit in first symbol according to the prior information of each bit in first symbol, obtains the first Soft Inform ation of first group of bit in first symbol for receiving the symbol sebolic addressing from the receiver；According to the demodulation mode of first group of bit in first symbol, second first group of bit into n-th symbol is demodulated, the first Soft Inform ation of first group of bit in N number of symbol is obtained, by the first Soft Inform ation and N number of symbol of first group of bit in N number of symbol The prior information of first group of bit is sent to the first processor in number, and first group of bit includes the bit for belonging to first code word；

The first processor, for receiving the prior information of first group of bit in the first Soft Inform ation and N number of symbol of first group of bit in N number of symbol from the demodulator, according to the prior information of the first Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second Soft Inform ation of first group of bit in N number of symbol is obtained, the second Soft Inform ation of first group of bit in N number of symbol is sent to the decoder and the second processor；

The decoder, for receiving the second Soft Inform ation of first group of bit in N number of symbol from the first processor, second Soft Inform ation of first group of bit in N number of symbol is decoded, the third Soft Inform ation of first group of bit in N number of symbol is obtained, the third Soft Inform ation of first group of bit in N number of symbol is sent to the second processor；

The second processor, for receiving the third Soft Inform ation of first group of bit in N number of symbol from the decoder, the second Soft Inform ation of first group of bit in N number of symbol is received from the first processor, according to the second Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the first external information of first group of bit in N number of symbol is obtained, the first external information of first group of bit in N number of symbol is sent to the demodulator and the first processor；

The demodulator, it is also used to receive the first external information of first group of bit in N number of symbol from the second processor, according to the first external information of first group of bit in first symbol, and in first symbol other bits prior information, second group of bit in first symbol is demodulated, the first Soft Inform ation of second group of bit in first symbol is obtained, second group of bit includes the bit for belonging to second code word.
Equipment according to claim 13, which is characterized in that

The demodulator, it is also used to the demodulation mode according to second group of bit in first symbol, second second group of bit into n-th symbol is demodulated, the first Soft Inform ation of second group of bit in N number of symbol is obtained, by the prior information of second group of bit is sent to the first processor in the first Soft Inform ation and N number of symbol of second group of bit in N number of symbol；

The first processor, it is also used to receive the prior information of second group of bit in the first Soft Inform ation and N number of symbol of second group of bit in N number of symbol from the demodulator, according to the prior information of the first Soft Inform ation of second group of bit in N number of symbol and corresponding bit, second group is obtained in N number of symbol Second Soft Inform ation of second group of bit in N number of symbol is sent to the decoder and the second processor by the second Soft Inform ation of bit；

The decoder, it is also used to receive the second Soft Inform ation of second group of bit in N number of symbol from the first processor, second Soft Inform ation of second group of bit in N number of symbol is decoded, the third Soft Inform ation of second group of bit in N number of symbol is obtained, the third Soft Inform ation of second group of bit in N number of symbol is sent to the second processor.
Equipment according to claim 14, which is characterized in that

The second processor, it is also used to receive the third Soft Inform ation of second group of bit in N number of symbol from the decoder, the second Soft Inform ation of second group of bit in N number of symbol is received from the first processor, according to the second Soft Inform ation of the third Soft Inform ation of second group of bit in N number of symbol and corresponding bit, the first external information of second group of bit in N number of symbol is obtained, the first external information of second group of bit in N number of symbol is sent to the demodulator and the first processor；

The demodulator, it is also used to receive the first external information of second group of bit in N number of symbol from the second processor, according to the first external information of first group of bit and second group of bit in first symbol, and in first symbol other bits prior information, third group bit in first symbol is demodulated, obtain the first Soft Inform ation of third group bit in first symbol, wherein the third group bit includes the bit for belonging to third code word.
Equipment according to claim 13, which is characterized in that

The first processor obtains the second Soft Inform ation of first group of bit in first symbol specifically for allowing the first Soft Inform ation of first group of bit in first symbol to subtract the prior information of corresponding bit；

The second processor obtains the first external information of first group of bit in N number of symbol specifically for allowing the third Soft Inform ation of first group of bit in N number of symbol to subtract the second Soft Inform ation of corresponding bit.
3 to 15 described in any item equipment according to claim 1, which is characterized in that

In iteration for the first time, the prior information of each bit be each bit be 0 or be 1 probability log-likelihood ratio；

In non-iteration for the first time, the prior information of each bit is the first external information of the corresponding bit that last iteration obtains.
Equipment according to claim 13, which is characterized in that the L in N number of symbol The sum of the bit number of group bit is the integral multiple of code word size, wherein L is the positive integer no more than K.
Equipment according to claim 13, which is characterized in that

The equipment further include: deinterleaver, for receiving the second Soft Inform ation of first group of bit in N number of symbol from the first processor, second Soft Inform ation of first group of bit in N number of symbol is deinterleaved, the 4th Soft Inform ation of first group of bit in N number of symbol is obtained, the 4th Soft Inform ation of first group of bit in N number of symbol is sent to the decoder and the second processor；

The decoder is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from the deinterleaver, decodes to the 4th Soft Inform ation of first group of bit in N number of symbol, obtains the third Soft Inform ation of first group of bit in N number of symbol；

The second processor, it is also used to receive the 4th Soft Inform ation of first group of bit in N number of symbol from the deinterleaver, according to the 4th Soft Inform ation of the third Soft Inform ation of first group of bit in N number of symbol and corresponding bit, the second external information of first group of bit in N number of symbol is obtained.
Equipment according to claim 19, which is characterized in that

The equipment further include: interleaver, for receiving the second external information of first group of bit in N number of symbol from the second processor, second external information of first group of bit in N number of symbol is interleaved, the first external information of first group of bit in N number of symbol is obtained.
3 to 15 described in any item equipment according to claim 1, which is characterized in that the equipment further include: decision device and parallel-to-serial converter,

The decision device, for after the completion of last time iteration, from the decoder receive in N number of symbol first to K group bit third Soft Inform ation, in N number of symbol first to K group bit third Soft Inform ation is made decisions respectively, the road K discriminative information is obtained, the road K discriminative information is sent to the parallel-to-serial converter；

The parallel-to-serial converter carries out parallel-serial conversion processing to the road K discriminative information, recovers the first bit sequence for receiving the road K discriminative information from the decision device.
A kind of coded modulation equipment characterized by comprising deserializer, encoder, modulator and transmitter, wherein

The deserializer carries out serioparallel exchange to first bit sequence, obtains the road K bit sequence, the road K bit sequence is sent to the encoder, wherein K is positive integer for receiving the first bit sequence；

The encoder encodes the road K bit sequence respectively, obtains the road K codeword sequence, the road K codeword sequence is sent to the modulator for receiving the road K bit sequence from the deserializer；

The modulator takes at least one bit to be modulated, obtains symbol, the symbol is sent to transmitter for receiving the road K codeword sequence from the encoder in every road codeword sequence；

The transmitter sends the symbol for receiving the symbol from the modulator.
Equipment according to claim 22, which is characterized in that the equipment further include:

Interleaver is interleaved the road K codeword sequence respectively, obtains the codeword sequence after the road K interweaves, the codeword sequence after the road K is interweaved is sent to the modulator for receiving the road K codeword sequence from the encoder；

The modulator is also used to receive the codeword sequence after the road K interweaves from the interleaver, takes at least one bit to be modulated in the codeword sequence after every road interweaves, obtains symbol.
The equipment according to claim 22 or 23, which is characterized in that the bit in the symbol belongs to K different codeword sequences.
A kind of modulation demodulation system characterized by comprising

Demodulation coding equipment as described in any one of claim 13-21 and the coded modulation equipment as described in any one of claim 22-24.