CN108346642A - A kind of inductance stacked structure - Google Patents
A kind of inductance stacked structure Download PDFInfo
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- CN108346642A CN108346642A CN201810331302.5A CN201810331302A CN108346642A CN 108346642 A CN108346642 A CN 108346642A CN 201810331302 A CN201810331302 A CN 201810331302A CN 108346642 A CN108346642 A CN 108346642A
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- 239000002184 metal Substances 0.000 claims abstract description 90
- 229910052751 metal Inorganic materials 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005516 engineering process Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 241000237858 Gastropoda Species 0.000 claims 1
- 241001062009 Indigofera Species 0.000 claims 1
- 239000010437 gem Substances 0.000 claims 1
- 229910001751 gemstone Inorganic materials 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2871—Pancake coils
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
Abstract
The invention discloses a kind of inductance stacked structure, which includes：Substrate；At least two metal layers of substrate side are sequentially stacked on, every layer of metal layer includes at least the first planar inductor；Through-hole, between arbitrary neighborhood two metal layers, the first planar inductor in different metal layer is electrically connected by through-hole；Wherein, the thickness of through-hole is more than the thickness of metal layer.The present invention is by being arranged the metal layer that multilayer includes the first planar inductor, increase the inductance value of inductance in inductance stacked structure with this, and the through-hole for being more than metal layer thickness by thickness connects the first planar inductor in each metal layer, the interference between each first planar inductor can be reduced, compared with prior art, between the first planar inductor during different metal layer is not greatly reduced in the case of mutual inductance, the parasitic capacitance between different metal layer can be greatly reduced, inductance is set to maintain higher inductance value and quality factor when with smaller area, reduce the area of integrated circuit.
Description
Technical field
The present embodiments relate to integrated circuit technique more particularly to a kind of inductance stacked structures.
Background technology
Growing with electronic product, the research and development of all kinds of components are all sent out towards highly integrated, multi-functional direction
Exhibition, therefore, the requirement to the integrated circuit structure of device is also increasingly improving.
The design of inductance is often a problem in integrated circuit design.At this stage, the inductance in integrated circuit is usually
There are problems that two, one be inductance quality factor (i.e. Q values) it is relatively low, circuit performance can be influenced；The other is inductance area
It is larger, circuit level, size and cost of manufacture can be influenced.
Invention content
The present invention provides a kind of inductance stacked structure, higher in the quality factor and inductance inductance value for keeping inductance to realize
When, the area of inductance is smaller, reduces the purpose of integrated circuit area.
The present invention provides a kind of inductance stacked structures, including：Substrate；
At least two metal layers of the substrate side are sequentially stacked on, every layer of metal layer includes at least the first plane
Inductance；
Through-hole is located between metal layer described in two layers of arbitrary neighborhood, first plane electricity in the different metal layers
Sense is electrically connected by the through-hole；
Wherein, the thickness of the through-hole is more than the thickness of the metal layer.
Optionally, the first planar inductor serial or parallel connection in the different metal layers.
Optionally, the vertical throwing of first planar inductor in metal layer described in two layers of arbitrary neighborhood on the substrate
Shadow exists overlapping.
Optionally, first planar inductor in metal layer described in two layers of arbitrary neighborhood, which corresponds to overlapping part, has phase
Same current direction.
Optionally, further include the second planar inductor at least one layer of metal layer, second planar inductor with it is described
First planar inductor insulate, and vertical throwing of second planar inductor with any first planar inductor on the substrate
Shadow no overlap.
Optionally, first planar inductor is planar spiral structures.
Optionally, the through-hole includes metal column.
Optionally, the inductance stacked structure, further includes function element, the function element be located at the substrate with most
Between the metal layer of the substrate；
The function element includes at least one of transistor, diode, resistance, inductance, capacitance and acoustic wave device.
Optionally, the metal layer is prepared using electroplating technology.
Optionally, the material of the substrate is one kind in silicon, quartz, sapphire and glass.
The present invention provides a kind of inductance stacked structure, which includes：Substrate；It is sequentially stacked on substrate one
At least two metal layers of side, every layer of metal layer include at least the first planar inductor；Through-hole is located at arbitrary neighborhood two metal layers
Between, the first planar inductor in different metal layer is electrically connected by through-hole；Wherein, the thickness of through-hole is more than the thickness of metal layer
Degree.The present invention increases the sense of inductance in inductance stacked structure with this by the way that the metal layer that multilayer includes the first planar inductor is arranged
Value, and the through-hole by thickness more than metal layer thickness connects the first planar inductor in each metal layer, can reduce each first
Interference between planar inductor, compared with scheme in the prior art, in the first plane that different metal layer is not greatly reduced
Between inductance in the case of mutual inductance, the parasitic capacitance between different metal layer can be greatly reduced, make inductance with smaller
Higher inductance value and quality factor are maintained when area, can reduce the area of integrated circuit.
Description of the drawings
Fig. 1 is a kind of structural schematic diagram of inductance stacked structure provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of another inductance stacked structure provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of another inductance stacked structure provided in an embodiment of the present invention.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is a kind of structural schematic diagram of inductance stacked structure provided in an embodiment of the present invention.Referring to Fig. 1, the present invention is real
The inductance stacked structure of example offer is provided, including：Substrate 10；At least two metal layers 20 of 10 side of substrate are sequentially stacked on, often
Layer metal layer 20 includes at least the first planar inductor 21；Through-hole 30, between arbitrary neighborhood two metal layers 20, different metal
The first planar inductor 21 in layer 20 is electrically connected by through-hole 30；Wherein, the thickness of through-hole 30 is more than the thickness of metal layer 20.
Substrate 10 mainly plays a part of to support the metal layer 20 in the inductance stacked structure, optionally, the material of substrate 10
For one kind in silicon, quartz, sapphire and glass.It is understood that according to actual demand, the material of other materials may be used
Material forms substrate 10.
Metal layer 20 can be formed on the substrate 10, and optionally, metal layer 20 is prepared using electroplating technology.It needs to illustrate
It is that prepare metal layer 20 only using electroplating technology be a kind of specific example provided in this embodiment, other techniques can also be passed through
Prepare metal layer 20.
In integrated circuits, there is higher requirement to the setting of inductance, both requires in integrated circuit in some applications
Inductance has higher inductance value, and requires to reduce the area of integrated circuit, so as to realize Highgrade integration.
Under normal circumstances, it in order to obtain the inductance of higher quality factor (i.e. Q values), needs the first of different metal layer 20
Planar inductor 21 with the through-hole 30 of 21 analogous shape of the first planar inductor by being electrically connected so that the first of different metal layer 20 is flat
Face inductance 21 realizes parallel connection, that is, substantially improves the thickness of inductance coil, to achieve the purpose that put forward high q-factor.But
While 20 thickness of metal layer improves, the inductance value in unit area also declines therewith.Designer is just necessary in this case
To in unit area inductance value and Q values make choice.Then, the Synchronous lifting of inductance value and Q values how is realized in equal area
As a problem.
In order to reduce the area of integrated circuit and the inductance value and quality factor of inductance can be improved, be arranged on the substrate 10 to
Lack two layers of metal layer 20 for including the first planar inductor 21, mutual inductance can be generated between each first planar inductor 21, increases inductance
Inductance value.And in order to reduce the parasitic capacitance between each first planar inductor 21, pass through between each first planar inductor 21
Through-hole 30 connects, and the thickness of through-hole 30 is more than the thickness of metal layer 20, can make to have between each first planar inductor 21 compared with
High mutual inductance, while the parasitic capacitance being greatly reduced between two metal layers, to increase the inductance stacked structure inductance value and
Quality factor.
In order to avoid there is unnecessary electricity between each metal layer 20 and between through-hole 30 and each first planar inductor 21
It connects, insulating layer can be set between each metal layer 20, insulating layer can wrap up through-hole, to prevent from going out in the inductance stacked structure
Phenomena such as existing short circuit, it is ensured that the inductance stacked structure can be with normal operation.
It should be noted that in order to maintain the quality factor of inductance, it is ensured that the electric conductivity of the inductance stacked structure, through-hole
30 can form for the metal of high conductivity.Optionally, through-hole 30 includes metal column.Illustratively, through-hole 30 is copper post.
Inductance stacked structure provided in this embodiment, by being respectively provided with the first planar inductor in each layer metal layer, and it is logical
It crosses thickness and connects each first planar inductor more than the through-hole of metal layer thickness, it can be equal in the inductance value and quality factor for keeping inductance
When higher, do not increase the area of inductance, realizes the purpose for reducing integrated circuit area.
With continued reference to Fig. 1, optionally, the first planar inductor 21 is planar spiral structures.
It should be noted that planar spiral inductor is easily integrated, it is at low cost, therefore it is plane that the first planar inductor, which can be arranged,
Helical structure.But it is only a kind of specific example provided in this embodiment that the first planar inductor, which is planar spiral structures, not pair
The limitation of the application, the first planar inductor 21 can be the planar inductors of other shapes structure.
Optionally, 21 serial or parallel connection of the first planar inductor in different metal layer 20.
The first planar inductor 21 in each layer metal layer 20 can be attached by through-hole 30 according to actual needs, and each
Can be connected in series between one planar inductor 21, can be connected in parallel can also sections in series connection, part in parallel connection.
With continued reference to Fig. 1, when each first planar inductor 21 is connected, total inductance value is each first in the inductance stacked structure
The sum of the inductance value of planar inductor 21, then when needing that inductance value is larger in the inductance stacked structure, each first planar inductor 21 can go here and there
Connection connection.
Optionally, the upright projection of the first planar inductor 21 in arbitrary neighborhood two metal layers 20 on the substrate 10 exists
It is overlapping.
When the upright projection between the first planar inductor 21 on the substrate 10, which exists, to be overlapped, each metal layer 20 can be reduced
The area of upright projection on the substrate 10 reduces the area of substrate and the inductance stacked structure, reduction integrated circuit is realized with this
The purpose of area.
Optionally, it is having the same to correspond to overlapping part for the first planar inductor 21 in arbitrary neighborhood two metal layers 20
Current direction.
When having a certain distance between the first adjacent planar inductor 21, can be generated between the first planar inductor 21
Mutual inductance has overlapping region when adjacent 21 directions electric current I having the same of the first planar inductor, and in 10 direction of vertical substrate
When, the first adjacent planar inductor 21 has the magnetic field of the same direction, will increase by the magnetic flux of the first planar inductor 21, meeting
Increase the mutual inductance inductance value between the first planar inductor 21, increases total inductance value of the inductance stacked structure.
Illustratively, setting metal layer is two layers, and the area of metal layer is identical, is long 0.68mm, wide 0.74mm
When, the thickness that each metal layer is arranged is 6 μm.Through-hole thickness in the prior art is 2 μm, and in through-hole and two metal layers
First planar inductor is completely overlapped in the upright projection of substrate, i.e. two the first planar inductor uses are similar with the first planar inductor
The through-hole of shape is realized in parallel.The present embodiment uses thickness to connect two the first planar inductors for 20 μm of through-hole series winding, exemplary
Ground, through-hole are copper post, and two the first planar inductors is made to have the electric current (reference can be made to Fig. 1) of the same direction.
Table 1 is the inductance value and quality factor of the prior art and inductance in the present embodiment.
| Long (mm) | Wide (mm) | Area (mm2) | Inductance value (nH@1GHz) | Q values (@1GHz) | |
| The prior art | 0.68 | 0.74 | 0.5032 | 1.52 | 57.9 |
| The present embodiment | 0.68 | 0.74 | 0.5032 | 3.3 | 61.7 |
Note：The unit of inductance value is nH, and measurement frequency 1GHz, representation is nH@1GHz.Q value dimensionless, measurement frequency
For 1GHz, representation is@1GHz.
Referring to table 1, compared with setting structure in the prior art, in the present embodiment, the logical of metal layer is more than by thickness
Hole, which connects the first planar inductor in each metal layer, can greatly improve inductance inductance value in inductance stacked structure, and can tie up
The quality factor for holding inductance are basically unchanged.That is, technical solution provided in this embodiment, can maintain under identical area
When the quality factor of inductance are higher, the inductance value of inductance in inductance stacked structure is improved.
When table 2 is through-hole thickness difference, the inductance value and quality factor of the prior art and inductance in the present embodiment.
Wherein, in addition to through-hole thickness, each experiment parameter is identical as each experiment parameter in table 1 in table 2.
It should be noted that the thickness of through-hole has a certain impact to the performance tool of inductance in the present embodiment.Keep above-mentioned
Parameters are constant, only change the thickness of through-hole in the present embodiment, the thickness range of through-hole determined with this, to improve inductance
The performance of stacked structure.
When change through-hole thickness when, inductance inductance value and quality factor can change, when through-hole thickness with it is existing
When the thickness of through-hole is identical in technology, although inductance inductance value can be significantly increased, since parasitic capacitance is excessive, the quality of inductance
Factor, which has, to decline to a great extent.In order to maintain inductance inductance value and quality factor to all have higher numerical value, the thickness of through-hole can be set
Thickness of the degree more than metal layer.
Therefore, in the present embodiment, the thickness that through-hole need to be arranged is more than the thickness of metal layer, is ensured with this integrated in reduction
While circuit area, higher inductance inductance value and quality factor can be maintained.
Fig. 2 is the structural schematic diagram of another inductance stacked structure provided in an embodiment of the present invention.Referring to Fig. 2, optionally,
Further include the second planar inductor 22 at least one layer of metal layer 20, the second planar inductor 22 and the first planar inductor 21 insulate, and
Second planar inductor 22 and upright projection no overlap of any first planar inductor 21 in substrate.
When there are the second planar inductor 22 when two planar inductors, can be arranged with it to be located at together in same metal layer 20
It insulate between first planar inductor 21 of one metal layer 20, so as to respectively connect other elements, corresponding work(may be implemented
Can and it reduce interference.
It should be noted that in the vertical direction of substrate 10, when the first planar inductor 21 in adjacent metal 20 is same
When with the metal layer 20 in the first planar inductor 21 and the second planar inductor 22 there are when overlapping region, can be deposited between inductance
It is interfering with each other, is influencing the performance of the inductance stacked structure.Therefore, it in order to ensure the performance of the inductance stacked structure, needs to set
It sets and corresponds between the inductance in inductance stacked structure, i.e., the planar inductor in adjacent metal 20 can be with a plane electricity
The upright projection in substrate 20 is felt in the presence of overlapping, and avoids the first planar inductor 21 in same metal layer 20 and the second plane
Inductance 22 there is a situation where with the first planar inductor 21 in adjacent metal 20 in the upright projection of substrate 10 overlapping simultaneously.
Fig. 3 is the structural schematic diagram of another inductance stacked structure provided in an embodiment of the present invention.Referring to Fig. 3, optionally,
Inductance stacked structure further includes function element 40, function element 40 be located at substrate 10 and the metal layer 20 near substrate 10 it
Between；Function element 40 includes at least one of transistor, diode, resistance, inductance, capacitance and acoustic wave device.
It should be noted that function element 40 may be located on other positions, for example, between arbitrary two metal layers 20,
It is contemplated that function element 40 need be arranged in the preferable region of flat performance, therefore, can be disposed at substrate 10 with
Between the metal layer 20 of substrate 10.
Function element 40 can be set in inductance stacked structure, so as to realize certain preset function, Functional Unit
Part 40 can determine its concrete structure according to actual demand, function element be the elements such as transistor, capacitance or acoustic wave device only
It is the specific example of the present embodiment, this non-limitation to the application, function element can also be other elements, for example, chip etc..
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of inductance stacked structure, which is characterized in that including：
Substrate；
At least two metal layers of the substrate side are sequentially stacked on, every layer of metal layer includes at least the first plane electricity
Sense；
Through-hole is located between metal layer described in two layers of arbitrary neighborhood, and first planar inductor in the different metal layers is logical
Cross the through-hole electrical connection；
Wherein, the thickness of the through-hole is more than the thickness of the metal layer.
2. inductance stacked structure according to claim 1, which is characterized in that described first in the different metal layers is flat
Face inductance serial or parallel connection.
3. inductance stacked structure according to claim 1, which is characterized in that the institute in metal layer described in two layers of arbitrary neighborhood
The upright projection of the first planar inductor on the substrate is stated in the presence of overlapping.
4. inductance stacked structure according to claim 3, which is characterized in that the institute in metal layer described in two layers of arbitrary neighborhood
It states the first planar inductor and corresponds to overlapping part current direction having the same.
5. inductance stacked structure according to claim 1, which is characterized in that further include at least one layer of metal layer
Two planar inductors, second planar inductor insulate with first planar inductor, and second planar inductor and any institute
State the upright projection no overlap of the first planar inductor on the substrate.
6. inductance stacked structure according to claim 1, which is characterized in that first planar inductor is snail knot
Structure.
7. inductance stacked structure according to claim 1, which is characterized in that the through-hole includes metal column.
8. inductance stacked structure according to claim 1, which is characterized in that further include function element, the function element
Between the metal layer positioned at the substrate and near the substrate；
The function element includes at least one of transistor, diode, resistance, inductance, capacitance and acoustic wave device.
9. inductance stacked structure according to claim 1, which is characterized in that the metal layer is prepared using electroplating technology.
10. inductance stacked structure according to claim 1, which is characterized in that the material of the substrate is silicon, quartz, indigo plant
One kind in jewel and glass.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810331302.5A CN108346642A (en) | 2018-04-13 | 2018-04-13 | A kind of inductance stacked structure |
| PCT/CN2018/108197 WO2019196354A1 (en) | 2018-04-13 | 2018-09-28 | Inductor stack structure |
| US16/754,798 US11631516B2 (en) | 2018-04-13 | 2018-09-28 | Inductor stack structure |
| KR1020207010411A KR20200052359A (en) | 2018-04-13 | 2018-09-28 | Inductor stack structure |
| JP2020538816A JP2021510935A (en) | 2018-04-13 | 2018-09-28 | Inductor laminated structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810331302.5A CN108346642A (en) | 2018-04-13 | 2018-04-13 | A kind of inductance stacked structure |
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| CN108346642A true CN108346642A (en) | 2018-07-31 |
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| CN109215979A (en) * | 2018-10-17 | 2019-01-15 | 安徽安努奇科技有限公司 | A kind of patch type inductance and preparation method thereof |
| CN109361042A (en) * | 2018-11-16 | 2019-02-19 | 安徽安努奇科技有限公司 | A kind of frequency demultiplexer |
| CN109638000A (en) * | 2019-01-29 | 2019-04-16 | 安徽安努奇科技有限公司 | A kind of integrated inductance structure and integrated circuit |
| CN110247637A (en) * | 2019-07-09 | 2019-09-17 | 安徽安努奇科技有限公司 | A kind of filter circuit construction |
| WO2019196354A1 (en) * | 2018-04-13 | 2019-10-17 | 安徽云塔电子科技有限公司 | Inductor stack structure |
| WO2020155478A1 (en) * | 2019-01-29 | 2020-08-06 | 安徽安努奇科技有限公司 | Integrated inductor structure and integrated circuit |
| CN112953455A (en) * | 2021-02-22 | 2021-06-11 | 安徽安努奇科技有限公司 | Filter structure |
| US12094631B2 (en) | 2018-10-17 | 2024-09-17 | Anhui Anuki Technologies Co., Ltd. | Chip inductor and method for manufacturing same |
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